# Compensation for finite word length

## Subclass of:

## 708 - Electrical computers: arithmetic processing and calculating

## 708100000 - ELECTRICAL DIGITAL CALCULATING COMPUTER

## 708200000 - Particular function performed

## 708490000 - Arithmetical operation

## 708495000 - Floating point

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

708496000 | Compensation for finite word length | 24 |

708497000 | Round off or truncation | 21 |

20080215659 | Round for Reround Mode in a Decimal Floating Point Instruction - a round-far-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent rewound instruction is able to round the result to any number of digits fewer or equal, to the number of digits of the result using the saved tags. | 09-04-2008 |

20080215660 | Three-Term Input Floating-Point Adder-Subtractor - The three-term input floating-point adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent with a width of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, a carry save adder (CSA) which reduces the mantissas from the pre-processing circuit from three terms to two terms, a carry look-ahead adder (CLA) which carries out addition on the mantissas of the two terms, a normalization circuit which makes a left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent. | 09-04-2008 |

20090094308 | RELAXED REMAINDER CONSTRAINTS WITH COMPARISON ROUNDING - A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as addition, subtraction, multiplication, division and square root. For the division operation, the constraints for the remainder may be relaxed in order to reduce the area for look-up tables. An extra internal precision bit may not be used. Only one quotient may be calculated, rather than two, further reducing needed hardware to perform the rounding. Comparison logic may be required that may add a couple of cycles to the rounding computation beyond the calculation of the remainder. However, the extra latency is much smaller than a second FMAC latency. | 04-09-2009 |

20090172065 | Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even - Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P | 07-02-2009 |

20090172066 | Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away - Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P | 07-02-2009 |

20090259708 | APPARATUS AND METHOD FOR OPTIMIZING THE PERFORMANCE OF X87 FLOATING POINT ADDITION INSTRUCTIONS IN A MICROPROCESSOR - A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any conditions exist in the addends with respect to their contribution to a rounding determination and relative to the PC field. If none of the conditions exists, the FPU makes the rounding determination based on the smaller addend and the PC field, and selectively rounds the sum based on the rounding determination. If any conditions exist, the FPU saves the sum and rounding information derived from the addends, and signals the instruction dispatcher to re-dispatch the instruction. On re-dispatch, the FPU makes the rounding determination based on the saved rounding information and the PC field, and selectively rounds the sum based on the rounding determination. | 10-15-2009 |

20110055307 | METHOD FOR FLOATING POINT ROUND TO INTEGER OPERATION - An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and retrieves a binary source operand having an exponent of a fixed first number of bits and a mantissa of a fixed second number of bits. If the unbiased exponent value is greater than or equal to zero and less than the fixed second number, the FPU generates a mask having N consecutive ‘1’ bits beginning with the least significant bit and whose remaining bits have a value of ‘0’, where N is equal to the fixed second number minus the unbiased exponent value. The FPU computes a bitwise OR of the source operand with the mask, increments the result if the instruction is to round up, and computes a bitwise AND of the result with the inverse of the mask. | 03-03-2011 |

20110072066 | Apparatus and method for performing fused multiply add floating point operation - A fused multiply add floating point unit | 03-24-2011 |

20120011185 | ROUNDING UNIT FOR DECIMAL FLOATING-POINT DIVISION - A method for performing a decimal floating-point division, including: receiving, by a decimal floating-point divider, a decimal floating-point dividend and a decimal floating-point divisor; obtaining, by the decimal floating-point divider, a preliminary quotient having a first precision level, where the preliminary quotient is calculated from the decimal floating-point dividend and the decimal-floating point divisor; receiving, by the decimal floating-point divider, a rounding mode; selecting a rounding action based on the preliminary quotient and the rounding mode; and obtaining a rounded quotient having a second precision level by rounding the preliminary quotient according to the rounding action, where the first precision level is at least one digit greater than the second precision level. | 01-12-2012 |

20120041997 | FUSED MULTIPLY-ADD ROUNDING AND UNFUSED MULTIPLY-ADD ROUNDING IN A SINGLE MULTIPLY-ADD MODULE - A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated. | 02-16-2012 |

20120191767 | Circuit which Performs Split Precision, Signed/Unsigned, Fixed and Floating Point, Real and Complex Multiplication - An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated. | 07-26-2012 |

20120259903 | ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT - An arithmetic circuit for rounding pre-rounded data includes a first register to store first-format pre-rounded data that includes a mantissa of a fixed-precision floating-point number using a base-N numbering system, and includes an exponent for the mantissa, a second register to store rounding precision data indicative of precision for rounding the pre-rounded data, a leading zero counting unit to count consecutive zeros starting from a most significant bit of the mantissa stored in the first register, an exponent generating unit to generate a post-round exponent indicative of an exponent for a rounded significant by subtracting the number of zeros counted by the leading zero counting unit and the rounding precision data from a sum of one and the exponent stored in the first register, and an output register to store the post-round exponent and a rounding-add value that is to be added to a digit at which rounding is performed. | 10-11-2012 |

20130191433 | PERFORMING ROUNDING OPERATIONS RESPONSIVE TO AN INSTRUCTION - In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed. | 07-25-2013 |

20130226981 | Round for Reround Mode in a Decimal Floating Point Instruction - A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags. | 08-29-2013 |

20130304785 | APPARATUS AND METHOD FOR PERFORMING A CONVERT-TO-INTEGER OPERATION - A data processing apparatus includes processing circuitry for performing a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value. The convert-to-integer operation uses round-to-nearest, ties away from zero, rounding (RNA rounding). The operation is performed by generating an intermediate value based on the floating-point value, adding a rounding value to the intermediate value to generate a sum value, and outputting the integer-valued bits of the sum value as the rounded two's complement integer value. If the floating-point value is negative, then the intermediate value is generated by inverting the bits without adding a bit value of 1 to a least significant bit of the inverted value. | 11-14-2013 |

20130304786 | DEVICE AND METHOD FOR COMPUTING A FUNCTION VALUE OF A FUNCTION - A device is provided for computing a function value of a function F. The device includes a memory, a truncator unit, a selector unit, and an evaluator unit. The memory contains a look-up table comprising a set of entries, each entry having associated with it a domain and an approximation function for approximating F on the associated domain. The truncator unit is arranged to truncate or round a first value X1 to generate a second value X2. The selector unit is arranged to select an entry of the lookup-table according to the second value X2, thus selecting the approximation function that is associated with the selected entry. The evaluator unit is arranged to determine the function value of the selected approximation function at the first value X1. | 11-14-2013 |

20140181169 | METHOD, APPARATUS, SYSTEM FOR SINGLE-PATH FLOATING-POINT ROUNDING FLOW THAT SUPPORTS GENERATION OF NORMALS/DENORMALS AND ASSOCIATED STATUS FLAGS - A mechanism for performing single-path floating-point rounding in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprises a floating point unit (FPU) to generate a plurality of status flags for a rounded value of a finite nonzero number. The plurality of status flags are generated based on the finite nonzero number without calculating the rounded value of the finite nonzero number. The plurality of status flags comprises an overflow flag and an underflow flag. The FPU determines whether a rounded value should be calculated for the finite nonzero number based on the plurality of status flags and whether the overflow flag is asserted. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is asserted, the FPU calculates the rounded value of the finite nonzero number based on an overflow rounding. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is not asserted, the FPU calculates the rounded value of the finite nonzero number based on a blended reduced precision rounding. | 06-26-2014 |

20160011855 | CHECK PROCEDURE FOR FLOATING POINT OPERATIONS | 01-14-2016 |

20160070536 | FLOATING-POINT ARITHMETIC DEVICE, SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM - A floating-point arithmetic device of an embodiment includes: a first functional unit configured to receive first input data to execute first arithmetic operation in a first rounding mode; a second functional unit configured to receive second input data to execute second arithmetic operation in a second rounding mode; a first output circuit capable of selectively outputting a first output or a first arithmetic operation result of the first arithmetic operation, the first output obtained by halving a first value obtained by adding a second arithmetic operation result of the second arithmetic operation to the first arithmetic operation result; and a second output circuit capable of selectively outputting a second output or the second arithmetic operation result, the second output obtained by halving a second value obtained by subtracting the second arithmetic operation result from the first arithmetic operation result. | 03-10-2016 |

20160070538 | Round For Reround Mode In A Decimal Floating Point Instruction - A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags. | 03-10-2016 |

20160092167 | ROUNDING FLOATING POINT NUMBERS - Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and denormal inputs and outputting normal and denormal results, and where a rounding module is used advantageously to reduce operational latency of the circuit. | 03-31-2016 |

708498000 | Overflow or underflow | 2 |

20090292754 | METHOD AND SYSTEM FOR AVOIDING UNDERFLOW IN A FLOATING-POINT OPERATION - Methods and systems for detecting underflow in a floating-point operation are disclosed. In accordance with an example disclosed method a plurality of comparator circuits and a plurality of logic devices coupled to the plurality of comparator circuits are operated to determine whether performing a floating-point operation using a floating-point hardware unit will generate an underflow condition. The operating of the plurality of comparator circuits and the logic devices involves inputting a multiply-add operation result value to at least some of the plurality of comparator circuits. In addition, a plurality of logic outputs are outputted via the plurality of logic devices. The plurality of logic outputs are indicative of comparison operations performed by at least some of the comparator circuits based on the multiply-add operation result value. An underflow indicator is outputted based on the plurality of logic outputs. The underflow indicator is indicative of whether performing the floating-point operation using the floating-point hardware unit will generate the underflow condition. | 11-26-2009 |

20160124714 | EXCEPTION GENERATION WHEN GENERATING A RESULT VALUE WITH PROGRAMMABLE BIT SIGNIFICANCE - A data processing system performs processing operations upon input operand(s) having a programmable bit significance. Exception generating circuitry generates exception indications representing exceptions such as overflow, underflow and inexact in respect of a result value having the programmable bit significance. | 05-05-2016 |

708499000 | Sticky bit | 1 |

20130007084 | FLOATING-POINT ADDER - Floating point adder circuitry | 01-03-2013 |