| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708505000 | Addition or subtraction | 23 |
| 20080263121 | METHOD AND SYSTEM FOR OPTIMIZING FLOATING POINT CONVERSION BETWEEN DIFFERENT BASES - A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c | 10-23-2008 |
| 20080263122 | MULTI-FUNCTION FLOATING POINT ARITHMETIC PIPELINE - A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product on data in a single pass through the datapath, which allows matrix transformations to be computed in an efficient manner, with a high data throughput and without substantially increasing the cost and amount of hardware required to implement the pipeline. | 10-23-2008 |
| 20080270507 | DECOMPOSITION OF DECIMAL FLOATING POINT DATA, AND METHODS THEREFOR - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 10-30-2008 |
| 20080307030 | GENERATION OF TEST CASES WITH RANGE CONSTRAINTS FOR FLOATING POINT ADD AND SUBTRACT INSTRUCTIONS - Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that | 12-11-2008 |
| 20090112960 | System and Method for Providing a Double Adder for Decimal Floating Point Operations - A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The calculating is performed by a plurality of adder blocks. Output from the calculating includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The sums of the corresponding digits and the carry out indicators in a carry chain are stored in an intermediate result register. Each of the sums in the intermediate result register is incremented by one. A selection between each of the sums and the sums incremented by one is performed. Input to the selecting includes the carry chain, and the output from the selecting includes a final sum of the first operand and the second operand. The final sum is stored in an output register. | 04-30-2009 |
| 20090132627 | Method for Performing Decimal Floating Point Addition - A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second register. An operation, either addition or subtraction, associated with the first operand and the second operand is received. Three concurrent calculations are performed on the first operand and the second operand. The three concurrent calculations include: applying the operation to the first operand and the second operand based on a first assumption; applying the operation to the first operand and the second operand based on a second assumption; and applying the operation to the first operand and the second operand based on a third assumption. A final result is selected from the first result, the second result and the third result. | 05-21-2009 |
| 20090210472 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR IDENTIFYING DECIMAL FLOATING POINT ADDITION OPERATIONS THAT DO NOT REQUIRE ALIGNMENT, NORMALIZATION OR ROUNDING - A method, computer program product and a system for identifying decimal floating point addition operations that guarantee operand alignment and do not require alignment, normalization or rounding are provided. The method includes: receiving an instruction to perform an addition of a first operand and a second operand; extracting a first exponent (EXP) and a first most significant digit (MSD) from the first operand; extracting a second EXP and a second MSD from the second operand; and determining whether alignment between the first operand and the second operand is guaranteed, based on the first EXP, the first MSD, the second EXP and the second MSD. | 08-20-2009 |
| 20100023574 | FLOATING-POINT ADDITION ACCELERATION - Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods. | 01-28-2010 |
| 20100312812 | Decimal Floating-Point Adder with Leading Zero Anticipation - A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain. | 12-09-2010 |
| 20110320514 | DECIMAL ADDER WITH END AROUND CARRY - Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps. | 12-29-2011 |
| 20120239719 | Floating-Point Addition Acceleration - Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods. | 09-20-2012 |
| 20120259905 | ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT - An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit. | 10-11-2012 |
| 20120259906 | ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT - An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision. | 10-11-2012 |
| 20130103732 | Circular Floating-Point Number Generator and a Circular Floating-Point Number Adder - One aspect of the present invention will provide a circular floating-point number generator (400) for generating, from an input fixed-point number, a circular floating-point number including sign-bit field (S), exponent field (E), and circular-mantissa field (M). The generator assigns the input bits in the fixed-point number to a plurality of slots, generates the sign-bit field (S), generate the exponent field (E) based on a bit position of a leading significant bit, and generate the mantissa field (M) by extracting a first bit group and a second bit group and by providing a start bit of the first bit group after a last bit of the second bit group. | 04-25-2013 |
| 20130297666 | FPGA-BASED HIGH-SPEED LOW-LATENCY FLOATING POINT ACCUMULATOR AND IMPLEMENTATION METHOD THEREFOR - This invention discloses a FPGA based high-speed low-latency floating-point accumulation and its implementation method. Floating accumulation of this invention comprises a floating-point adder unit, numerous intermediate result buffers, an input control unit and an output control unit. The floating-point accumulation implementation method of this invention is used for gradation of the whole accumulation calculation process to ensure cross execution of accumulation calculation processes and graded storage of intermediate results of accumulation calculation at different levels; meanwhile, the operation in the mode of pure flow line can significantly improve utilization rate of internal floating-point adder, and maintain relatively low latency to output of final results of floating-point accumulation calculation. This invention is expected to improve utilization rate of floating-point adder through dynamic allocation of input data in internal floating-point adder unit, and thereby maintains higher arithmetic speed and relatively low latency while ensuring minimized consumption of logic or DSP resources as required. | 11-07-2013 |
| 20140046994 | OPERATION CIRCUIT AND CONTROL METHOD OF OPERATION CIRCUIT - An operation circuit includes: a register that holds a decimal floating point number of a DPD (densely-packed decimal) format having a sign field, a combination field and a succeeding mantissa field; a first logical operation circuit that performs an operation including an exclusive logical sum operation and a modulo operation on values of the combination field; a second logical operation circuit that performs an operation including an exclusive logical sum operation and a modulo operation on values of the succeeding mantissa field; and a third logical operation circuit that performs a logical operation on a value of the sign field, an operation result of the first logical operation circuit and an operation result of the second logical operation circuit. | 02-13-2014 |
| 20140074903 | Dual-Path Fused Floating-Point Add-Subtract - A fused floating-point add-subtract unit includes far path logic, close path logic, and selection logic. The far path logic is configured to perform addition and subtraction operations on first and second significands of first and second operands, respectively, to produce a far path sum and a far path difference. The close path logic is configured to perform addition and subtraction operations on the first and second significands of the first and second operands, substantially concurrently with the addition and subtraction operations of the far path logic, to produce a close path sum and a close path difference. The selection logic selectively provides one of the far path sum and the close path sum as a significand of a sum output and one of the far path difference and the close path difference as a significand of a difference output. | 03-13-2014 |
| 20140172936 | FLOATING-POINT ERROR DETECTION AND CORRECTION - An embodiment includes a method for detecting a potential floating-point error in an addition or a subtraction instruction included in an operation. The method may include identifying a first operand and a second operand. The first operand and the second operand may be configured to be manipulated during execution of the instruction. The method may include copying a first exponent of the first operand to a first comparison register. The method may also include copying a second exponent of the second operand to a second comparison register. The method may further include comparing the first exponent in the first comparison register to the second exponent in the second comparison register. Based on the comparison, a determination may be made whether the instruction includes a potential floating-point error when executing the instruction using the first operand and the second operand formatted according to a first precision. | 06-19-2014 |
| 20150019609 | MODAL INTERVAL PROCESSOR - A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register. | 01-15-2015 |
| 20150142864 | HIGH PERFORMANCE FLOATING-POINT ADDER WITH FULL IN-LINE DENORMAL/SUBNORMAL SUPPORT - According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating point operands. | 05-21-2015 |
| 20160110162 | NON-RECURSIVE CASCADING REDUCTION - As disclosed herein a method, executed by a computer, for conducting non-recursive cascading reduction includes receiving a collection of floating point values, using a binary representation of an index corresponding to a value being processed to determine a reduction depth for elements on a stack to be accumulated, and according to the reduction depth, iteratively conducting a reduction operation on the current value and one or more values on the stack. In addition to accumulation, the reduction operation may include transforming the value with a corresponding function. The method may also include using a SIMD processing environment to further increase the performance of the method. The method provides results with both high performance and accuracy. A computer system and computer program product corresponding to the method are also disclosed herein. | 04-21-2016 |
| 20160139882 | ACCURACY-CONSERVING FLOATING-POINT VALUE AGGREGATION - A method for enhancing an accuracy of a sum of a plurality of floating-point numbers. The method receives a floating-point number and generates a plurality of provisional numbers with a value of zero. The method further generates a surjective map from the values of an exponent and a sign of a mantissa to the provisional numbers in the plurality of provisional numbers. The method further maps a value of the exponent and the sign of the mantissa to a first provisional number with the surjective map. The method further generates a test number from the first provisional number and if the test number exceeds a limit, modifies a second provisional number by using at least part of the test number. The method further equates the first provisional number to the test number if the test number does not exceed the limit. The method further sums the plurality of provisional numbers. | 05-19-2016 |
| 20160378432 | Handling Instructions that Require Adding Results of a Plurality of Multiplications - Floating point compound equations that involve addition of at least three terms, where each term involves a multiplication, can be implemented by using a bypass to prevent small, remaining values from being lost when shifted. | 12-29-2016 |
