| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708500000 | Evaluation of root | 6 |
| 20080288571 | ARITHMETIC DEVICE FOR PERFORMING DIVISION OR SQUARE ROOT OPERATION OF FLOATING POINT NUMBER AND ARITHMETIC METHOD THEREFOR - When division X/Y of floating point numbers is performed, bit string data of a mantissa x including a fraction xf of X or a mantissa y including a fraction yf of Y is shifted in accordance with magnitude relation between them to perform a fraction computation. Thereby, a fraction division result in which the position of the most significant bit is fixed at a prescribed digit is generated. When a square root operation √Y is performed, a fraction square root operation result in which the position of the most significant bit is fixed at a prescribed digit is generated by an exception handling if all of the three conditions that all the bits in the fraction of Y are one, a difference between the exponent ye of Y and a bias value b is an odd number, and a rounding mode is a positive infinity direction are satisfied. | 11-20-2008 |
| 20090216822 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING FLOATING POINT SQUARE ROOT OPERATION RESULTS - A method, system and computer program product for verifying a result of a floating point square root operation is provided. The method includes: receiving a result of a floating point square root operation for an operand; performing a comparison of a magnitude of a least significant bit (LSB) of the operand and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison. | 08-27-2009 |
| 20090248777 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR HARDWARE ASSISTS FOR MICROCODED FLOATING POINT DIVIDE AND SQUARE ROOT - Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root operations. Exemplary embodiments include a method including receiving a first microcoded instruction in the pipeline, decoding the first microcoded instruction in a decode stage of the pipeline, initiating a microcode engine coupled to the processor, with the microcode engine configured to process the streamlined microcode routine. During the delay between detecting the need to start a microcode routine and seeing the first microcode instruction actually issued, and using the processor cycle intended for the original instruction, hardware prepares for the microcode by pre-normalizing the operand, writing the pre-normalized operand to a scratch register coupled to the processor, conditionally generating a final result and discarding microcode routine instructions subsequent to the first microcode routine instruction and copying a final result from the scratch register to a floating point architectural register associated with the processor. | 10-01-2009 |
| 20120226730 | System and Method for Testing Whether a Result is Correctly Rounded - A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case. | 09-06-2012 |
| 20140052767 | APPARATUS AND ARCHITECTURE FOR GENERAL POWERING COMPUTATION - An apparatus for general powering computation is disclosed. The apparatus is capable of computing a powering function of a floating-point number with an unrestricted exponent. The unrestricted exponent can be a fixed-point or a floating-point exponent. Additionally, the unrestricted exponent can be an inverse of a number in order to enable for q-th root computation using the same hardware processor and architecture. | 02-20-2014 |
| 20160026437 | APPARATUS AND METHOD FOR PERFORMING FLOATING-POINT SQUARE ROOT OPERATION - A data processing apparatus has a processing circuitry for performing a floating-point square root operation on a radicand value R to generate a result value. The processing circuitry has first square root processing circuitry for processing radicand values R which are not an exact power of two and second square root processing circuitry for processing radicand values which are an exact power of 2. Power-of-two detection circuitry detects whether the radicand value is an exact power of two and selects the output of the first or second square root processing circuitry as appropriate. This allows the result to be generated in fewer processing cycles when the radicand is a power of 2. | 01-28-2016 |
