Entries |
Document | Title | Date |
20080204102 | METHOD TO REGULATE PROPAGATION DELAY OF CAPACITIVELY COUPLED PARALLEL LINES - Capacitive coupling between adjacent parallel lines in an integrated circuit is made more uniform and allows for better timing control of the lines through the use of inverters placed on one or both of the adjacent interconnect lines. By staggering the placement of inverters along adjacent lines, constructive and destructive coupling terms between the lines are balanced out. The propagation delay through the inverter is made less than the propagation delay through one half of the line length of the corresponding line. | 08-28-2008 |
20080224749 | SYSTEM AND METHOD FOR PROVIDING STABLE CONTROL FOR POWER SYSTEMS - System and method for providing stable control for power systems. According to an embodiment, the present invention provides an apparatus for providing one or more control signals for a power system. The apparatus includes an input terminal for receiving an electrical energy, which can be characterized by a first input voltage. The apparatus includes a control component that is configured to generate a first control signal based on at least information associated with the first input voltage. The apparatus additionally includes an output terminal for sending the first control signal. Moreover, the apparatus includes a timing component that is coupled to the control component. The control component is configured to process at least information associated with a first value of the first input voltage at a first time and a first reference voltage and to generate a second control signal. | 09-18-2008 |
20080258791 | DIRECT DIGITAL SYNTHESIZER WITH VARIABLE REFERENCE FOR IMPROVED SPURIOUS PERFORMANCE - Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements. | 10-23-2008 |
20080265966 | INTEGRATED CIRCUIT WITH A PROGRAMMABLE DELAY AND A METHOD THEREOF - An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed. | 10-30-2008 |
20090015307 | LOCAL SKEW DETECTING CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermineddelay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal. | 01-15-2009 |
20090015308 | EFFICIENT DELAY ELEMENTS - Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths. | 01-15-2009 |
20090058487 | DELAY CIRCUIT - A delay circuit controls a delay time according to variation of a power supply voltage. In the delay circuit, the capacitance of a capacitor connected in parallel to the delay line is changed according to the change of the power supply voltage. Alternatively, a current is made to flow through one path selected from a plurality of paths having different resistance between the input and the output of the delay line. Accordingly, the delay time can be independently controlled or adjusted by greatly changing the time taken to pass through the delay line according to the change of the power supply voltage. | 03-05-2009 |
20090108899 | DYNAMIC VOLTAGE SCALING FOR SELF-TIMED OR RACING PATHS - A timing-constrained circuit (e.g., a self-timed circuit) of optimal performance is achieved by allowing the delay of the circuit to be changed dynamically as a function of operating conditions (e.g., operating voltages or temperatures). The delay of timing signals in the timing-constrained circuit for a given operating condition may be selected to have the minimum margin for that operating condition among the available delays to maximize performance over the entire dynamic range of operating conditions. | 04-30-2009 |
20090108900 | APPARATUS AND METHOD FOR OPTIMIZING DELAY ELEMENT IN ASYNCHRONOUS DIGITAL CIRCUITS - A computer readable storage medium includes executable instructions to construct a delay element to replicate the timing of critical gates and paths within a segment of an asynchronous circuit. The rise and fall delay mismatch of the delay element is minimized without obeying timing constraints. The position of each output of the delay element is determined to include a globally shared node within the segment and a non-shared local node in the segment. | 04-30-2009 |
20090108901 | PULSE GENERATION CIRCUIT AND UWB COMMUNICATION DEVICE - A pulse generation circuit for outputting to an output terminal (OT) includes an inverter delay circuit (IDC) for processing a start signal with a predetermined delay; a first switching circuit (SC) adapted to connect the OT to a first voltage when a logical product of the IDC is true, and to connect the OT to a second voltage when a logical sum of the IDC is false; a second SC adapted to connect the OT to the first voltage when a logical product of the IDC is true, and to connect the OT to the second voltage when a logical sum of the IDC is false; and a start signal control circuit adapted to input the start signal to the IDC with a delay when the first SC is activated, and to input the start signal to the IDC without the delay when the second SC is activated. | 04-30-2009 |
20090115484 | DIGITALLY CONTROLLED DELAY ELEMENT - Techniques and corresponding circuits for achieving programmable delay with linear resolution are provided. The techniques provide for incremental delay with substantially equal increments. Linear resolution may be achieved through the use of a circuit arrangement that allows current to be controlled to linearly vary effective resistance of a delay circuit, without affecting the effective capacitance. | 05-07-2009 |
20090153213 | METHOD FOR REDUCING DELAY DIFFERENCE OF DIFFERENTIAL TRANSMISSION AND SYSTEM THEREOF - The present invention discloses a system and method for reducing delay difference of differential transmission, a certain delay difference between waveforms of the P signal and N signal is generated through controlling delay adjustment to P signal or N signal of the differential signals and controlling delay adjustment value simultaneously, to compensate for the delay difference of differential transmission due to the channels. Therefore, the present invention can reduce the delay difference of differential transmission due to property discrepancy of board materials and delay inconsistency among pins of the connectors, and at same time simplify the scheme design. | 06-18-2009 |
20090160519 | PROGRAMMABLE DELAY CIRCUIT WITH INTEGER AND FRACTIONAL TIME RESOLUTION - A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path. | 06-25-2009 |
20090167398 | PULSE SIGNAL DELAY CIRCUIT AND LED DRIVE CIRCUIT - A pulse signal delay circuit comprises: a first pulse edge delay circuit for generating a first delay timing signal for sequentially outputting a first edge detection delay timing gained by detecting the rising edge of an input pulse signal and delaying the detection timing by a constant delay time a predetermined number of times; a second pulse edge delay circuit for generating a second delay timing signal for sequentially outputting a second edge detection delay timing gained by detecting the falling edge of the input pulse signal and delaying the detection timing by the delay time the number of times; and a delay pulse signal generating circuit for generating and outputting delay pulse signals rising and falling according to the first and second edge detection delay timings, respectively, from the first and second delay timing signals, the first and second edge detection delay timings delayed the same number of times. | 07-02-2009 |
20090189666 | JITTER INJECTION CIRCUIT, PATTERN GENERATOR, TEST APPARATUS, AND ELECTRONIC DEVICE - Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal. | 07-30-2009 |
20090189667 | JITTER INJECTION CIRCUIT, PATTERN GENERATOR, TEST APPARATUS, AND ELECTRONIC DEVICE - Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that are connected in a cascading manner and that each sequentially delay a supplied reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal. | 07-30-2009 |
20090212837 | Circuit, apparatus and method of transmitting signal - A circuit includes a first wiring to transmit a first signal, an alteration element to adjust a delay amount being added to the first wiring, and a shield element to shield the alteration element from a second wiring, the second wiring transmitting a second signal. | 08-27-2009 |
20090231010 | INPUT LATCH CIRCUIT HAVING FUSES FOR ADJUSTING A SETUP AND HOLD TIME - An input latch circuit of a semiconductor device includes a setup time adjusting unit configured to selectively delay a clock signal and a hold time adjusting unit configured to selectively delay an input signal. The input latch circuit also includes a latch unit configured to latch an output signal of the hold time adjusting unit according to an output signal of the setup time adjusting unit. The input latch circuit changes and delays the clock signal and the input signal by cutting a fuse within the setup time adjusting unit and the hold time adjusting unit without requiring a change to a circuit in order to adjust a setup time and a hold time. | 09-17-2009 |
20090261878 | METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE - Various methods and apparatus can be used for amplifying a time interval in a variety of applications. In an embodiment, a feedback device is implemented in a time amplifier in conjunction with an output device of the time amplifier. | 10-22-2009 |
20090261879 | VOLTAGE AND TEMPERATURE COMPENSATION DELAY SYSTEM AND METHOD - A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that receives the delayed output signal of the first delay stage, and generates a delayed output signal from the output of the first delay stage. The first delay stage and the second delay stage are coupled a voltage supply. The magnitude of the delay of the second delayed signal is inversely proportional to the magnitude of the supply voltage to substantially the same degree that the delayed output signal of the first delay stage is proportional to the magnitude of the supply voltage. | 10-22-2009 |
20090309642 | SIGNAL DELAY DEVICES, CLOCK DISTRIBUTION NETWORKS, AND METHODS FOR DELAYING A SIGNAL - In one aspect, a signal delay device includes an inverter circuit, a positive feedback circuit, and a programmable element. The inverter circuit is connected between an input node and an output node, and the positive feedback circuit is connected between the output node and the inverter circuit. The programmable element controls the positive feedback circuit to set a voltage transfer characteristic from the input node to the output node. | 12-17-2009 |
20100001777 | Flash Time Stamp Apparatus - One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is connected to a data input on a latch. An event signal input is connected to an enable input on each of the latches. An output of each of the latches is connected to the time stamp output. The apparatus is adapted to produce a value on the time stamp output indicating a point at which the event signal input transitions between transitions on the clock input. | 01-07-2010 |
20100039154 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit comprises: a first signal delay circuit including a first precharge element configured to precharge a first node with a leakage current and a first signal output circuit configured to output a first signal; a second signal delay circuit including a second precharge element configured to precharge a second node with a leakage current and a second signal output circuit configured to output a second signal. The first signal delay circuit is configured to discharge the first node via a first discharge element, while the second signal delay circuit precharges the second node via the second precharge element and outputs the second signal. The second signal delay circuit is configured to discharge the second node via a second discharge element, while the first signal delay circuit precharges the first node via the first precharge element and outputs the first signal. | 02-18-2010 |
20100052758 | Stage by stage delay current-summing slew rate controller - A stage by stage delay current-summing slew rate controller includes a delay controller, a delay cell array, a current source array, a switch array, a load. The delay cell array includes N delay cells, the switch array includes N switches, and the switch includes N current sources, wherein N>1. The delay controller is connected with the control ports of the delay cells respectively, and the delay cells are connected with the control terminal of the switches respectively. One of the connecting terminals of the switch is connected with the output end of the current source, and the other end of the connecting terminals of the switch is connected with one end of the load, and the other end of the load is connected to the ground. | 03-04-2010 |
20100127746 | Digitally Controlled CML Buffer - Techniques and corresponding circuits for achieving programmable delay of a current mode logic delay buffer are provided. The techniques provide for incremental delay with substantially equal increments Delay may be achieved through the use of a circuit arrangement that allows biasing current to be controlled effect the response time of the circuit by digital control. | 05-27-2010 |
20100141323 | DELAY LINE - A delay line has a high response speed by minimizing the amount of loading on an input node and an output node while delaying an input signal over a wide variation range. The delay line includes a forward delay unit configured to determine the length of a forward delay path passing an input signal in response to a delay control code, a reverse delay unit configured to receive an output signal of the forward delay unit, and to output a delayed input signal through a reverse delay path that is as long as the length of the forward delay path determined by the delay control code, and a transfer unit configured to transfer the output signal of the forward delay unit from a turn point determined by the delay control code to the reverse delay unit. | 06-10-2010 |
20100164583 | Method and System for Setup/Hold Characterization in Sequential Cells - An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell. | 07-01-2010 |
20100237923 | Method of placing delay units of pulse delay circuit on programmable logic device - A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string. | 09-23-2010 |
20100244919 | DIGITAL SUPPRESSION OF SPIKES ON AN I2C BUS - An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I | 09-30-2010 |
20100244920 | DELAY CIRCUIT - A delay circuit includes first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto; and a delay control unit configured to control selectively applying an input signal to the first selective delay stage or the second selective delay stage in response to a code combination of first and second selection signals and produce an output signal. | 09-30-2010 |
20100271099 | FINE GRAIN TIMING - A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain. | 10-28-2010 |
20110102043 | REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT - A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary. | 05-05-2011 |
20110156790 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DETERMINING DELAY AMOUNT USING THE SAME - A semiconductor integrated circuit includes: a first node through which an input signal passes; an adjustment block including at least one delay unit electrically connected to the first node; and
| 06-30-2011 |
20110175658 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING VOLTAGE CONTROL METHOD - A semiconductor integrated circuit includes a first circuit part that is designed under a first corner condition with respect to a process variation, a second circuit part that is designed under a second corner condition narrower than the first condition, and a control part that changes an operating voltage supplied to the first circuit part and the second circuit part according to a delay amount of the first circuit part, and starts the second circuit part when a delay characteristic caused by a change in the operating voltage conforms to a delay characteristic under the second corner condition. | 07-21-2011 |
20110175659 | Generating a time delayed event - A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times there between. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage. | 07-21-2011 |
20110260766 | DIGITAL SUPPRESSION OF SPIKES ON AN I2C BUS - An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I | 10-27-2011 |
20110291729 | Hardware performance monitor (HPM) with extended resolution for adaptive voltage scaling (AVS) systems - An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays. | 12-01-2011 |
20120068752 | Systems and Methods for Low Latency Noise Cancellation - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period. | 03-22-2012 |
20120235724 | Interface for MEMS inertial sensors - In a high-performance interface circuit for micro-electromechanical (MEMS) inertial sensors, an excitation signal (used to detect capacitance variation) is used to control the value of an actuation signal bit stream to allow the dynamic range of both actuation and detection paths to be maximized and to prevent folding of high frequency components of the actuation bit stream due to mixing with the excitation signal. In another aspect, the effects of coupling between actuation signals and detection signals may be overcome by performing a disable/reset of at least one of and preferably both of the detection circuitry and the MEMS detection electrodes during actuation signal transitions. In a still further aspect, to get a demodulated signal to have a low DC component, fine phase adjustment may be achieved by configuring filters within the sense and drive paths to have slightly different center frequencies and hence slightly different delays. | 09-20-2012 |
20120249205 | Semiconductor Device, a Method of Improving a Distortion of an Output Waveform, and an Electronic Apparatus - Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure. | 10-04-2012 |
20120293226 | CLOCK AND DATA RECOVERY SYSTEM, PHASE ADJUSTING METHOD, AND PHASEDETECTOR - Disclosed is a phase discriminator, including: a first XOR gate connected to a trigger and a delay unit, a second XOR gate connected to the trigger and a latch, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first offset current source circuit outputting a first adjustable offset circuit for controlling amplitude of the error signal output by the first XOR gate; and/or, the second XOR gate is a current mode logic XOR gate, the second XOR gate comprises a second offset current source circuit outputting a second adjustable offset circuit for controlling amplitude of reference signal output by the second XOR gate. Also disclosed are a clock and data recovery system and a phase adjustment method. The present invention can prevent introducing noise coupling to the voltage control oscillator (VCO) module. | 11-22-2012 |
20130002330 | Systems and Methods for Crossover Delay to Prevent Power Module Faults - Systems and methods detect when a transition from a first power module to a second power module is taking place and generates a lockout pulse when the transition is detected. The lockout pulse initiates the blocking of a predetermined number of gate pulses from reaching the second power module. When the predetermined number of gate pulses are blocked, the systems and methods reset to allow complete gate pulses to reach the second module, and continues to detect when the next transition takes place. | 01-03-2013 |
20130076423 | Integrated Circuit With Delay Circuitry - The delay circuit, such as a clock circuit, of an integrated circuit operates with tolerance of variation in temperature. For example, the delay circuit has a temperature dependent current generator that has an adjustable temperature coefficient, such that a range of temperature coefficients is selectable at a particular current output. Also, the clock circuit of an integrated circuit operates with multiple versions of a current that controls a discharging rate and/or a charging rate between reference signals of timing circuitry. | 03-28-2013 |
20130099842 | TEMPERATURE SENSITIVE DEVICE - A temperature sensitive device includes a first delay unit generating a first delayed signal, a second delay unit generating a second delayed signal, a difference generating unit generating an indication signal according to the first delayed signal and the second delayed signal, and a processing unit generating an output signal that is dependent on the temperature sensed by the temperature sensitive device and substantially independent of the manufacturing process of the temperature sensitive device. | 04-25-2013 |
20130169336 | ELECTRONIC DEVICE - When operational clocks are output to a plurality of connecting sections, magnetic waves caused by the rising and falling of each clock have a large effect on the surrounding area. Therefore, provided is an electronic device comprising a plurality of connecting sections that are respectively connected to a plurality of external devices having the same frequencies for operational clocks used to communicate signals; and a clock output section that outputs, respectively to the connecting sections, operational clocks that are phase-shifted relative to each other. The clock output section outputs operational clocks with inverse phases to two of the connecting sections. | 07-04-2013 |
20130321053 | METHOD AND DEVICE FOR SAMPLING AN INPUT SIGNAL - In accordance with various embodiments, a method for sampling an input signal may be provided, wherein the method may include providing a single frequency clock signal; selecting clock pulses from the single frequency clock signal in a random manner to generate a spread spectrum clock signal; and sampling the input signal using the spread spectrum clock signal. A corresponding device for sampling an input signal may be provided. | 12-05-2013 |
20140049306 | SIGNAL TRANSMISSION CIRCUITS - A signal transmission circuit includes a pre-driver and a driver. The pre-driver is configured to generate a first drive signal in response to a first delay signal and a first selection signal and to generate a second drive signal in response to a second delay signal, a second selection signal, and a pulse signal. The driver is configured to drive a transmission signal in response to the first and second drive signals. The first delay signal is enabled at a second time which is later than a first time when an input signal is received, the second delay signal is enabled at a third time which is later than the second time, and the pulse signal is enabled at a fourth time which is delayed by a predetermined delay period from the first time. | 02-20-2014 |
20140084981 | CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE - Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps. | 03-27-2014 |
20140111264 | PRINTED CIRCUIT BOARD AND METHOD FOR CONTROLLING SIGNAL TIMING SEQUENCE THEREOF - A printed circuit board includes multiple receiving components for respectively receiving control signals and a transmitting component coupled to the receiving component through multiple leads. Given that the lengths of the leads may be different to each other, the control unit generates the control signals to the leads according to the information about the leads, and firstly delivers at least one of the control signals to the corresponding receiving component(s), and then delivers the remaining control signals to the receiving components after a predetermined time. Furthermore, a method for controlling a signal sequence for the printed circuit board includes generating multiple control signals depending on the information about leads and delivering at least one of the control signals to the corresponding receiving component and delivering the remaining control signals to the remaining receiving components after the predetermined time. | 04-24-2014 |
20140139280 | SYSTEMS, APPARATUS, AND METHODS FOR PROVIDING CONTINUOUS-TIME SIGNAL DIFFERENTIATION AND INTEGRATION - The disclosed subject matter includes an apparatus. The apparatus is configured to provide an approximate differentiation of an input continuous-time signal. The apparatus includes a continuous-time delay block configured to receive the input continuous-time signal and to delay the input continuous-time signal by a predetermined delay factor to generate a delayed input continuous-time signal; a processing block configured to determine a difference between the input continuous-time signal and the delayed input continuous-time signal; and a multiplication block configured to multiply the difference by a multiplication factor to provide the approximate differentiation of the input continuous-time signal. | 05-22-2014 |
20140253198 | APPARATUSES, METHODS, AND CIRCUITS INCLUDING A DELAY CIRCUIT - Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths. | 09-11-2014 |
20140253199 | SYSTEMS, APPARATUS, AND METHODS FOR PROVIDING CONTINUOUS-TIME SIGNAL DIFFERENTIATION AND INTEGRATION - Systems and methods for providing an approximate differentiation and integration of an input continuous-time signal are provided. The disclosed systems include a continuous-time delay block configured to receive an input continuous-time signal and to delay the input continuous-time signal by a predetermined delay factor to generate a delayed input continuous-time signal, a processing block configured to determine a difference or a sum between two continuous-time signals, and a multiplication block configured to multiply an input continuous signal to provide a multiplied input continuous signal. | 09-11-2014 |
20140266372 | APPARATUS, METHOD AND SYSTEM FOR IMPLEMENTING A HARDWARE INTERFACE PINOUT - Techniques and mechanisms for operating an integrated circuit to communicate via a hardware interface for the integrated circuit, wherein a pinout with the hardware interface is based on the configuration. In an embodiment, the integrated circuit receives a first plurality of signals via the hardware interface, and sequentially latches a second plurality of signals based on the first plurality of signals. In another embodiment, some or all of the second plurality of signals are variously latched by the integrated circuit in an order which is based on the first configuration. | 09-18-2014 |
20150355672 | CLOCK SKEW ADJUSTING STRUCTURE - An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path. | 12-10-2015 |
20160013780 | CMOS Pulse Shrinking, Stretching or Shrink-and-Stretch Mixing Method and Device Thereof | 01-14-2016 |
20160072502 | INPUT/OUTPUT CIRCUIT - A circuit includes a first power node, a second power node, an output node, a plurality of first transistors and a plurality of second transistors. The plurality of first transistors is serially coupled between the first power node and the output node. The plurality of second transistors is serially coupled between the second power node and the output node. | 03-10-2016 |
20160191032 | CLOCK GENERATING DEVICE - A clock generating device includes a first timing delay module, a multiplexer, and a second timing delay module. The multiplexer is electrically connected to the first timing delay module. The second timing delay module is electrically connected to the multiplexer. The first timing delay module generates a plurality of delayed clock signals based on a reference clock signal. The multiplexer outputs a first delayed clock signal and a second delayed clock signal, among the plurality of delayed clock signals, based on a clock generating signal. The second timing delay module generates an output clock signal based on the clock generating signal, the first delayed clock signal and the second delayed clock signal. | 06-30-2016 |
20180026615 | COMPARATOR, CIRCUIT DEVICE, PHYSICAL QUANTITY SENSOR, ELECTRONIC DEVICE, AND VEHICLE | 01-25-2018 |