| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327285000 | Having specific active circuit element or structure (e.g., complementary transistors, etc.) | 42 |
| 20090002046 | Skew signal generation circuit and semiconductor memory device having the same - In a skew signal generation circuit, a pad is connected to an external resistor and a code generator compares a voltage of the pad with a reference voltage to generate a plurality of codes. A skew signal extractor extracts a skew signal from the codes, the skew signal containing information about a current characteristic of a MOS transistor. A driver calibrates a drivability in response to the skew signal. | 01-01-2009 |
| 20090058488 | Delay circuit, semiconductor control circuit, display device, and electronic device - Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor. | 03-05-2009 |
| 20090079487 | Time Delay Line with Low Sensitivity to Process Variations - A time delay line comprises a plurality of delay elements connected in series. Each delay element comprises one or more transistors that exhibit a reverse short channel effect at channel lengths within a certain range. The transistors are configured to have a channel length in the certain range in order to reduce time delay sensitivity to process variations. | 03-26-2009 |
| 20090212838 | Delay Circuit Having Long Delay Time and Semiconductor Device Comprising the Same - A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased. | 08-27-2009 |
| 20090219073 | HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER - A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps. | 09-03-2009 |
| 20100295593 | DELAY CIRCUIT - A delay circuit ( | 11-25-2010 |
| 20110115539 | SIGNAL PROCESSING ARRANGEMENT - A signal processing arrangement comprises a series of latches (XDL, L | 05-19-2011 |
| 20110260767 | SYSTEM AND DEVICE FOR REDUCING INSTANTANEOUS VOLTAGE DROOP DURING A SCAN SHIFT OPERATION - A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation is disclosed. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation. | 10-27-2011 |
| 20120068754 | METHOD AND APPARATUS FOR TIMING CLOSURE - Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation. | 03-22-2012 |
| 20130293275 | PROGRAMMABLE DELAY UNIT - A tunable delay unit and methods of tuning are provided, comprising a plurality of first delay elements and a plurality of first delay element taps between the first delay elements, wherein the first delay element taps are inputs to a first multiplexer and wherein the output of the first multiplexer is selected from among the inputs according to a first tap select input, further comprising a plurality of second delay elements connected in series to the output of the first multiplexer and a plurality of second delay element taps between the second delay elements, wherein the second delay element taps are inputs to a second multiplexer and wherein the output of the second multiplexer is selected from among the inputs according to a second tap select input, the output of the second multiplexer forming the output of the programmable delay unit. The programmable delay unit provides for highly accurate calibration of timed circuits, in particular delay lines. | 11-07-2013 |
| 20140247078 | APPARATUS FOR PROGRAMMABLE INSERTION DELAY TO DELAY CHAIN-BASED TIME TO DIGITAL CIRCUITS - An apparatus for delaying a plurality of chain-based time-to-digital circuits (TDCs). The apparatus includes a plurality of propagation path devices each connected to a respective one of the plurality of TDCs, each propagation path device delays a common start signal by a selectable amount based on a delay selection signal received by the propagation path device, and transmits the delayed start signal to the respective one of the TDCs. | 09-04-2014 |
| 327286000 | With counter | 5 |
| 20090251187 | OUTPUT ENABLE SIGNAL GENERATING CIRCUIT AND METHOD - An output enable signal generating circuit including a first count value generation unit that provides a first count value by executing a counting operation, starting from an initial count value corresponding to a CAS latency information, the counting operation being executed in response to an internal clock signal, a second count value generation unit that provides a second count value that is counted in response to an external clock signal and an output enable signal generation unit for generating an output enable signal that is activated at every timing when the second count value and the first count value become equal to each other, in response to each of a plurality of read commands. | 10-08-2009 |
| 20110050313 | METHODS AND SYSTEMS RELATED TO A CONFIGURABLE DELAY COUNTER USED WITH VARIABLE FREQUENCY CLOCKS - In certain arrangements and methods, a reset-able counter ( | 03-03-2011 |
| 20110221499 | COUNTER CIRCUIT AND PROTECTION CIRCUIT - A counter circuit is provided that can switch delay times by use of a simple circuit configuration. A counter circuit includes plural stages of flip flops connected in cascade, in which a flip flop in a first stage receives a clock from an oscillator as an input signal, and a flip flop in a given stage after the first stage receives a Q output of a preceding stage as an input signal, wherein all or part of the plural stages of flip flops receive a mode signal, and wherein each of the plural stages of flip flops divides by 2 a frequency of the received input signal for output as a Q output when the mode signal indicates a normal delay mode, and each stage of the flip flops that receives the mode signal allows through passage of the received input signal for output as a Q output when the mode signal indicates a delay shortened mode. | 09-15-2011 |
| 20110260768 | PROGRAMMABLE DELAY TIMER AND METHOD THEREFOR - A timer circuit, comprises a delay indication circuit, a frequency indication circuit, and a plurality of counters. The delay indication circuit is for providing a delay time indication. The frequency indication circuit is for providing a frequency indication of a frequency of a clock signal. Each counter of the plurality of counters includes a load input to receive an initial value, and an indication output to provide a count complete indication of the counter. During operation a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired. At least a portion of the frequency indication is provided to the load input of one counter of the set and at least a portion of the delay time indication is provided to the load input of another counter of the set. | 10-27-2011 |
| 20130021079 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SIGNAL TRANSMISSION METHOD THEREOF - A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip. | 01-24-2013 |
| 327287000 | Differential amplifier | 2 |
| 20080238516 | Timing interpolator with improved linearity - A programmable timing interpolator circuit includes low output impedance buffer circuitry driving a node having a capacitance that varies in response to a programmed delay to be introduced by the interpolator. The low output impedance buffer circuitry receives a subset of course delay signals and, after buffering, provides the buffered course delay signals to fine delay circuitry. The buffer may include two source follower stages coupled to each other. The first source follower stage shifts the level of the received signal down. The second source follower stage shifts the level of the signal from the first source follower stage up. The first and second source follower stages are implemented using NMOS and PMOS technology. | 10-02-2008 |
| 20140091847 | DIFFERENTIAL DELAY LINE, RING OSCILLATOR AND MOBILE COMMUNICATION DEVICE - A differential delay line includes a series connection of a plurality of differential delay stages. Each differential delay stage includes a first delay element and a second delay element. The first delay element has a first input, a second input and an output. The second delay element has a first input, a second input and an output. The output of the first delay element of an n-th differential delay stage of the plurality of differential delay stages is coupled to an input of the second delay element of an (n+m)-th differential delay stage of the plurality of differential delay stages, wherein m is an even natural number larger than or equal to two. | 04-03-2014 |
| 327288000 | Field-effect transistor | 24 |
| 20080204103 | Clock skew controller and integrated circuit including the same - A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal | 08-28-2008 |
| 20090146718 | DELAY CIRCUIT - A delay circuit is disclosed for providing highly stable delay time in digital signal processing. The delay circuit includes a preliminary charging/discharging circuit, a signal processing circuit and an output circuit. The preliminary charging/discharging circuit performs charging and discharging operations based on a logic input signal for generating a voltage signal. The signal processing circuit performs signal processing on the voltage signal for generating a first delay signal and a second delay signal. The output circuit performs logic signal processing on the first and second delay signals for generating a logic output signal lagging behind the logic input signal by a delay time. The delay time is independent of any supply voltage. That is, even though the supply voltage is unstable, the delay circuit is capable of generating a stable logic output signal by performing a signal delay process on a logic input signal regardless of the unstable supply voltage. | 06-11-2009 |
| 20100109735 | Control signal generation circuit and sense amplifier circuit using the same - A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals. | 05-06-2010 |
| 20100127748 | TIME-DELAY BUFFER - A time-delay buffer having a CMOS transistor and a capacitor is disclosed. The CMOS transistor of the time-delay buffer has a silicide layer partially disposed on the transistor gate of the CMOS and a non-silicide region lain in between the silicide layers. Therefore, the time-delay buffer of the present invention has a resistance therein, and results in a period of time delayed in the circuit. | 05-27-2010 |
| 20100134170 | Delay Cell of Ring Oscillator and Associated Method - A delay cell for use in a ring oscillator and associated method is provided. The delay cell includes a differential amplifier, a switched capacitance bank, and a Kvco equalizer. The differential amplifier comprises a differential pair, a first load and a second load. The differential pair includes a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The first load is coupled to the positive output terminal, and the second load is coupled to the negative output terminal. The switched capacitance bank has a plurality of controlled capacitor paths selectively connecting to the positive output terminal or the negative output terminal according to a capacitance controlling signal. The Kvco equalizer has an adjustable current source for providing a current to the Kvco equalizer according to a current controlling signal to compensate currents flowing through the first load and the second load. | 06-03-2010 |
| 20100259310 | DATA TRANSFER CIRCUIT AND METHOD WITH COMPENSATED CLOCK JITTER - A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal. | 10-14-2010 |
| 20100327935 | DELAY CIRCUIT OF SEMICONDUCTOR DEVICE - A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage. | 12-30-2010 |
| 20120038405 | DELAY LINES, AMPLIFIER SYSTEMS, TRANSCONDUCTANCE COMPENSATING SYSTEMS AND METHODS OF COMPENSATING - Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages. | 02-16-2012 |
| 20120038406 | DELAY CIRCUIT - To cancel a delay time that occurs in a delay circuit due to temperature and voltage changes. The delay circuit includes a plurality of first and second inverters that are each composed of an N-channel first transistor and a P-channel second transistor connected in series, and P-channel third transistors that are connected between a first power supply wiring and the input nodes of the second inverters. According to the present invention, the presence of the third transistors cancels characteristic variations of the second transistors included in the respective plurality of inverters even if there are changes in temperature, voltage, etc. Consequently, when temperature, voltage, or the like changes, variations in the amount of delay of the entire delay circuit can be regarded as resulting from characteristic variations of the first transistors. | 02-16-2012 |
| 20120062301 | Control voltage generating circuit, constant current source circuit, and delay circuit and logic circuit including the same - A control voltage generating circuit according to an aspect of the present invention includes: a reference voltage unit that includes a plurality of first transistors of the same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistor as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage. | 03-15-2012 |
| 20120075000 | DRIVER AND HIGH VOLTAGE DRIVE CIRCUIT INCLUDING THE SAME - A high voltage drive circuit includes an edge detector for generating an edge detection signal by detecting edges of a first high side input signal and a first low side input signal, the edge detector providing a high side delay signal and a low side delay signal by delaying the first high side input signal and the first low side input signal, a dead time generator for generating a dead time signal indicating a preset dead time in response to the edge detection signal, and a driver comprising a drive signal generator for providing a high side output signal and a low side output signal by inserting the preset dead time based on the dead time signal into the high side delay signal and the low side delay signal. | 03-29-2012 |
| 20120268185 | COMPARATOR WITH ADAPTIVE TIMING - An adaptive delay device that provides a delay to a signal based on circuit conditions such as temperature, supply voltage values and/or fabrication processes. The adaptive delay device may respond to circuit conditions by charging a capacitive device to a threshold voltage. A comparator may incorporate the adaptive delay device to provide adaptive timing for the comparator functions thereby attaining improved noise performance and/or reduce power consumption. | 10-25-2012 |
| 20130002332 | BUS SWITCH CIRCUIT - A bus switch circuit according to an embodiment includes a signal transmission circuit connected between a first terminal and a second terminal. The bus switch circuit includes a first switch element controlled by a first control signal. The bus switch circuit includes a second switch element controlled by a second control signal. The bus switch circuit includes a delay signal generating circuit that outputs a delay signal based on a first signal varying with a first voltage applied to the first terminal and a second signal varying with a second voltage applied to the second terminal. The bus switch circuit includes a control signal generating circuit that outputs the first control signal and the second control signal based on the first signal, the second signal, and the delay signal. | 01-03-2013 |
| 20130015899 | DELAY LINES, AMPLIFIER SYSTEMS, TRANSCONDUCTANCE COMPENSATING SYSTEMS AND METHODS OF COMPENSATING - Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages. | 01-17-2013 |
| 20130027105 | NON-OVERLAP CIRCUIT - A non-overlap circuit includes a first delay circuit configured to receive a first input signal and output a first control signal to a driver circuit, sensing circuitry configured to sense a current generated in response to the first control signal coupled through bulk semiconductor of a semiconductor substrate and produce a feedback signal response, and a second delay circuit. The second delay circuit configured to receive the feedback signal from the sensing circuitry and a second input signal and output a second control signal to the driver circuit based on the sensed feedback signal and the second input signal. | 01-31-2013 |
| 20130033297 | SEMICONDUCTOR CIRCUIT - The present invention relates to a semiconductor circuit including: a delay unit for delaying an input signal by a predetermined time to output the delayed signal; a voltage adjusting unit for charging and discharging voltage according to a level of the input signal; and a combination unit for controlling the charging and discharging operations of the voltage adjusting unit according to signals generated using the level of the input signal and a level of the signal output from the delay unit, and it is possible to effectively remove low level noise and high level noise which are respectively mixed in a high level signal and a low level signal input to the semiconductor circuit. | 02-07-2013 |
| 20130038369 | Delay Cell and Digitally Controlled Oscillator - A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided. | 02-14-2013 |
| 20130043924 | Systems, Methods, and Apparatus for High-Speed Signal Buffer Circuitry - Certain embodiments of the invention may include systems, methods, and apparatus for providing an integrated high-speed signal buffer circuit. According to an example embodiment of the invention, a method is provided for driving a clock signal. The method includes configuring a clock driver circuit with a differential clock buffer output connected to one or more clock lines; matching an operational output resistance of the differential clock buffer output approximately with an input impedance associated with the one or more clock lines; receiving a clock reference signal; applying the clock reference signal to inputs associated with the differential clock driver circuit; and driving the one or more clock lines with the differential clock buffer output. | 02-21-2013 |
| 20130257502 | DELAY CIRCUIT AND ASSOCIATED METHOD - The embodiments of the present invention disclose a delay circuit. The delay circuit comprises an inverter, a load capacitor, and a first voltage clamping module, wherein the first voltage clamping module generates a voltage drop configured to prolong the propagation delay time of the delay circuit as the power supply voltage decreases. The power supply dependent delay circuit may have a much larger propagation delay time at low power supply voltage than it at high power supply voltage at the rising-edge or falling-edge of an input signal. | 10-03-2013 |
| 20140077858 | DIGITALLY CONTROLLED DELAY - A digitally controlled delay device includes at least one delay generating gate device, whose propagation delay is controlled by limiting operating current by means of a tail transistor that is controlled by its gate voltage, a gate control voltage control means for controlling the current limiting transistor gate voltage, and a bank of digitally controlled MOSFET transistors in parallel configuration, and the digital control is adapted to switch the transistors to off and to diode mode connection, current feeding means to feed current through the bank of MOSFET transistors, and the voltage over the bank of parallel transistors is used for gate source control voltage of the tail transistors. | 03-20-2014 |
| 20140167830 | DELAY TIME ADJUSTING CIRCUIT, METHOD, AND INTEGRATED CIRCUIT - A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs | 06-19-2014 |
| 20150349765 | DELAY LINE CIRCUITS AND SEMICONDUCTOR INTEGRATED CIRCUITS - A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors. | 12-03-2015 |
| 20150349766 | DELAY LINE CIRCUITS AND SEMICONDUCTOR INTEGRATED CIRCUITS - A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors. | 12-03-2015 |
| 20190147922 | CHARGE PUMP CIRCUIT WITH LOW REVERSE CURRENT AND LOW PEAK CURRENT | 05-16-2019 |
