| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327290000 | Having specific passive circuit element or structure (e.g., RLC circuit, etc.) | 8 |
| 20100007398 | Linear monotonic delay chain circuit - A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit. | 01-14-2010 |
| 20100019820 | DIGITAL CONTROL SYSTEM AND METHOD - A low power monolithic CMOS device incorporating functions to control power supply transition noise such as in audio circuits and systems. The digital control circuit incorporates MOSFETs that are maintained in an OFF state during normal operation and are turned ON only when system power is turned on or off to thus eliminate the need for bias voltages and maintain minimal quiescent current. | 01-28-2010 |
| 20100039155 | TIME DELAY CIRCUIT FOR USE IN A RESET CIRCUIT - A time delay circuit for providing a time delay to a reset circuit includes a first circuit, a second circuit, an AND gate and a control signal input. The first circuit includes a first resistor and a first capacitor. The second circuit includes a second resistor and a second capacitor. The AND gate includes a first input, a second input and an output. The first capacitor includes an input coupled to a power source via the first resistor, and an output grounded. The second capacitor includes an input coupled to the control signal input and an output grounded. The first input of the AND gate is coupled to the input of the first capacitor, the second input coupled to the input of the second capacitor, and the output configured for coupling to a integrated circuit to reset. | 02-18-2010 |
| 20100090741 | DELAY CIRCUIT - A delay circuit with a delay time being more accurate and a circuit area being reduced is provided. The delay circuit includes a resistance element | 04-15-2010 |
| 20100188128 | Method and Apparatus for Shaping Electronic Pulses - An initial pulse signal is split into a first pulse signal and a second pulse signal. The first pulse signal is delayed through a first impedance to generate a first delayed pulse signal. The first impedance attenuates the first delayed pulse signal to generate an attenuated pulse signal. The second pulse signal is delayed through a second impedance to generate a second delayed pulse signal. The first delayed pulse signal and the attenuated pulse signal are combined to generate the two-pulse response signal. | 07-29-2010 |
| 20120133409 | DELAY CIRCUIT AND SCHEDULE CONTROLLER EMPLOYING THE SAME - A delay circuit used in a schedule controller includes a voltage detection unit, a timer, and a first electronic switch. The voltage detection unit receives an input voltage and compares the input voltage with a predetermined voltage. The timer is controlled by the voltage detection unit to calculate duration of an interval time. The first electronic switch is switched on or off under the control of the timer. When the input voltage substantially equals or exceeds the predetermined voltage, the timer calculates duration of the interval time, the timer generates and transmits a switch signal to the first electronic switch when the timing is reached, and the first electronic switch is switched on by the switch signal and provides an output voltage. | 05-31-2012 |
| 20120212274 | DEVICE FOR CAPTURING AND TRANSFERRING A MEASURED VALUE, SERIES CONNECTION, SYSTEM FOR CAPTURING AND TRANSFERRING MEASURED VALUES, AND HOUSEHOLD APPLIANCE - A device includes a logic circuit having first, second, and third input ports, a first output port, and a feedback path between the first output port and the third input port. In a first operating state, a logic state change at the first input port triggers a logic state change at the first output port, but a logic state change at the third input port does not trigger a logic state change at the first output port. This allows signals to be routed through the device. In a second operating state, a logic state change of the third input port triggers a logic state change of the first output port. This change is fed back, delayed by a time value, to the third input to maintain an oscillation with at least two edges. The frequency of this oscillation is used to determine a value of a measurement variable. | 08-23-2012 |
| 20140266374 | Fractional Order Capacitor - Disclosed is a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side, and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric nanocomposite layer, a complex impedance phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer. | 09-18-2014 |
