| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327262000 | Including significant compensation (e.g., temperature compensated delay, etc.) | 26 |
| 20090045863 | System and method for removal of frequency-dependent timing distortion - A method of preparing a signal for measurement includes receiving the signal and selecting a first edge and a second edge within the signal. The method also includes delivering the first edge to a time interval measurement system after expiration of a first delay period and delivering the second edge to a time interval measurement system after expiration of a second delay period. | 02-19-2009 |
| 20090045864 | VARIABLE DELAY CIRCUIT AND DELAY CORRECTION METHOD - A variable delay circuit is provided which has a plurality of delay elements. The variable delay circuit comprises a delay time correction circuit for individually correcting a delay time on each of the plurality of delay elements to compensate for the variation in transistor performance among the plurality of delay elements. | 02-19-2009 |
| 20090102533 | Temperature Independent Delay Circuits - Delay circuits are provided. Some embodiments of delay circuits herein include a delay line including multiple delay cells connected in series and a variable voltage supplier operative to output a voltage value proportional and/or inversely proportional to a temperature. Delay circuits may include at least one loading capacitor that includes a first end that is connected to an output port of the delay cell and a second end that is connected to an output port of the variable voltage supplier., the at least one loading capacitor including a capacitance that is decreased corresponding to an increase in temperature when a positive voltage is applied across the first end and the second end of the at least one loading capacitor. | 04-23-2009 |
| 20090108902 | Delay Circuit Having Reduced Duty Cycle Distortion - A delay circuit having reduced duty cycle distortion is provided. The delay circuit includes a plurality of delay elements connected together in a series configuration. Each of the delay elements has a prescribed delay associated therewith. The delay circuit further includes a controller connected to respective outputs of the delay elements. The controller is configured such that signal paths between the respective outputs of the delay elements and an output of the controller have delays that are substantially the same relative to one another. Each of the signal paths has a tri-statable switching element associated therewith. | 04-30-2009 |
| 20090115485 | Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus - Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units. | 05-07-2009 |
| 20090153214 | DELAY ELEMENT, VARIABLE DELAY LINE, AND VOLTAGE CONTROLLED OSCILLATOR, AS WELL AS DISPLAY DEVICE AND SYSTEM COMPRISING THE SAME - To provide, with a simple structure, a voltage controlled oscillator, etc., whose center oscillation frequency is stable even if there is a change in the temperature. A delay element includes: a delay generating part which adds a delay amount to an input signal to generate an output signal; and a delay control part which controls the delay. The delay control part has a delay adjusting circuit which outputs a first control signal for adjusting the delay amount, and a temperature compensating circuit which outputs a second control signal for compensating property changes caused by the temperature. The delay control part outputs a third control signal obtained by synthesizing the first control signal and the second control signal to the delay generating part to control the delay amount. The delay control part obtains the third control signal by having the delay adjusting circuit and the temperature compensating circuit connected in series. | 06-18-2009 |
| 20090273384 | VERNIER DELAY CIRCUIT - A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted. | 11-05-2009 |
| 20100007397 | Delay line circuit for generating a fixed delay - A delay line circuit is provided. The delay line circuit includes a reference voltage generating circuit that generates a reference voltage, the reference voltage having a positive temperature coefficient. The delay line circuit also includes a voltage regulating circuit that generates a regulated voltage in response to the generated reference voltage as an input, and a delay chain circuit coupled to the voltage regulator to receive the regulated voltage, the delay chain circuit outputting a delay signal. In an embodiment consistent with the present invention, the reference voltage generating circuit includes a bandgap reference voltage circuit. In another embodiment consistent with the present invention, the reference voltage generating circuit includes a proportional to absolute temperature (PTAT) circuit. | 01-14-2010 |
| 20100013536 | Absolute time delay generating device - An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals. | 01-21-2010 |
| 20100182064 | DATA DELAY CONTROL CIRCUIT AND METHOD - A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal. Consequently, the data delay circuit can automatically generate a data delay signal according to the changes in the operating environment. | 07-22-2010 |
| 20100231280 | DELAY CELL THAT INVERSELY RESPONDS TO TEMPERATURE - A delay cell structure that inversely responds to temperature is provided. A first current mirror includes first and second transistors having sources commonly connected to a power supply terminal. A second current mirror includes third and fourth transistors having drains connected to the channels of the first and second transistors and sources commonly connected to a ground terminal. A resistor is connected between the drains of the first and second transistors. An inverter is provided between the drains of the second and fourth transistors so as to face the resistor and outputting a delay signal that is later than input signal by a delay time proportional to the threshold voltages of the first and third transistors which vary as a function of temperature. | 09-16-2010 |
| 20110128060 | DELAY ADJUSTMENT DEVICE AND DELAY ADJUSTMENT METHOD - Provided is a delay adjustment device for adjusting delay of a strobe signal, which specifies when to read a data signal on a data line, with respect to the data signal in order to perform data transfer with an external memory. A testing unit | 06-02-2011 |
| 20110210779 | CIRCUIT AND METHOD FOR RECOVERING CLOCK DATA IN HIGHLY INTEGRATED SEMICONDUCTOR MEMORY APPARATUS - Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units. | 09-01-2011 |
| 20120139602 | APPARATUS AND METHOD FOR SUPPORTING CIRCUIT DESIGN, AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a circuit design support apparatus, a selection unit selects a delay circuit model from among two or more delay circuit models with wire load based on different values of physical parameters relating to wiring, on the basis of a difference value in a physical parameter between a first path and a second path, the first path being from a branch point of a clock signal line for supplying a clock signal to a register model of a semiconductor integrated circuit model to be designed up to a clock signal input terminal of the register model, the second path being from the branch point up to a data signal input terminal of the register model. An arrangement unit arranges the selected delay circuit model on a data signal line connected to the data signal input terminal. | 06-07-2012 |
| 20120194248 | NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA STROBE - A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects. | 08-02-2012 |
| 20130241618 | SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS - The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree. | 09-19-2013 |
| 20140028364 | CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTIVE VOLTAGE SCALING AND METHOD OF OPERATION THEREOF - A critical path monitor (CPM), a method of setting supply voltage based on output of a CPM and an integrated circuit (IC) incorporating the CPM. In one embodiment, the CPM includes: (1) an edge detector configured to produce a thermometer output over a plurality of clock cycles and (2) a min_max recorder, coupled to the edge detector and configured to record minimum and maximum values of the thermometer output during a polling interval. | 01-30-2014 |
| 20140103985 | Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface - A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL. | 04-17-2014 |
| 20140218092 | PULSED LATCHING APPARATUS AND METHOD FOR GENERATING PULSE SIGNAL OF PULSED LATCH THEREOF - A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal. | 08-07-2014 |
| 20140266373 | INTEGRATED DELAYED CLOCK FOR HIGH SPEED ISOLATED SPI COMMUNICATION - A system may include a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal. A delay circuit may be included to receive the clock signal and provide a delayed clock signal that lags the clock signal by an amount representing a delay across the isolation barrier. The delayed clock signal may be delayed by a round trip propagation delay over the isolation barrier. The delayed clock signal may be used as a reference to read data sent over the isolation barrier. | 09-18-2014 |
| 20140368249 | DELAY CONTROL CIRCUIT - The present invention relates to a delay control circuit and technology in which the amount of delay can be regularly maintained although Process, Voltage, and Temperature (PVT) conditions are changed. The delay control circuit of the present invention includes a ZQ calibration unit configured to generate an impedance code into which a change of PVT conditions has been incorporated, a voltage trimming unit configured to control a level of a trimming voltage at a calibration node, and a delay compensation unit configured to compensate for the amount of delay by controlling an effective capacitance value of a capacitor. | 12-18-2014 |
| 20150035576 | CLOCK SPURS REDUCTION TECHNIQUE - Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver. | 02-05-2015 |
| 20150109042 | APPARATUSES AND METHODS FOR CHANGING SIGNAL PATH DELAY OF A SIGNAL PATH RESPONSIVE TO CHANGES IN POWER - Apparatuses and methods for changing a signal path delay of a signal path responsive to changes in power provided to the signal path are disclosed. An example apparatus includes a signal path and signal path delay compensation circuit. The signal path includes a plurality of signal driver circuits coupled in series. The signal path delay compensation circuit includes an adjustable path delay circuit and a bias circuit. The adjustable path delay circuit is coupled to an output of a signal driver circuit of the plurality of signal driver circuits and includes a latch circuit. The bias circuit is configured to change a resistance to switching a latched signal level of the latch circuit responsive to changes in power provided to the signal path. Additional example apparatuses and methods are also disclosed. | 04-23-2015 |
| 20150145580 | APPARATUS FOR CONTROLLING SEMICONDUCTOR CHIP CHARACTERISTICS - Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit. | 05-28-2015 |
| 20150145581 | IN-SITU DELAY ELEMENT CALIBRATION - A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver. | 05-28-2015 |
| 20150295567 | PULSE DELAY CIRCUIT - A pulse delay circuit includes a pull down element, a first pull up element, a first delay unit, a second delay unit, a second pull up element, and an inverted buffer. The pull down element is connected to an input pulse signal, a node b and a first voltage. The first pull up element is connected to a node c, a second voltage and the node b. The first delay unit has a reset terminal. The first delay unit is connected to the node b and the node c. The second delay unit is connected to the node c and the node d. The second pull up element is connected to the node d, the second voltage and the node c. The inverted buffer is connected to the node c and the reset terminal. Moreover, a delayed pulse signal is outputted from the inverted buffer. | 10-15-2015 |
