| Entries |
| Document | Title | Date |
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| 20080224750 | Digital delay architecture - A digital delay architecture and a digital delay method are provided. The digital delay architecture includes at least one shifter, at least one adder connected to the at least one shifter and a plurality of registers storing at least an output of the at least one adder and an original sampled signal. The plurality of registers are selectable to define a fractional delay value. | 09-18-2008 |
| 20080278210 | SYSTEM FOR GLITCH-FREE DELAY UPDATES OF A STANDARD CELL-BASED PROGRAMMABLE DELAY - A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals. | 11-13-2008 |
| 20080290923 | SYSTEMS AND METHODS FOR PROVIDING DELAYED SIGNALS - A variable delay apparatus comprises a calibrating unit receiving a signal from a variable delay unit and from a plurality of fixed delay sources, the calibrating unit comparing the signal from the variable delay unit with a plurality of signals from the fixed delay sources to control operation of the variable delay unit over a delay range independently of environmentally-induced drift. | 11-27-2008 |
| 20080290924 | METHOD AND APPARATUS FOR PROGRAMMABLE DELAY HAVING FINE DELAY RESOLUTION - An programmable delay apparatus includes a first delay stage having a delay cell which includes a passive network, where the first delay stage is capable of providing a first time delay. The apparatus further includes a second delay stage which includes a plurality of delay cells, where each delay cell is capable of providing a second time delay which is larger than the first time delay. A method for delaying an input signal includes receiving a delay select command based upon the desired time delay, establishing a circuit path which includes at least one delay element, selected from a plurality of delay cells, according to the delay select command, wherein at least one of the plurality of delay cells includes a delay element which comprises a passive network. | 11-27-2008 |
| 20080297221 | DELAY CIRCUIT AND DELAY TIME ADJUSTMENT METHOD - A delay circuit includes an interface for giving a command of setting a delay time and a delay device that can be set to any desired delay time, and the delay time of the delay device is set according to a command from the interface. | 12-04-2008 |
| 20080309391 | DELAY CIRCUIT AND RELATED METHOD THEREOF - Disclosed is a delay circuit, which comprises: a map delay module, for delaying an input data signal to generate an output data signal according to a mapped delay selection signal; and a delay mapping unit, coupled to the map delay module, for generating the mapped delay selection signal according to an input selection signal and at least a mapping value. | 12-18-2008 |
| 20090002045 | INTEGRATED CIRCUIT WITH DELAY SELECTING INPUT SELECTION CIRCUITRY - Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit. | 01-01-2009 |
| 20090039938 | DELAYING STAGE SELECTING CIRCUIT AND METHOD THEREOF - A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first register for sampling the delayed clock signals according to a clock signal to generate sampled values; first memory units, wherein the first memory units are utilized to memorize the sampled values, and each of first memory unit outputs at least one of the sampled values according to a corresponding first selecting signal; a first selecting unit, for outputting the sampled values according to a second selecting signal; a determining module, for determining if the sampled values meet a specific relation, where if the determination result is positive then determining the particular delaying stage; and a counter for generating a counting value to control the delayed clock signal sampled by the first register. | 02-12-2009 |
| 20090051399 | ELECTRONIC CIRCUIT WITH LOW NOISE DELAY CIRCUIT - An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages ( | 02-26-2009 |
| 20090066390 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit which receives a first clock having a period T | 03-12-2009 |
| 20090146716 | Timing control circuit, timing generation system, timing control method and semiconductor memory device - A timing control circuit DLY | 06-11-2009 |
| 20090160520 | VARIABLE DELAY CIRCUIT AND DELAY AMOUNT CONTROL METHOD - A variable delay circuit comprising a first delay element configured to delay an input signal, a second delay element coupled to the first delay element in parallel and also configured to delay the input signal, a control current supply section configured to supply control currents for adjusting a delay amount of the first delay element and a delay amount of the second delay element, and an output signal selecting section configured to select any one of an output signal from the first delay element and an output signal from the second delay element according to a selecting signal for selecting delay time of the input signal. | 06-25-2009 |
| 20090256612 | DELAY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source. | 10-15-2009 |
| 20090284296 | SELECTABLE DELAY PULSE GENERATOR - A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer. | 11-19-2009 |
| 20090295449 | DUTY CYCLE MEASUREMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE - A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance. | 12-03-2009 |
| 20090309643 | INSULATING COMMUNICATION CIRCUIT - According to an embodiment of the present invention, an insulating communication circuit includes a first insulating circuit | 12-17-2009 |
| 20090315605 | VARIABLE DELAY APPARATUS - It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block | 12-24-2009 |
| 20090322397 | DELAY CIRCUIT AND RELATED METHOD THEREOF - A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal. | 12-31-2009 |
| 20100019818 | DEVICE AND METHOD FOR POWER MANAGEMENT - A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error. | 01-28-2010 |
| 20100123503 | Variable delay circuit, variable delay circuit controlling method, and input/output circuit - A variable delay circuit includes: a first delay section that changes a first drive capability or a first capacity load, receives the reference signals, and generates a first delayed signal by giving a first delay to the reference signal; a second delay section that changes a second drive capability or a second capacity load of the second delay section, receives the reference signal, and generates a second delayed signal by giving a second delay to the reference signal; a first capacity load setting section that sets at least one of the first capacity load and the second capacity load; a first phase comparing section that compares a first phase of the first delayed signal with a second phase of the second delayed signal; and a drive capability setting section that controls the first drive capability and the second drive capability. | 05-20-2010 |
| 20100127747 | DIGITALLY CONTROLLED OSCILLATOR WITH THE WIDE OPERATION RANGE - There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block | 05-27-2010 |
| 20100148839 | Self-Tuning Of Signal Path Delay In Circuit Employing Multiple Voltage Domains - Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation. | 06-17-2010 |
| 20100164584 | Timing Generator - A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data. | 07-01-2010 |
| 20100213999 | Dynamic Element Matchinig for Delay Lines - This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching. | 08-26-2010 |
| 20100295591 | INTER-PAIR SKEW ADJUSTMENT - A skew adjustor that can reduce inter-pair skew between differential signals received via a cable is disclosed. In one embodiment, a skew adjustor includes: a skew detector that receives signals from a cable, and provides a detected skew amount when skew is detected between two of the signals; an offset controller for receiving the detected skew amount, and for providing a delay control signal in response thereto; and a skew delay circuit that receives the signals and the delay control signal, and enables one or more delay stages in a path of a first arriving of the two skewed signals based on the delay control signal, such that an adjusted skew between the two skewed signals at an output of the skew delay circuit is less than the detected skew amount by an amount corresponding to the enabled one or more delay stages. | 11-25-2010 |
| 20100295592 | AUTOMATIC HOLD TIME FIXING CIRCUIT UNIT - An automatic hold time fixing circuit unit includes a first switch having first and second ends connected to data input and output ports. An input end of a memory element is connected to the second end of the first switch. A second switch includes a first end connected to an output end of the memory element and a second end connected to the data output port. A control circuit includes first and second output terminals and first and second input terminals. The first and second output terminals are connected to control ends of the first and second switches. The first and second input terminals allow input of two clocks to the control circuit for controlling connection or disconnection of the first and second switches. The data stored in the memory element can be utilized to fix a hold time of the data, so that correct data can be obtained at the data output port. | 11-25-2010 |
| 20110012661 | SEQUENTIALLY OPERATED MODULES - Method, modules and a system formed by connecting the modules for controlling payloads. An activation signal is propagated in the system from one module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to an external power source such as AC power. | 01-20-2011 |
| 20110068844 | DELAY CONTROL CIRCUIT AND METHOD - The present invention relates to a delay control circuit and a method of controlling delay of an output signal generating based on an input signal, wherein a plurality of delayed replicas of a reference signal are generated with dedicated time delays with respect to the reference signal and are sampled at a predetermined timing defined by the input signal. One of the delayed replicas is selected based on the output of the sampling means, and the output signal is generated based on the selected replica. Thereby, a predetermined phase relationship can be generated even in cases where no strict phase relation is given between data and reference signal. | 03-24-2011 |
| 20110080202 | ADAPTIVE VOLTAGE SCALERS (AVSs), SYSTEMS, AND RELATED METHODS - Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database. | 04-07-2011 |
| 20110084750 | MODULATION APPARATUS AND TEST APPARATUS - Provided is a modulation apparatus that outputs an output signal having a designated amplitude and a designated phase, comprising a first variable delay section that outputs a first delayed signal obtained by delaying a periodic signal by a set delay time; a second variable delay section that outputs a second delayed signal obtained by delaying the periodic signal by a set delay time; an adding section that adds together the first delayed signal and the second delayed signal, and outputs the result as the output signal; and a setting section that sets the delay times for the first variable delay section and the second variable delay section according to the designated amplitude and the designated phase. | 04-14-2011 |
| 20110095802 | Semiconductor device and designing method of the same - A semiconductor device includes: a control target circuit section; and a voltage control section configured to dynamically control a supply voltage to the control target circuit section. The control target circuit section includes: a delay monitor circuit configured to measure a delay in the control target circuit section as a monitor delay; and a target delay register configured to store a target delay data which shows a target delay as a target value of the monitor delay. The delay monitor circuit compares the monitor delay and the target delay shown by the target delay data and sends a comparison resultant signal to the voltage control section to show a result of the comparison. The voltage control section controls the supply voltage based on the comparison resultant signal such that the monitor delay approaches to the target delay. | 04-28-2011 |
| 20110133808 | APPARATUS - An apparatus has a delay circuit, a delay control circuit which detects the delay time of the delay circuit and generates a delay adjustment signal based upon the detection result, and a delay adjustment circuit operable to adjust delay time of the delay circuit in response to the delay adjustment signal. | 06-09-2011 |
| 20110169542 | DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DELAYING - A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal. | 07-14-2011 |
| 20110187433 | On-Chip Self Calibrating Delay Monitoring Circuitry - The present disclosure relates to on-chip self calibrating delay monitoring circuitry. | 08-04-2011 |
| 20110193607 | Method and Apparatus for Clock Calibration in a Clocked Digital Device - Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock signal at the input of the DCM circuit and appearance of an active edge of another clock signal at the output of the DCM circuit depends on a phase adjustment signal applied to the DCM circuit's phase adjust input. A phase adjustment circuit provides the phase adjustment signal to the DCM circuit's phase adjust input for controlling the amount of the delay between the clock signal at the input of the DCM circuit and the clock signal at the output of the DCM circuit. | 08-11-2011 |
| 20110241746 | LOW POWER SMALL AREA STATIC PHASE INTERPOLATOR WITH GOOD LINEARITY - A static phase interpolator includes first and second plurality of inverters coupled in parallel between an output node and first and second input nodes for receiving first and second clock signals, and first and second plurality of switch elements coupled to the first and second plurality of inverters for selectively turning on individual ones of the inverters in response to a phase control signal. An inverter is coupled the output node. The interpolator may include a slew rate controller coupled to the first and second input nodes. Also, each inverter of the interpolator may include a PMOS transistor in series with an NMOS transistor and have a respective one of the switch elements disposed between the PMOS and NMOS transistors. | 10-06-2011 |
| 20110254606 | Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider - A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal. | 10-20-2011 |
| 20110291730 | OPEN LOOP TYPE DELAY LOCKED LOOP AND METHOD FOR OPERATING THE SAME - An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value. | 12-01-2011 |
| 20120062300 | CIRCUIT AND METHOD FOR ASYNCHRONOUS PIPELINE PROCESSING WITH VARIABLE REQUEST SIGNAL DELAY - Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design. | 03-15-2012 |
| 20120098583 | PIPELINE CIRCUIT, SEMICONDUCTOR DEVICE, AND PIPELINE CONTROL METHOD - Provided is a pipeline circuit capable of flexibly controlling clock frequencies regardless of whether a pipeline operation by a flow control is stopped or not, without significantly increasing a processing latency even if a clock frequency is decreased, and in response to performance requests for a processing throughput. Among P clocks (P is a positive integer), the phases of which are delayed in the order from a first clock to a P-th clock, for example, among six clocks of P | 04-26-2012 |
| 20120126870 | CIRCUIT AND METHOD FOR RAS-ENABLED AND SELF-REGULATED FREQUENCY AND DELAY SENSOR - Circuits and methods are provided for a reliability, availability and serviceability (RAS) enabled and self-regulated frequency and delay sensor of a semiconductor. A circuit for measuring and compensating for time-dependent performance degradation of an integrated circuit, includes at least one critical functional path of the integrated circuit, and Wearout Isolation Registers (WIR's) connected to boundaries of the critical functional path. The circuit also includes a feedback path connected to the WIR's, and a sensor control module operable to disconnect the critical functional path from preceding and succeeding functional paths of the integrated circuit, connect the critical functional path to the feedback path to form a critical path ring oscillator (CPRO), and enable the CPRO to generate an operating signal. A delay sensor module is operable to measure a frequency of the operating signal to determine and compensate for a degradation of application performance over a lifetime of a semiconductor product. | 05-24-2012 |
| 20120182057 | POWER SUPPLY INDUCED SIGNAL JITTER COMPENSATION - Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response. | 07-19-2012 |
| 20120212273 | SYNCHRONOUS SIGNAL GENERATING CIRCUIT - A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode. | 08-23-2012 |
| 20120223757 | Method and Apparatus for Clock Calibration in a Clocked Digital Device - Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock signal at the input of the DCM circuit and appearance of an active edge of another clock signal at the output of the DCM circuit depends on a phase adjustment signal applied to the DCM circuit's phase adjust input. A phase adjustment circuit provides the phase adjustment signal to the DCM circuit's phase adjust input for controlling the amount of the delay between the clock signal at the input of the DCM circuit and the clock signal at the output of the DCM circuit. | 09-06-2012 |
| 20120262213 | On-Chip Self Calibrating Delay Monitoring Circuitry - The present disclosure relates to on-chip self calibrating delay monitoring circuitry. | 10-18-2012 |
| 20130002331 | SEMICONDUCTOR DEVICE AND DESIGNING METHOD OF THE SAME - A semiconductor device includes a control target circuit section and a voltage control section configured to dynamically control a supply voltage to the control target circuit section. The control target circuit section includes a delay monitor circuit configured to measure a delay in the control target circuit section as a monitor delay and a target delay register configured to store target delay data for a target value of the monitor delay and which is set before the measuring of the delay, based on an external signal. The delay monitor circuit compares the monitor delay and the target delay and sends a comparison resultant signal to the voltage control section to show a result of the comparison. The voltage control section controls the supply voltage based on the comparison resultant signal such that the monitor delay approaches to the target delay. | 01-03-2013 |
| 20130093488 | TEST CIRCUIT AND METHODS FOR SPEED CHARACTERIZATION - A system and method for efficiently performing timing characterization of regions of an integrated circuit. An integrated circuit has monitors distributed in different physical regions across its die. Each monitor includes timing characterization and self-test circuitry. This circuitry includes one or more tunable delay lines used during timing measurements. The circuitry verifies the tunable delay lines are defect free prior to the timing measurements. If defects are detected, but tunable delay lines may still be used, a scaling factor may be generated for a failing tunable delay line. The scaling factor may be used during subsequent timing measurements to maintain a high accuracy for the measurements. The timing measurements may determine a particular physical region of the die provides fast or slow timing values. The resulting statistics of the timing measurements may be used to change an operational mode of the IC in at least the particular region. | 04-18-2013 |
| 20130106482 | SIGNAL DELAY CIRCUIT | 05-02-2013 |
| 20130120047 | POWER-SUPPLY-INSENSITIVE BUFFER AND OSCILLATOR CIRCUIT - One embodiment of the present invention sets forth a technique for reducing jitter caused by changes in a power supply for a clock generated by a ring oscillator of inverter devices. An inverter sub-circuit is coupled in parallel with a current-starved inverter sub-circuit to produce an inverter circuit that is insensitive to changes in the power supply voltage. When the ring oscillator is used as the voltage controlled oscillator of a phase locked loop, the delay of the inverters may be controlled by varying a bias current for each inverter in response to changes in the power supply voltage to reduce any jitter in a clock output produced by the changes in the power supply voltage. When the transistor devices are sized appropriately and the bias current is adjusted, the sensitivity of the inverter circuit to changes in the power supply voltage may be reduced. | 05-16-2013 |
| 20130127508 | SIGNAL DELAY CIRCUIT AND SIGNAL DELAY METHOD - A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled. | 05-23-2013 |
| 20130147536 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first signal delay block configured to delay a first edge of an input signal with varying delay amounts, maintain a second edge of the input signal, and output at least one first driving signal, a second signal delay block configured to delay the second edge of the input signal with the varying delay amounts, maintain the first edge of the input signal, and output at least one second driving signal, and an output pad driving block configured to drive a data output pad with a first voltage in response to the first driving signal and drive the data output pad with a second voltage in response to the second driving signal. | 06-13-2013 |
| 20130147537 | FAILURE DETECTOR CIRCUIT AND ASSOCIATED METHOD - A failure detector circuit for detecting status of a protected circuit, the failure detector circuit having an operating cycle, has an enabling signal generator, a comparator circuit, a delay circuit. The enabling signal generator enables the comparator for an enable time in each operating cycle. The comparator circuit compares an output of the protected circuit with a reference signal. The delay circuit receives an output signal of the comparator to decide whether a failure occurred within a give delay time. | 06-13-2013 |
| 20130169337 | PHASE DIFFERENCE QUANTIZATION CIRCUIT, DELAY VALUE CONTROL CIRCUIT THEREOF, AND DELAY CIRCUIT - A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to N | 07-04-2013 |
| 20130207709 | VARIABLE UNIT DELAY CIRCUIT AND CLOCK GENERATION CIRCUIT FOR SEMICONDUCTOR APPARATUS USING THE SAME - A clock generation circuit includes, inter alia, a first phase detection block comparing initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and outputting an initial phase difference detection signal corresponding to a comparison result; a second phase detection block comparing phases of the reference clock signal and the output clock signal, and outputting a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and delaying the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and outputting the output clock signal; and a delay control block generating the control voltage which has the voltage level corresponding to the phase detection signal. | 08-15-2013 |
| 20130241619 | POWER SUPPLY INDUCED SIGNAL JITTER COMPENSATION - Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response. | 09-19-2013 |
| 20130257501 | VARIABLE DELAY CIRCUIT - Plural unit delay circuits connected in series and an output circuit that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit includes a selector that outputs a signal input to a second input terminal when the set signal is “0”, and outputs a signal input to a first input terminal when the set signal is “1”, and an inverter that inverts and outputs an output of the selector from a second output terminal. A second unit delay circuit includes an inverter that inverts the signal input to the first input terminal and outputs from a first output terminal, and a selector that outputs the signal input to the second input terminal when the set signal is “0”, and outputs an output of the inverter when the set signal is “1” from the second output terminal. | 10-03-2013 |
| 20130335130 | APPARATUS AND METHOD FOR PROVIDING TIMING ADJUSTMENT OF INPUT SIGNAL - An apparatus for providing time adjustment of an input signal includes a coarse timing digital-to-analog converter (DAC), a replica delay element and an interpolator. The coarse timing DAC has multiple delay settings for providing a coarse timing adjustment of the input signal, and outputs a first delayed signal by delaying the input signal by a first delay time corresponding to a selected setting of the multiple delay settings. The replica delay element receives the first delayed signal from the coarse timing DAC and outputs a second delayed signal by delaying the first delayed signal by a predetermined second delay time. The interpolator blends either the input signal and the first delayed signal or the first delayed signal and the second delayed signal for providing a fine timing adjustment of the input signal, and outputs a timing adjusted output signal including the coarse timing adjustment and the fine timing adjustment. | 12-19-2013 |
| 20130342254 | APPARATUSES AND METHODS FOR ADJUSTING A MINIMUM FORWARD PATH DELAY OF A SIGNAL PATH - Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency. | 12-26-2013 |
| 20130342255 | SIGNAL DELAY DEVICE AND CONTROL METHOD - A signal delay device includes a delay unit including delay parts connected to one another in series and generating a delay signal; a selection unit to output the delay signal and including selectors connected to one another in series and outputting the delay signal, each selector receiving an output of one of the delay parts, being supplied with an output of former selector, and outputting the output of the delay part or the output of the former selector, based on a selection signal; a register unit holding delay setting data to set an amount of delay of the signal delay device; and a selection signal generator generating a selection signal indicating one of the selectors selecting an output of one of the delay parts based on the delay setting data and outputting the generated selection signal to the selection unit. | 12-26-2013 |
| 20140015583 | SYSTEM AND METHOD FOR TESTING STACKED DIES - Systems and methods are disclosed for testing a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack, particularly where the defect is located in the inter-die data transfer path. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit. | 01-16-2014 |
| 20140015584 | SYSTEM AND METHOD FOR TESTING STACKED DIES - Systems and methods are disclosed for testing dies in a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit. | 01-16-2014 |
| 20140028365 | RING OSCILLATOR - Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided. | 01-30-2014 |
| 20140028366 | Method and Apparatus of Digital Control Delay Line - A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log | 01-30-2014 |
| 20140103986 | MUX-BASED DIGITAL DELAY INTERPOLATOR - A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal. | 04-17-2014 |
| 20140103987 | PHASE DIFFERENCE QUANTIZATION CIRCUIT, DELAY VALUE CONTROL CIRCUIT THEREOF, AND DELAY CIRCUIT - A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to N | 04-17-2014 |
| 20140184297 | CLOCK GENERATION AND DELAY ARCHITECTURE - This disclosure provides examples of circuits, devices, systems, and methods for generating a reference clock signal and delaying a received clock signal based on the reference clock signal. In one implementation, a circuit includes a control block configured to generate a control signal. The circuit includes an oscillator configured to generate a reference clock signal. The oscillator includes a plurality of delay elements each configured to receive the control signal and to introduce a delay in the reference clock signal based on the control signal. The delay elements of the oscillator are arranged to generate the reference clock signal. The circuit further includes a delay block configured to receive a clock signal and to generate a delayed clock signal. The delay block includes one or more delay elements each configured to receive the control signal and to introduce a delay in the clock signal based on the control signal. | 07-03-2014 |
| 20140218093 | METHOD AND APPARATUS FOR TIMING CLOSURE - Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation. | 08-07-2014 |
| 20140253200 | LINK PATH DELAY ESTIMATOR THAT COMBINES COARSE AND FINE DELAY ESTIMATES - A link-path delay estimator estimates a signal-path delay of a signal path between a master device and a remote device, by combining coarse delay estimates and a fine delay estimate. The coarse delay estimates indicate only an integral portion of the signal-path delay, selected as an integral multiple of a symbol period. The fine delay estimate indicates only a fractional portion of the signal-path delay, selected from a range of values that extends over one symbol period. The link-path delay estimator can combine the coarse and fine delay estimates using a first rule if the two most recent coarse delay estimates are equal, and a second rule if the two most recent coarse delay estimates differ. The coarse delay estimates can arise from both rising edges and falling edges of periodic signals sent along the signal path. | 09-11-2014 |
| 20140312951 | ADAPTIVE VOLTAGE SCALERS (AVSs), SYSTEMS, AND RELATED METHODS - Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database. | 10-23-2014 |
| 20150035577 | PROGRAMMABLE DELAY CIRCUIT - A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller. | 02-05-2015 |
| 20150061743 | Clock Gated Delay Line Based On Setting Value - In an embodiment, a delay circuit includes a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. Each delay element of the delay line receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value. | 03-05-2015 |
| 20150372666 | INTEGRATED CIRCUIT - An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage. | 12-24-2015 |
| 20160043707 | DYNAMIC MARGIN TUNING FOR CONTROLLING CUSTOM CIRCUITS AND MEMORIES - Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed. | 02-11-2016 |
| 20160072491 | AUTOMATIC CALIBRATION CIRCUITS FOR OPERATIONAL CALIBRATION OF CRITICAL-PATH TIME DELAYS IN ADAPTIVE CLOCK DISTRIBUTION SYSTEMS, AND RELATED METHODS AND SYSTEMS - Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit. | 03-10-2016 |
| 20160079971 | DELAY CIRCUIT - Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal. | 03-17-2016 |
