| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327283000 | Having specific passive circuit element or structure (e.g., RLC circuit, etc.) | 7 |
| 20100176861 | ELECTRONIC DEVICE AND DELAY CIRCUIT THEREOF - A delay circuit is used for receiving an input signal from a signal source. The delay circuit includes a delay unit, a switch unit, and a generator. The switch unit is used for receiving a voltage from a power supply and selectively transmitting the voltage to the delay unit according to the input signal. The generator is coupled to the power supply for generating an output signal. The output signal is equivalent to the input signal that is delayed for a predetermined time period. Wherein the delay unit is used for generating an electrical signal according to the voltage and transmitting the electrical signal to the generator. The delay unit includes an adjustable capacitor coupled between ground and an interconnection of the switch unit and the generator. An electronic device including the delay circuit is also provided. | 07-15-2010 |
| 20100308882 | FINE DELAY ADJUSTMENT - A fine delay adjustment device is disclosed. The fine delay adjustment device in accordance with the present invention has at least one delay buffer having an output impedance; a capacitor connected to the delay buffer in series; and a variable resistive unit connected with the capacitor in series. The variable resistive unit has a variable resistance of the same order as the output impedance of the delay buffer. The fine delay adjustment of the present invention is capable of providing sub-ps adjustment steps. In the mean while, an increment due to the fine delay adjustment added to delay time is limited. | 12-09-2010 |
| 20120105123 | Fine-grained Clock Skew Tuning in an Integrated Circuit - An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit. | 05-03-2012 |
| 20120105124 | SEMICONDUCTOR APPARATUS, METHOD FOR DELAYING SIGNAL THEREOF, STACKED SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR GENERATING SIGNAL THEREOF - The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal. | 05-03-2012 |
| 20120306557 | CALIBRATION CIRCUIT AND CALIBRATION METHOD - A calibration circuit and a calibration method are provided. The calibration circuit has a delay circuit, a phase detector, and a controller. The delay circuit delays an input signal to output an output signal, wherein a delay time between the input signal and the output signal is related to an equivalent capacitance and an equivalent resistance of the delay circuit. The phase detector coupled to the delay circuit compares the phases of the input signal and the output signal. The controller coupled to the delay circuit and the phase detector generates a control signal according to the comparison result of the phase detector to adjust the equivalent resistance of the delay circuit. | 12-06-2012 |
| 20140002166 | ACCURATE LOW-POWER DELAY CIRCUIT | 01-02-2014 |
| 20140043081 | SAMPLE-AND-HOLD CIRCUIT FOR GENERATING A VARIABLE SAMPLE DELAY TIME OF A TRANSFORMER AND METHOD THEREOF - A sample-and-hold circuit for generating a variable sample delay time of a transformer includes a discharge detection unit, a sample delay time generation unit, and a comparator. The discharge detection unit generates a first voltage according to a first turning-on signal and a first reference current. Length of the first turning-on signal is varied with a discharge time of a present period of the transformer. The sample delay time generation unit generates a second voltage according to the first turning-on signal and a second reference current. The comparator generates a sample signal to a control circuit of the transformer according to a first voltage corresponding to a previous period of the transformer and a second voltage corresponding to the present period of the transformer. The first reference current is K times the second reference current, and 0| 02-13-2014 | |
