Class / Patent application number | Description | Number of patent applications / Date published |
327277000 | Including delay line or charge transfer device | 22 |
20080224751 | Delay Circuit - A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal. | 09-18-2008 |
20080252353 | VOLTAGE MEASURING APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND VOLTAGE MEASURING SYSTEM HAVING THE SAME - A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units. | 10-16-2008 |
20080272817 | Integrated Circuit on a Semiconductor Chip with a Phase Shift Circuit and a Method for Digital Phase Shifting - The present invention relates to an integrated circuit on a semiconductor chip with at least one phase shift circuit ( | 11-06-2008 |
20100164585 | SEMICONDUCTOR DEVICE WITH INTEGRATED DELAY CHAIN - A semiconductor device wherein a delay chain is integrated; the semiconductor device having a semiconductor layer. The delay chain includes a plurality of delay cells placed in the semiconductor layer and electrically connected to each other so as to form the delay chain. The semiconductor device includes a first and second metal lines respectively connected to a supply voltage and a reference voltage and placed in a longitudinal direction on a surface of the semiconductor layer; each delay cell of the plurality of cells is electrically connected with the first and second metal lines. Any delay cell and its successive or preceding delay cells of the delay chain are placed in a transversal direction with respect to the first or the second metal line. | 07-01-2010 |
20100244921 | PROGRAMMABLE DELAY LINE CIRCUIT WITH GLITCH AVOIDANCE - Embodiments of programmable delay line circuits are disclosed herein. The delay line circuit may comprise a first multiplexer having a first input coupled with an input line; a second multiplexer having a first input, and a second input coupled with an output of the first multiplexer, and an output coupled with a second input of the first multiplexer; a third multiplexer having a first input coupled with the output of the second multiplexer, a second input coupled with the input line, and an output coupled with an output line; a first control gate coupled with the third multiplexer to control the third multiplexer; and a second control gate coupled with the second multiplexer to control the second multiplexer; wherein the first and second control gates selectively control the second and third multiplexer, responsive to a delay value encoded in Gray Code. | 09-30-2010 |
20110080203 | DELAY LINE CALIBRATION - A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals. | 04-07-2011 |
20110187434 | SWITCHABLE CAPACITIVE ELEMENT WITH IMPROVED QUALITY FACTOR, AND METHOD OF PRODUCTION - A switchable capacitive element having an adjustable capacitance and an improved quality factor is specified. To this end, the characteristic variables of the switchable capacitive element are optimized in accordance with the equations cited in the description. | 08-04-2011 |
20120139603 | TUNABLE DELAY CELL APPARATUS - A tunable delay cell (TDC) is disclosed, the TDC is applied to power gating circuit design, and the TDC is connected with control unit. The TDC comprises multiplexer, delay unit, clock signal input line, control signal line, power source terminal and combinational circuit. The signal provided by the control signal line can control the clock signal provided by the clock signal input line whether to be delayed a predetermined time by the delay unit or not. The control unit controls the combinational circuit to be turned off to make the TDC stop working. | 06-07-2012 |
20120268184 | On-Chip Self Calibrating Delay Monitoring Circuitry - The present disclosure relates to on-chip self calibrating delay monitoring circuitry. | 10-25-2012 |
20130181759 | ON-CHIP COARSE DELAY CALIBRATION - Process, voltage and temperature corners of an on-chip device under calibration are obtained by comparing the outputs of different on-chip components such as active on-chip components and passive-on chip components in response to an input. A first on-chip delay line including a number of active devices, which generate an array of outputs D[ ]) at different stages of the delay. A second on-chip delay line generates a single output (CLK). A DFF array samples the array of outputs (D[ ]) with the single output clock CLK. The different delay variations in different process and temperature corners cause different outputs from the DFF array. The different outputs from the DFF array provide information about the process and temperature corner that can be for rapid calibration of the on-chip device under calibration within one cycle of the CLK. | 07-18-2013 |
20130285728 | PULSE GENERATOR - A pulse generator comprising: an input for receiving a trigger; an output node for outputting a signal; a delay line comprising one or more delay units and a plurality of taps; one or more pull-up devices each connected to the output node for increasing the output voltage on the output node; and/or one or more pull-down devices each connected to the output node for decreasing the output voltage on the output node; wherein the taps of the delay line are operably connected to the pull-up and/or pull-down devices such that a trigger passing along the delay line activates one or more of the pull-up and/or one or more of the pull-down devices more than once. Re-use of the pull-up and/or pull-down devices enables longer and more complex pulse shapes, such as high-order Gaussian pulse shapes to be produced while keeping the number of components low, thus reducing chip area, power requirements and parasitic capacitance. | 10-31-2013 |
20130342256 | TEMPERATURE-INDEPENDENT OSCILLATORS AND DELAY ELEMENTS - Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit. | 12-26-2013 |
20140028367 | SELF-CALIBRATION OF OUTPUT BUFFER DRIVING STRENGTH - An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay. | 01-30-2014 |
20140152365 | APPARATUSES AND METHODS FOR DELAYING SIGNALS USING A DELAY LINE WITH HOMOGENOUS ARCHITECTURE AND INTEGRATED MEASURE INITIALIZATION CIRCUITRY - Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element. | 06-05-2014 |
20150097609 | APPARATUSES AND METHODS FOR CONTROLLING DELAY CIRCUITS DURING AN IDLE STATE TO REDUCE DEGRADATION OF AN ELECTRICAL CHARACTERISTIC - Apparatuses and method for controlling delay circuits during an idle state to reduce degradation of an electrical characteristic is disclosed. An example apparatus includes a delay line circuit including a plurality of delay stages, and further includes a delay line control circuit coupled to the delay line circuit. The delay line control circuit is configured to enable delay stages of the plurality of delay stages, and is further configured to control enabled delay stages of the plurality of delay stages to provide a respective output clock signal having a high logic level during an idle state. | 04-09-2015 |
20160006423 | CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS - A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0. | 01-07-2016 |
20160065193 | LINEAR PROGRESSION DELAY REGISTER - An adjustable delay line includes a series of delay elements for adjusting the accumulative delay. Each element has a plurality of registers indicating to various devices within the delay element to be ‘on’ or ‘off’, thereby changing the time delay through the element. A master control indicates to the delay line whether to go faster (increment) or go slower (decrement). When one of these control signals is applied to the delay line, it is applied to half the elements, either the odd or the even numbered elements. Only one element will have its state changed by the increment or decrement control signal, and it will be the element for which the previous delay's corresponding element is already set or un-set depending upon the applicable case. | 03-03-2016 |
20160065194 | DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT - A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller. | 03-03-2016 |
20160149564 | DELAY LINE CIRCUIT - A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal. | 05-26-2016 |
20160182028 | DELAY CIRCUIT | 06-23-2016 |
20160380619 | CLOCK GENERATION CIRCUIT THAT TRACKS CRITICAL PATH ACROSS PROCESS, VOLTAGE AND TEMPERATURE VARIATION - Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal. | 12-29-2016 |
20180026613 | BALANCING DELAY ASSOCIATED WITH DUAL-EDGE TRIGGER CLOCK GATERS | 01-25-2018 |