| Entries |
| Document | Title | Date |
|---|
| 20080211542 | Input buffer with wide input voltage range - The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage. | 09-04-2008 |
| 20080218214 | SEMICONDUCTOR OUTPUT CIRCUIT, EXTERNAL OUTPUT SIGNAL GENERATION METHOD, AND SEMICONDUCTOR DEVICE - A semiconductor output circuit, an external output signal generation method and a semiconductor device that suppress variation in an external output signal caused by a decrease in power supply voltage. An output section changes electric potential of an external output signal EB according to a change in electric potential of an internal input signal A from ground to VDD or from VDD to the ground. A differential section outputs an output signal corresponding to the external output signal EB and a predetermined reference signal VREF. The differential section functions as a voltage follower so that the electric potential of the external output signal EB will correspond to the predetermined reference signal VREF. As a result, variation in output voltage VOL at a low voltage side of the external output signal EB is suppressed. | 09-11-2008 |
| 20080246511 | Differential Drive Circuit and Electronic Apparatus Incorporating the Same - A differential driving circuit used for low voltage differential signals and an electronic device incorporating the same are provided wherein no differential amplifiers are used or the number of differential amplifiers are reduced, thereby reducing the circuit area and the current consumption and further solving the problem of oscillation caused by noise, while a high driving performance is achieved. There are included a switch circuit an output circuit and a reference potential generating circuit. The switch circuit, which comprises MOS transistors, receives differential signals and outputs current signals. The output circuit comprises an NMOS transistor, an end of which is connected to the power supply potential of a higher potential side, the other end of which is connected to a node of the switch circuit and which acts as a source follower, and an PMOS transistor, an end of which is connected to the power supply potential of a lower potential side, the other end of which is connected to the other node of the switch circuit and which acts as a source follower. The reference potential generating circuit supplies reference potentials to the respective gates of the PMOS and NMOS transistors. The reference potential generating circuit includes a potential varying means that varies the differential potentials with an offset potential kept constant. Further, there is included an emphasis circuit for the output circuit. | 10-09-2008 |
| 20080246512 | SLEW-RATE CONTROLLED PAD DRIVER IN DIGITAL CMOS PROCESS USING PARASITIC DEVICE CAP - A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up transistor is provided, having a source connected to one side of a power supply, having a gate, and having a drain connected to the output node. The PMOS transistor also has a parasitic capacitance between its gate and drain, having a value that may vary from one integrated circuit to the next from process variations and in response to varying circuit conditions. A current source generates a current having a level corresponding to the value of the parasitic capacitance, and to provide that current to the gate of the PMOS transistor. A level shifter receives an input signal having a voltage varying in a first range provides as output signal to the gate of the PMOS transistor shifted to a level suitable for the PMOS transistor. An NMOS pull-down transistor is also provided, connected to the other side of the power supply, with a similar and corresponding current source and level shifter as has the PMOS transistor. | 10-09-2008 |
| 20080246513 | GATE DRIVING CIRCUIT - The present invention relates to a gate driving circuit, comprising a driver control circuit, a voltage following bias circuit, a pull up circuit and a MOS transistor. The driver control circuit receives an active signal and generates a pull up signal or a pull down signal. In case of the pull up signal, the MOS transistor is turned to the OFF state by the pull up circuit, and there is no current for the output load device. In case of the pull down signal, the MOS transistor is turned to the ON state by the voltage following bias circuit. The driving voltage for the gate of the MOS transistor has a constant voltage drop according to the external supply voltage. Therefore, the gate driving circuit of the present invention provides a constant current for the output load device. | 10-09-2008 |
| 20080265943 | LINE DRIVING CIRCUIT OF SEMICONDUCTOR DEVICE - Disclosed is a line driving circuit which includes two NMOS transistors in series between a supply voltage and a ground voltage. The output of the line driving circuit is applied to an interior circuit through a transmission line, and a repeater is used when the transmission line is long. | 10-30-2008 |
| 20080278199 | OFF-CHIP DRIVER - A driver includes a plurality of first PMOS transistors, a first resistor, a amplifier, a second PMOS transistor and a second resistor. The amplifier herein receives a reference voltage and outputs a regulating voltage. The above-mentioned reference voltage is produced in accordance with a band-gap reference voltage. Since the band-gap reference voltage is unlikely affected by a process variation, thus, the present invention is capable of providing an output current robust from process characteristic and the output current is more reliable to indicate a data signal. | 11-13-2008 |
| 20090002030 | HIGH SPEED SIGNALING SYSTEM WITH ADAPTIVE TRANSMIT PRE-EMPHASIS - A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level. | 01-01-2009 |
| 20090051390 | GLITCH REDUCED COMPENSATED CIRCUITS AND METHODS FOR USING SUCH - Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal. | 02-26-2009 |
| 20090066368 | DIGITAL CALIBRATION CIRCUITS, DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF OPERATION - A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a binary searcher. The driver provides a signal corresponding to an output impedance to the comparator circuit. The output impedance signal is compared to a target impedance, and the comparator circuit then provides logic signals to the binary searcher representing whether the output impedance is greater than the target impedance. The binary searcher then selects a type of step size and count direction, in response to the logic signals, to count the number of steps for adjusting the calibration transistors of the driver. | 03-12-2009 |
| 20090072860 | OFF-CHIP DRIVER APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis for a period of time. The output drive may include a first transistor and a second transistor coupled to an output of the off-chip driver to provide additional initial drive emphasis strength when both transistors are energized for an initial period of time. The time period may be set by an inverted delay circuit. | 03-19-2009 |
| 20090085607 | EMBEDDED POWER GATING - With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers. | 04-02-2009 |
| 20090096485 | Systems and Methods for Dynamic Logic Keeper Optimization - Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that includes an inverting output buffer, a logic function, a bias transistor, and a current circuit. An input of the logic function is electrically coupled to a logic input, an output of the logic function is electrically coupled to an input of the inverting output buffer, and the logic function exhibits a leakage current. The gate of the bias transistor is electrically coupled to an output of the inverting buffer, and a first leg of the bias transistor is electrically coupled to the input of the inverting buffer. The current circuit supplies a current corresponding to the to a second leg of the bias transistor. In some cases, an improved performance may be achieved for a given leakage, or a reduced leakage may be achieved for a given performance. | 04-16-2009 |
| 20090140771 | Current-controlled CMOS circuits with inductive broadbanding - Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C | 06-04-2009 |
| 20090153192 | BI-DIRECTIONAL BUFFER FOR OPEN-DRAIN OR OPEN-COLLECTOR BUS - Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node. | 06-18-2009 |
| 20090184732 | DIFFERENTIAL DRIVING CIRCUIT CAPABLE OF OPERATING AT LOW SUPPLY VOLTAGE WITHOUT REQUIRING COMMON MODE REFERENCE VOLTAGE - A driving circuit includes a pair of input ports, a pair of differential output ports, a first differential pair, a second differential pair, a load unit, and a current source. The first differential pair is directly connected to a first voltage level, and is coupled to the pair of input ports and the pair of differential output ports. The second differential pair is coupled to the pair of input ports and the pair of differential output ports. The load unit is coupled to the pair of differential output ports. The current source is coupled between the second differential pair and a second voltage level. | 07-23-2009 |
| 20090206879 | Signal transmission circuit and signal transmission system using the same - A signal transmission circuit includes first and second power source wirings, and a plurality of differential circuits connected in series between the first and second power source wirings. A signal transmission system includes a plurality of pairs of signal wirings, an output circuit supplying a differential signal to each of the pairs of signal wirings, and an input circuit receiving the differential signals via the pairs of signal wirings, wherein the output circuit includes first and second power source wirings, and a plurality of differential output circuits connected in series between the first and second power source wirings, and the input circuit includes a plurality of differential input circuits respectively corresponding to the differential output circuits. | 08-20-2009 |
| 20090243655 | CURRENT DRIVER SUITABLE FOR USE IN A SHARED BUS ENVIRONMENT - A transceiver suitable for interfacing a logic device to a shared bus includes a transmit node that receives an input signal from the logic device and an I/O node, that is coupled to the shared bus. The transceiver may be designed for use with a shared-bus, single master, multiple slave architecture, e.g., a Local Interconnect Network (LIN). In a LIN compliant implementation, the transceiver may be suitable for use in at least some types of automobiles and other motorized vehicles. Control logic coupled to the transmit node may assert a current driver enable signal in response to detecting an assertion of the input signal. A current driver of the transceiver is configured to draw a time varying driver current from the shared bus node after detecting an assertion of the current driver enable signal. The driver current may cause a sinusoidal transition of the shared bus voltage. | 10-01-2009 |
| 20090243656 | OUTPUT BUFFER FOR AN ELECTRONIC DEVICE - In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function. | 10-01-2009 |
| 20090256592 | SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL - A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage. | 10-15-2009 |
| 20100079167 | DIFFERENTIAL VOLTAGE MODE DRIVER AND DIGITAL IMPEDANCE CALIBERATION OF SAME - A differential voltage mode driver and digital impedance calibration of same is provided. In one embodiment, the invention relates to a method of calibrating a differential driver circuit having a plurality of parallel driver stages, the differential driver circuit for driving a differential signal over a transmission line having an impedance, the method including determining an indication of an impedance of a plurality of parallel replica stages, wherein the plurality of parallel replica stages are replicas of the plurality of parallel driver stages, determining a number of the plurality of parallel replica stages to approximately match the measured impedance with the transmission line impedance, and activating a number of the plurality of parallel driver stages equal to the number of the plurality of parallel replica stages. In another embodiment, the invention relates to a differential voltage mode driver using at least one H-bridge driver stage. | 04-01-2010 |
| 20100090721 | BUFFER OF SEMICONDUCTOR MEMORY APPARATUS - A buffer of a semiconductor memory apparatus includes a buffering section configured to generate an output signal by buffering an input signal. A mismatch compensation section generates a control voltage in correspondence with sizes of a second transistor of the same type as a first transistor constituting the buffering section, wherein the buffering section controls a transition time of the output signal in response to a level of the control voltage. | 04-15-2010 |
| 20100102852 | CIRCUITS AND METHODS FOR BUFFERING AND COMMUNICATING DATA SIGNALS - Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential. | 04-29-2010 |
| 20100134147 | TOLERANT BUFFER CIRCUIT AND INTERFACE - A tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V. Tolerant buffer circuit | 06-03-2010 |
| 20100201399 | Driver Circuit for a Two-Wire Conductor and Method for Generating Two Output Currents for a Two-Wire Conductor - A driver circuit and method for generating two complementary output currents from a two-state logic input signal at two outputs for connecting a two-wire conductor provide the following actions: generating from the input signal, an output signal at each output, the amperage of one of the output currents being adjustable by a control signal; analyzing each voltage materializing at the outputs; generating an error signal as a function of the output voltages within each of at least two time slots subsequent to a change in state of the input signal; caching the error signals or signals derived therefrom and adjusting, as a function of cached error signals or of the cached signals as a function thereof, the output current in corresponding time slots subsequent to a resulting change in state of the input signal. | 08-12-2010 |
| 20100207661 | BI-DIRECTIONAL BUFFER FOR OPEN-DRAIN OR OPEN-COLLECTOR BUS - Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node. | 08-19-2010 |
| 20100244900 | Power Up Biasing in a System Having Multiple Input Biasing Modes - This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected. An operational state detect circuit receives this signal and is responsive to an operational state of the module. The operational state detect circuit enables one of a pull-up and pull-down transistor corresponding said operational state of the module. The operational state detect circuit may the input buffer a predetermined time following external clock signal detection, which might be a following transition in the external clock signal. The operational state detect circuit enables the pull-up or pull-down transistor a predetermined time following enabling said input buffer. | 09-30-2010 |
| 20100283507 | CURRENT SOURCE APPLICABLE TO A CONTROLLABLE DELAY LINE AND DESIGN METHOD THEREOF - A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do. | 11-11-2010 |
| 20100289527 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit | 11-18-2010 |
| 20100308866 | SEMICONDUCTOR BUFFER CIRCUIT - A semiconductor buffer circuit that operates stably against PVT fluctuation is disclosed. The disclosed semiconductor buffer unit of the present invention includes: a detecting block configured to generate a plurality of code signals by detecting an external voltage, using a plurality of reference voltages; and a buffer unit configured to receive an input signal and the plurality of code signals and, based on the code signals, to generate an output signal, wherein a consumption of a driving current of the buffer unit is controlled based on the code signals. | 12-09-2010 |
| 20110074465 | DATA COMMUNICATION CIRCUIT, TRANSMISSION APPARATUS, RECEPTION APPARATUS, AND TRANSMISSION/RECEPTION SYSTEM - A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied. | 03-31-2011 |
| 20110148465 | MERGED PROGRAMMABLE OUTPUT DRIVER - Embodiments provide input/output devices having programmable logic that is programmable to operate input/output devices in one of two drive modes. In various embodiments, to operate an input/output device in a first drive mode, logic circuitry is programmable to couple a reference voltage to a gate of a transistor element of an output driver. In various embodiments, to operate an input/output device in a second drive mode, the logic circuitry is programmable to couple a bias voltage to the gate of the transistor element of the output driver. In various embodiments, the logic circuitry may also be programmable to couple one of a plurality of data inputs to the output driver to operate an input/output device in either a single-ended mode or a differential mode. | 06-23-2011 |
| 20110175647 | Method of operating inverter - A method of operating inverter may include providing a load transistor and a driving transistor connected to the load transistor wherein at least one of the load transistor and the driving transistor has a double gate structure, and varying a threshold voltage of the at least one of the load transistor and the driving transistor having the double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter. | 07-21-2011 |
| 20110215836 | OUTPUT BUFFER - According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor. | 09-08-2011 |
| 20120133392 | MULTIPLEX GATE DRIVING CIRCUIT - A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel. | 05-31-2012 |
| 20120133393 | SEMICONDUCTOR DEVICE - A semiconductor device includes a core circuit including an integrated circuit; output drivers, each including sub-drivers to output digital data transferred from the core circuit, as output data; and a selector that selects a sub-driver to be driven from among the plurality of sub-drivers. Each of the sub-drivers includes: an output transistor connected between a first power supply and an output wiring line to allow the output data to rise or fall according to the digital data; and a switching transistor and a slew-rate control transistor which are connected in series between a gate of the output transistor and a second power supply. The switching transistor turns on or off the output transistor according to the digital data. A gate potential adjusted to determine a slew rate for rise or fall of the output data is selectively provided by the selector to each slew-rate control transistor. | 05-31-2012 |
| 20120139583 | Driving circuit with zero current shutdown and a driving method thereof - Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current. | 06-07-2012 |
| 20120268166 | Low-Current Logic Plus Driver Circuit - A circuit includes a logic stage, an inverter stage, and a driver stage. The logic stage and the inverter stage are provided with current limiters, which include a D-mode feedback transistor and a component that generates a voltage drop. A feedback loop connects the source and the gate of the D-mode feedback transistor via this component. The driver stage includes E-mode transistors connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit. | 10-25-2012 |
| 20120268167 | Semiconductor Device and Method of Controlling the Same - A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current. | 10-25-2012 |
| 20120313663 | OUTPUT BUFFER WITH ADJUSTABLE FEEDBACK - A system according to one embodiment includes input stage circuitry configured to receive input data; output stage circuitry configured to generate buffered output data based on said received input data, said output stage circuitry comprising a first switch and a second switch, wherein said first switch comprises a first gate configured to control said first switch through an inverted gate signal and said second switch comprises a second gate configured to control said second switch through a non-inverted gate signal; first feedback inverter circuitry configured to enable pull-up of said second gate based on an input to said first gate, said first feedback inverter circuitry is further configured to provide an adjustable transition threshold for generation of said pull-up enable; and second feedback inverter circuitry configured to enable pull-down of said first gate based on an input to said second gate, said second feedback inverter circuitry is further configured to provide an adjustable transition threshold for generation of said pull-down enable. | 12-13-2012 |
| 20130002300 | SERIALIZING TRANSMITTER - In embodiments of a serializing transmitter, the serializing transmitter includes one or more multiplexing drive units that each generate a series of output pulses derived from input data signals and multi-phase clock signals. Each of the multiplexing drive units includes a pulse-controlled push-pull output driver that has first and second inputs, and an output coupled to an output of the multiplexing drive unit. Each of the multiplexing drive units also includes a first M:1 (where M is two or more) pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and generating a first series of intermediate pulses at the output; and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, and generating a second series of intermediate pulses at the output. | 01-03-2013 |
| 20130002301 | SINGLE-ENDED CONFIGURABLE MULTI-MODE DRIVER - Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus. | 01-03-2013 |
| 20130082737 | SEMICONDUCTOR DEVICE HAVING SERIALIZER CONVERTING PARALLEL DATA INTO SERIAL DATA TO OUTPUT SERIAL DATA FROM OUTPUT BUFFER CIRCUIT - Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2 n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off. | 04-04-2013 |
| 20130127496 | DRIVING CIRCUIT WITH ZERO CURRENT SHUTDOWN AND A DRIVING METHOD THEREOF - Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current. | 05-23-2013 |
| 20130169312 | SYSTEM AND METHOD FOR REDUCING INPUT CURRENT SPIKE FOR DRIVE CIRCUITRY - A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display. | 07-04-2013 |
| 20130194003 | DRIVER CIRCUIT - The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal. | 08-01-2013 |
| 20130328591 | VOLTAGE MODE DRIVER WITH CURRENT BOOSTER (VMDCB) - A voltage mode driver circuit able to achieve a larger voltage output swing than its supply voltage. The voltage mode driver circuit is supplemented by a current source or “current booster.” The circuit includes a first inverter, a second inverter, and a current source. The first inverter receives a first input and outputs a signal at a node. The second inverter receives a second input signal and outputs an inverted second input signal at the same node. The current source provides current to the node via a first switch, the first switch receiving an input at a first input where the voltage output swing at the node is larger than a power supply voltage applied to the current source. The voltage mode driver circuit uses a stable power supply voltage using a power amplifier with feedback. | 12-12-2013 |
| 20140002135 | SEMICONDUCTOR DEVICE CAPABLE OF SWITCHING OPERATION MODES AND OPERATION MODE SETTING METHOD THEREFOR | 01-02-2014 |
| 20140028350 | CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY - A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode. | 01-30-2014 |
| 20140055164 | BUFFER SYSTEM HAVING REDUCED THRESHOLD CURRENT - A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal. | 02-27-2014 |
| 20140062531 | SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL - A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage. | 03-06-2014 |
| 20140320169 | CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY - A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode. | 10-30-2014 |
| 20150303918 | LOGIC GATE USING SCHMITT TRIGGER CIRCUIT - Logic gates using Schmitt trigger circuits are provided. An AND gate using the Schmitt trigger circuit includes: a NAND gate configured to receive two input signals, perform a NAND logic operation, and output a first output signal; and a DTMOS inverter configured to invert the first output signal, and output the inverted first output signal as a second output signal, and a threshold voltage of the NAND gate is controlled using the second output signal. A OR gate using the Schmitt trigger circuit includes: a NOR gate configured to receive two input signals, perform a NOR logic operation, and output a first output signal; and a DTMOS inverter configured to invert the first output signal, and output the inverted first output signal as a second output signal, and a threshold voltage of the NOR gate is controlled using the second output signal. | 10-22-2015 |
| 20150326225 | CIRCUIT, SEMICONDUCTOR DEVICE, AND CLOCK TREE - A circuit with a reduced leakage current is provided. A first transistor, a third transistor, and a second transistor are electrically connected in this order in series, a drain of the second transistor and a source of the third transistor are electrically connected to each other and are electrically connected to an output node. The first transistor is a p-channel transistor. The second and third transistors are n-channel transistors each including a semiconductor region including an oxide semiconductor. The third transistor functions as a switch that controls electrical connection between a drain of the first transistor and an output node of the circuit. In the standby mode, the third transistor is in an off state. | 11-12-2015 |
| 20160173098 | FAST FALL AND RISE TIME CURRENT MODE LOGIC BUFFER | 06-16-2016 |
