| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326086000 | Bus driving | 21 |
| 20080218215 | Advanced Repeater Utilizing Signal Distribution Delay - An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state of said output stage subsequent to a delay after a transition of said output signal. The delay is due to transmission line effects of said output signal line. | 09-11-2008 |
| 20080265944 | Output Buffer Circuit and Differential Output Buffer Circuit, and Transmission Method - In an output buffer circuit including Inverter | 10-30-2008 |
| 20090033366 | DATA TRANSMISSION SYSTEM AND CABLE - A data transmission system capable of transmitting data at high speed without being bound by a counterpart's power supply voltage can be realized. The data transmission system comprises multiple electronic equipment having individual power supplies, a cable for connecting between the multiple electronic equipment so as to transmit signals therebetween, digital data transmitting circuits extending between the multiple electronic equipment and the cable and each having an open drain type output section at the transmitting end, and an input section provided with a pull-up type resistor at the receiving end, wherein the resistor and the output section are moved from the electronic equipment to the connector of the cable so that parasitic capacitance for restricting time constant of waveforms of signals when rising is changed from a capacitance to a small capacitance. | 02-05-2009 |
| 20090045845 | Adjusting Output Buffer Timing Based on Drive Strength - This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a scaled-down drive transistor employing varying drive codes compared with a standard. The thus determined drive code is combined with an offset to generate the drive code for the adjustable strength transistor. | 02-19-2009 |
| 20090045846 | ADVANCED REPEATER WITH DUTY CYCLE ADJUSTMENT - An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal. | 02-19-2009 |
| 20090072861 | WIRELINE TRANSMISSION CIRCUIT - A wireline transmission circuit includes a first circuit that produces a first variable current, a second circuit that produces a first static current, a trans-impedance amplifier that outputs a first analog signal at a first output node in response to the first variable current and the first static current received at a first input node, and a first feedback resistor connected to the first input node and the first output node. | 03-19-2009 |
| 20090085608 | Systems, methods and devices for arbitrating die stack position in a multi-bit stack device - Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked dies are arbitrated to select one of the dies as the primary die and the other as secondary. Each die includes an input/output buffer that drives an output signal to a commonly shared output terminal in response to receiving a die identification data bit as the input signal. Each die also includes an arbitration circuit that generates a control signal in response to the identification bit of one die being mismatched to a corresponding identification bit of the other die. The control signal programs a stack enable fuse in accordance with the arbitration to designate one of the dies as the secondary die. | 04-02-2009 |
| 20090102513 | Low Power Output Driver - A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground. | 04-23-2009 |
| 20090140772 | ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES - Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed. | 06-04-2009 |
| 20090273369 | GTL BACKPLANE BUS WITH IMPROVED RELIABILITY - Isolation components such as p-n junction or Schottky diodes are provided at pull-up resistors of each signal line of a Gunning Transceiver Logic (GTL) backplane bus in an electronic system for improved reliability, specifically to prevent momentary termination of the bus to ground when a circuit card incorporating the pull-up resistors is inserted into the system. | 11-05-2009 |
| 20090289662 | BRIDGE DESIGN FOR SD AND MMC DATA BUSES - A circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, and a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that (i) at any given clock cycle at least one of the first buffer and the second buffer is disabled, and (ii) when the first buffer and said the buffer are both disabled, subsequent generation of a ‘0’ bit in the first signal or the second signal causes enablement of the first buffer or the second buffer, respectively. | 11-26-2009 |
| 20090309631 | CIRCUIT WITH ENHANCED MODE AND NORMAL MODE - Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit in the normal mode. | 12-17-2009 |
| 20100066410 | LOW-LOSS IMPEDANCE-MATCHED SOURCE-FOLLOWER FOR REPEATING OR SWITCHING SIGNALS ON A HIGH SPEED LINK - Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-emphasis, by avoiding impedance discontinuities over process, voltage and temperature variations and by driving a broader range of loads, e.g., heavily capacitive loads. A circuit for switching or repeating signals on a single-ended or differential high speed link may comprise a source follower with input and output impedances matched to input and output transmission lines on the high speed link. The source follower is biased by a constant transconductance circuit, an external calibration circuit or other circuit to provide an essentially constant output impedance over process, voltage and temperature variations. | 03-18-2010 |
| 20100102853 | Circuitry and Methods Minimizing Output Switching Noise Through Split-Level Signaling and Bus Division Enabled by a Third Power Supply - Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals. With the transmitter and power supplies so configured, no one of the three power supplies must source or sink current to or from more than half of the transmitters at any given time, which reduces power supply loading and minimizes switching noise. As a result, use of the technique may dispense with the need to provide power supply isolation at the transmitters. | 04-29-2010 |
| 20100164546 | CIRCUIT SYSTEM INCLUDING FIRST CIRCUIT SUB-SYSTEM, SECOND CIRCUIT SUB-SYSTEM AND BIDIRECTIONAL BUS, CIRCUIT SUB-SYSTEM AND METHOD - A circuit system has a first and a second circuit sub-system, and a bidirectional bus, the first circuit sub-system having a first control circuit that receives a control signal for controlling the direction of the bidirectional bus, and controls the first sub-system to be either of a transmitting or a receiving state based on a state of the control signal, a first sending unit that receives the control signal, and outputs as a first control signal, and a second sending unit that receives the control signal, and outputs as a second control signal, the second circuit sub-system having a first receiving unit that receives the first control signal, a second receiving unit that receives the second control signal, and a second control circuit that controls the second sub-system to assume either the transmitting or the receiving state on the basis of the first and the second control signal. | 07-01-2010 |
| 20110199120 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit capable of reducing unnecessary current consumption includes a plurality of bus drive circuits for receiving data input, a common bus coupled to the bus drive circuits, and a bus holder coupled to the common bus. One of the bus drive circuits is selected as the selected bus drive circuit. When a logical value corresponding to the data input to be output is the same as a logical value that has been held by the bus holder and output to the common bus, the selected bus drive circuit stops outputting the logical value corresponding to the data input to the common bus. With this configuration, it is possible to eliminate the unnecessary output of the selected bus drive circuit, and to reduce unnecessary current consumption compared to the conventional semiconductor integrated circuit. | 08-18-2011 |
| 20110204922 | Receiver to Match Delay for Single Ended and Differential Signals - In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two current sources to control a gain of an amplification stage in the receiver. If the receiver circuit is receiving a differential input, one of the current sources may be used. If the receiver circuit is receiving a single-ended input, both of the current sources may be used. A larger gain may thus be provided for the single-ended input as compared to the differential input. | 08-25-2011 |
| 20110234259 | OPPORTUNISTIC BUS ACCESS LATENCY - A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device. | 09-29-2011 |
| 20120187980 | TRANSMITTER CIRCUIT - A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage. | 07-26-2012 |
| 20130093465 | ASYMMETRICAL BUS KEEPER - Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level. | 04-18-2013 |
| 20130285703 | ASYMMETRICAL BUS KEEPER - Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level. | 10-31-2013 |
