| Entries |
| Document | Title | Date |
|---|
| 20080204075 | INTERFACING OF CIRCUITS IN AN INTEGRATED ELECTRONIC CIRCUIT - An interface having internal conductors to transfer data between a sending circuit and a receiving circuit in an integrated electronic circuit, the receiving circuit including an input buffer capable of receiving data and an output terminal for sending to the sending circuit an item of extraction information on each extraction of a data word from the input buffer, and the sending circuit including an enable circuit capable of activating an enable signal according to an item of availability information representative of the memory space available in the input buffer. The item of availability information is updated in the sending circuit on each transmission of a data word or on each receipt of the item of extraction information. | 08-28-2008 |
| 20080204076 | Integrated Circuit and a Method For Designing a Boundary Scan Super-Cell - A method for designing an integrated circuit, the method includes: providing an initial definition of a boundary scan register that includes identical super-cells adapted to be connected to multiple pin types; and determining the configuration of each super-cell by providing at least one pin type indication signal to each super-cell. An integrated circuit that includes a boundary scan super-cell, the boundary scan super-cell includes first circuitry adapted to be connected to at least one type of integrated circuit pin; characterized by further including a second circuitry, connected to first circuitry, wherein the second circuitry is adapted to receive at least one pin type indication signal and in response allows the boundary scan super-cell to be connected to at least one additional type of an integrated circuit pin. | 08-28-2008 |
| 20080218210 | INTEGRATED NANOTUBE AND FIELD EFFECT SWITCHING DEVICES - Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit. | 09-11-2008 |
| 20080218211 | High-speed buffer circuit, system and method - A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation. | 09-11-2008 |
| 20080265939 | INTERFACE CIRCUIT AND ELECTRONIC DEVICE - An interface circuit and an electronic device are used for expanding an output port of a micro processing unit. The interface circuit includes an input port electrically connected to the output port of the micro processing unit for receiving a control signals, and a plurality of output ports selectively driven to control external circuits by inputting different values of the control signal at the input port. | 10-30-2008 |
| 20080278198 | Buffer for Object Information - A buffer that is state-aware and/or node-oriented. In a state-aware buffer, one or more operations relating to a state can be performed. In a node-oriented buffer, instances of a node can be accessed without regard to an object structure in which the instance is included. | 11-13-2008 |
| 20080297198 | Two-wire transmitter - A two-wire transmitter for receiving power supply from an external circuit through two transmission lines and also transmitting a current signal based on the measurement value of a sensor includes a current control section to which a voltage is supplied from an external circuit, for controlling the current value of the current signal based on an electric signal responsive to the measurement value of the sensor, if current consumption of the two-wire transmitter becomes smaller than the current value of the current signal, the current control section for charging and if the current consumption becomes larger than the current value of the current signal, the current control section for discharging; a computation control section for outputting the electric signal to the current control section and also outputting a setting signal based on predetermined computation processing information; a clock supply circuit for controlling the frequency of a clock signal based on the setting signal and supplying the clock signal to the computation control section; and a constant-voltage circuit for setting output voltage of the current control section to a predetermined voltage and supplying the voltage at least to the computation control section and the clock supply circuit. | 12-04-2008 |
| 20080303549 | Data transmitting method and electronic device using the same - A data transmitting method for transmitting a software version data from a power IC to a controlling IC is provided. Firstly, a request signal is transmitted to a second pin of the power IC from a data pin of the controlling IC. Next, an acknowledge signal is transmitted to the data pin from the second pin. Then, a first pin of the power IC is enabled by a clock pin of the controlled IC. Lastly, the software version data is transmitted to the data pin from the second pin of the power IC. | 12-11-2008 |
| 20090051389 | Configurable on-die termination - Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted. | 02-26-2009 |
| 20090072859 | HIGH SPEED IO BUFFER - A bi-directional buffer is provided. The buffer includes a driver, a receiver, and a circuitry configured to select a driving mode in response to detecting a first condition and to select a receiving mode in response to detecting a second condition. The driving mode has a first impedance and the receiving mode has a second impedance. The second impedance is partially contributed from the driver. | 03-19-2009 |
| 20090146692 | Structure for apparatus for reduced loading of signal transmission elements - A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. A signal-handling apparatus may include an isolating circuit coupled to a first conductor, a second conductor to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. A signal-handling circuit can perform a signal-handling function in response to the output of the isolating circuit. The signal-handling circuit and the first circuit may be isolated from the second conductor and the signal-handling circuit such that a communication signal may be conducted with less capacitance and be subject to less return loss. | 06-11-2009 |
| 20090160484 | Input buffer - Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold. | 06-25-2009 |
| 20090167355 | High performance pulsed buffer - An integrated circuit ( | 07-02-2009 |
| 20090201049 | INTEGRATED CIRCUIT WITH INPUT AND/OR OUTPUT BOLTON PADS WITH INTEGRATED LOGIC - An input and/or output pad (P) is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad (P) comprises a pad cell (PC) comprising a pad block (PB) connected to an input buffer (IB | 08-13-2009 |
| 20090302888 | INCREASED SENSITIVITY AND REDUCED OFFSET VARIATION IN HIGH DATA RATE HSSI RECEIVER - Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuits elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade. | 12-10-2009 |
| 20090302889 | INTEGRATED CIRCUIT CONTAINING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK - Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector. | 12-10-2009 |
| 20100066409 | Bidirectional Signal Separation Module for a Bus Converter - A bidirectional signal separation module includes a comparator having a first input node communicatively coupled to a bidirectional single-ended bus, a second input node communicatively coupled to a first voltage source, and an output node communicatively coupled to a unidirectional data transmission node; and a resistive network having a first node communicatively coupled to the second voltage source, a second node communicatively coupled to the bidirectional single-ended bus, a third node communicatively coupled to ground, and a fourth node communicatively coupled to an electronic switch. The electronic switch is configured to alternately couple the fourth node of the resistive network to the second voltage source or ground according to a voltage level on a unidirectional data receiving node. | 03-18-2010 |
| 20100097100 | INTEGRATED CIRCUITS - An integrated circuit comprises a processor, a controller and plural terminals. Each terminal constitutes a connection between the integrated circuit and a peripheral device. Each terminal is connected to a logic circuit on the integrated circuit by a respective IO cell in series connection with a respective IO isolation circuit and wherein the controller is operable on power up of the integrated circuit to activate a reset state and to release the reset state prior to releasing IO isolation by one or more of the IO isolation circuits. Each IO isolation circuit may be arranged so that a default state of the IO isolation circuit is a state in which the IO cell is isolated from the logic circuit. The IO isolation circuits may be controllable by software, for instance a driver for a peripheral device connected to the terminal associated with the IO isolation circuit. Plural IO isolation circuits may be connected so as to be commonly controllable by a single control signal from the controller. | 04-22-2010 |
| 20100109704 | DIFFERENTIAL ON-LINE TERMINATION - Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals. | 05-06-2010 |
| 20100231257 | LOW VOLTAGE ELECTRONIC MODULE INTERFACE - A low voltage electronic module interface, with a low voltage interface for an electronic module receiving a constant current from a body control module, the interface including a reverse current protection circuit | 09-16-2010 |
| 20100244898 | TRANSCEIVER FOR SINGLE ENDED COMMUNICATION WITH LOW EMI - A cable driver ( | 09-30-2010 |
| 20100283506 | CONFIGURABLE INPUT PORT OF AN ELECTRONIC COMPUTER OF A MOTOR VEHICLE - An input port ( | 11-11-2010 |
| 20110062990 | Semiconductor Device and Method of Controlling the Same - A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current. | 03-17-2011 |
| 20110068826 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block. | 03-24-2011 |
| 20110128042 | Universal IO Unit, Associated Apparatus and Method - A universal IO unit applied to a chip or an integrated circuit is provided. The universal IO unit includes a power pad and a plurality of signal pads for providing different functions. According to functional requirements of the universal IO unit, the pad power is selectively connected to an electric wire to couple to a predetermined voltage, and each of the signal pads is also selectively connected to a signal wire to transceive signals. | 06-02-2011 |
| 20110204920 | INTERFACE CIRCUIT, ANALOG FLIP-FLOP, AND DATA PROCESSOR - On an interface between LSIs, boards, devices (units), and others, the data transfer efficiency per signal line is improved. A shift circuit | 08-25-2011 |
| 20110291702 | SIGNAL TRANSMISSION SYSTEM AND SIGNAL TRANSMISSION METHOD - A signal transmission system according to the present invention includes a first data conversion circuit ( | 12-01-2011 |
| 20120038389 | INTERFACE CIRCUIT - An interface circuit electronically connects a processor and a card reader. The interface circuit includes a clock circuit, a reset circuit, and an I/O circuit. The clock circuit may transmit a clock signal transmitted from the processor to the card reader, and includes a first bipolar junction transistor (BJT). The reset circuit may transmit a reset signal transmitted from the processor to the card reader, and includes a second BJT. The I/O circuit may transmit data transmitted from the processor to the card reader, and includes a third BJT and a fourth BJT. | 02-16-2012 |
| 20120105105 | Nonvolatile Logic Circuit - Semiconductor industry seeks to replace traditional volatile logic and memory devices with the improved nonvolatile devices. The increased demand for a significantly advanced, efficient, and nonvolatile data retention technique has driven the development of magnetic tunnel junctions (MTJs) employing a giant magneto-resistance (GMR). The present application relates to nonvolatile logic circuits with integrated MTJs and, in particular, concerns a nonvolatile spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct the nonvolatile logic circuits performing NOT, NOR, NAND and other logic functions. | 05-03-2012 |
| 20120176156 | SINGLE-ENDED SIGNALING WITH PARALLEL TRANSMIT AND RETURN CURRENT FLOW - A single-ended signaling system in which transmitted and returned signal currents are enabled to flow substantially parallel to one another and thereby maintain a substantially uniform impedance along the length of a single-ended signal conductor. A reference plane is disposed substantially parallel to a single-ended signaling conductor and coupled to the signaling conductor within a signal-receiving IC and to signaling supply voltage nodes within a signal-transmitting IC. By this arrangement, an signal current flowing to or from the receiving IC via the signaling conductor is conducted to the reference plane, thereby enabling a signal-return current to flow back to or back from the transmitting IC along a single path that is substantially parallel to the signal conductor. | 07-12-2012 |
| 20120299621 | SUPPLY VOLTAGE CONTROL BASED AT LEAST IN PART ON POWER STATE OF INTEGRATED CIRCUIT - Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value. | 11-29-2012 |
| 20130113521 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a main driving unit configured to receive an output data and to drive the received data to a data output pad; a pre-emphasis data generation unit configured to compare a delayed data obtained by delaying the output data by one data period with the output data, to delay the comparison result by one data period, and to output the delayed data as pre-emphasis data; and a pre-emphasis driving unit configured to receive the pre-emphasis data and to drive the received data to the data output pad. | 05-09-2013 |
| 20130113522 | ASYNCHRONOUS-LOGIC CIRCUIT FOR FULL DYNAMIC VOLTAGE CONTROL - Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation. | 05-09-2013 |
| 20130234758 | DELAY-INSENSITIVE ASYNCHRONOUS CIRCUIT - The asynchronous circuit includes a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal. It further includes a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal, and a blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states. | 09-12-2013 |
| 20140002132 | METHOD AND DEVICE FOR LOW POWER CONTROL | 01-02-2014 |
| 20140218069 | MULTI-SUPPLY SEQUENTIAL LOGIC UNIT - Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit. | 08-07-2014 |
