Entries |
Document | Title | Date |
20080197883 | Integrated circuit device and electronic instrument - An integrated circuit device includes a first predriver that drives an N-type power MOS transistor of an external driver including the N-type power MOS transistor and a P-type power MOS transistor, a second predriver that drives the P-type power MOS transistor, a low-potential-side power supply pad, a first output pad, a second output pad, and a high-potential-side power supply pad. The low-potential-side power supply pad, the first output pad, the second output pad, and the high-potential-side power supply pad are disposed along a first direction. The first predriver is disposed in a second direction with respect to the low-potential-side power supply pad and the first output pad, the second direction being a direction that is perpendicular to the first direction, and the second predriver is disposed in the second direction with respect to the second output pad and the high-potential-side power supply pad. | 08-21-2008 |
20080238482 | Transmitter swing control circuit and method - disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver. | 10-02-2008 |
20080265942 | DIFFERENTIAL AMPLIFIER, DIGITAL-TO-ANALOG CONVERTER AND DISPLAY APPARATUS - A differential amplifier includes a first differential pair, a second differential pair, a load circuit, connected in common to the first and second differential pairs, and first and second current sources for supplying the current to the first and second differential pairs, and amplifies a signal responsive to a common output signal of the first and second differential pairs. One of differential inputs of the first differential pair is connected to a reference voltage. A data output period includes a first period and a second period. During the first period, voltages of first and second input terminals are input through first and fourth switches in the on-state to differential inputs of the second differential pair. The other of the differential inputs of the first differential pair is connected through a third switch in the on-state to an output terminal. An output voltage is stored in a capacitor C connected to the other differential input of the first differential pair. The first, third and fourth switches are turned off during the second period. One of the differential inputs of the second differential pair is connected through a second switch to the output terminal. The other differential input of the second differential pair is connected through a fifth switch to a third input terminal. | 10-30-2008 |
20080309372 | Semiconductor memory device - The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which outputs a chip enable signal in response to an output command of the chip enable signal; a standard chip enable pad which receives the output command; a first extension pad which supplies a first extension chip enable signal (/CEm+1) to the chip enable buffer circuit; a second extension pad which supplies a second extension chip enable signal (CEm+1) to the chip enable buffer circuit; a first option pad which receives a first option signal; and a second option pad which receives a second option signal, is constituted. | 12-18-2008 |
20090027083 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS HAVING THE SAME - With an offset circuit including transistors of the same conductivity type, offset of an input signal is performed. Then, the input signal after the offset is supplied to a logic circuit including transistors of the same conductivity type as that of the offset circuit, thereby H and L levels of the input signal can be shifted at the same time. Further, since the offset circuit and the logic circuit are formed using the transistors of the same conductivity type, a display device can be manufactured at a low cost. | 01-29-2009 |
20090033365 | TRANSMITTING APPARATUS - To provide a transmitting apparatus capable of suppressing the fluctuation of a common mode potential and performing high-speed, long-distance signal transmission. The transmitting apparatus has a main buffer circuit and a pre-emphasis buffer circuit | 02-05-2009 |
20090108872 | INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION - An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system. | 04-30-2009 |
20090160486 | High speed electronic data transmission system - A high-speed electrical data transmission system ( | 06-25-2009 |
20090167357 | EXTENDING DRIVE CAPABILITY IN INTEGRATED CIRCUITS UTILIZING PROGRAMMABLE-VOLTAGE OUTPUT CIRCUITS - An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC. | 07-02-2009 |
20090195270 | OUTPUT BUFFER DEVICE - A controlling output buffer slew rate method and an output buffer circuit for a memory device is provided. The output buffer include an output stage formed by a PMOS transistor and a NMOS transistor electrically connected in series, a pre-driver for respectively controlling each gate terminal of the PMOS transistor and the NMOS transistor in order to bring these transistors to the turning-on threshold, a first wire, for transmitting a pull-up signal, coupled between the output stage and the pre-driver, and a second wire, for transmitting a pull-down signal, coupled between the output stage and the pre-driver. After a DATA signal transition (logic state is changed from “H” to “L” or “L” from to “H”), the PMOS or NMOS transistor is turned off first, and then the NMOS or PMOS transistor is turned on due to the time difference between the pull-up signal and the pull-down signal. | 08-06-2009 |
20090219052 | Transmitter swing control circuit and method - Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver. | 09-03-2009 |
20090278568 | METHOD AND SYSTEM TO REDUCE ELECTROMAGNETIC RADIATION FROM SEMICONDUCTOR DEVICES - Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance. | 11-12-2009 |
20090302891 | OUTPUT DRIVER - There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal. | 12-10-2009 |
20090315589 | ADJUSTING METHOD AND CIRCUIT USING THE SAME - A method adjusts driving ability of an output buffer. The output buffer has multiple driving ability classes. The method includes the following steps. First, the driving ability of the output buffer is initialized as an initial class among the driving ability classes. Next, a voltage at an output terminal of the output buffer is initialized to an initial voltage. Then, an input voltage is inputted via the input terminal at a first time instant. Next, an output voltage outputted from the output terminal is sampled to obtain a voltage value at a second time instant. Then, whether the voltage value satisfies a predetermined condition is judged. Next, if the voltage value satisfies the predetermined condition, the driving ability class of the output buffer is recorded and set. | 12-24-2009 |
20100007381 | DRIVE SIGNAL OUTPUT CIRCUIT AND MULTI-CHIP PACKAGE - Input signals from a signal input terminal are input to a logic circuit, and a control signal corresponding to states of the input signals is output. The control signal is supplied to an output circuit, a plurality of transistors are controlled, and a drive signal is output corresponding to states of the transistors. In the logic circuit, the logic is switched according to the polarity of the setting signal which is input to a logic setting terminal, and a control signal corresponding to the input signal is changed. | 01-14-2010 |
20100033210 | Data Output Circuit - A data output circuit includes a plurality of drivers configured to drive data output terminals to a logic level corresponding to levels of input data in response to driving control signals, and a control section configured to activate and output driving control signals that supplied to a first group of the plurality of drivers, and to activate or inactivate and output driving control signals that supplied to a second group of the plurality of drivers, depending upon a level of a supply voltage. | 02-11-2010 |
20100033211 | Link transmitter with reduced power consumption - With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency. | 02-11-2010 |
20100097101 | DISTRIBUTED SUPPLY CURRENT SWITCH CIRCUITS FOR ENABLING INDIVIDUAL POWER DOMAINS - An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided. | 04-22-2010 |
20100109706 | USB 2.0 HS Voltage-Mode Transmitter With Tuned Termination Resistance - A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D− signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45Ω±10%) in the USB transceiver. | 05-06-2010 |
20100141300 | INVERTER DRIVER INTEGRATED CIRCUIT - An inverter driver integrated circuit (IC) includes a control signal generator generating a first control signal and a second control signal by use of a pulse width modulation oscillator signal, a comparator comparing a half-wave rectified signal of a lamp feedback signal fed back from a lamp with a preset reference signal to output a lamp state signal, a first sensor receiving the lamp state signal and the second control signal to output a first sensing signal, and a second sensor receiving the first sensing signal and the first control signal to output a second sensing signal. | 06-10-2010 |
20100156464 | REDUCED CURRENT INPUT BUFFER CIRCUIT - There is provided a reduced current input buffer circuit. More specifically, in one embodiment, there is provided an input buffer circuit comprising an input buffer that is adapted to draw an operating current, means for providing a first portion of the operating current to the input buffer, and means for providing a second portion of the operating current to the input buffer if the input buffer is expecting data. | 06-24-2010 |
20100176844 | VARIABLE OFF-CHIP DRIVE - A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver. | 07-15-2010 |
20100259300 | Circuit for digitally controlling line driver current - In one embodiment, a circuit for providing a tail current for a line driver includes an adjustable current source. The adjustable current source includes a number of current source cells coupled together in a parallel configuration, where the current source cells are configured to provide the tail current for the line driver in response to a digital control signal. The circuit can further include a digital core coupled to the adjustable current source, where the digital core provides the digital control signal. The digital control signal provides a number of bits, where each bit controls one of the current source cells. In one embodiment, a current source cell can comprise a number of current source sub-cells. The current source cells can be configured to provide the tail current for the line driver in response to the digital control signal when the line driver is operating in a class AB mode. | 10-14-2010 |
20100271070 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 10-28-2010 |
20100308865 | SEMICONDUCTOR DEVICE - A semiconductor device includes a buffer unit configured to include first and second buffers, connected to each other in a cross-coupled manner, to receive a reference voltage and to buffer an input signal applied to the first and second buffers based on the reference voltage to drive an output terminal with a current-driving capacity; and a drive power adjustor configured to adjust the current-driving capacity depending on a level of a power supply voltage applied to the buffering unit. | 12-09-2010 |
20100327910 | Interface device and interface system - An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits a differential signal to the differential signal receiver via a differential signal line including a first signal line and a second signal line. The first coupling capacitor is communicatively coupled to the first signal line and to the differential signal transmitter. The second coupling capacitor is communicatively coupled to the first signal line and to the differential signal receiver. The DC signal transmitter transmits a DC signal via the first signal line. The DC signal receiver receives the DC signal via the first signal line. | 12-30-2010 |
20110012642 | SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS - First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. | 01-20-2011 |
20110084730 | TRANSMISSION APPARATUS FOR DIFFERENTIAL COMMUNICATION - A transmission apparatus for differential communication includes a driver bridge circuit and a pair of noise protection circuits. The driver bridge circuit includes four output devices that are independently connected between each of a pair of transmission lines and a power line or a ground line. Each noise protection circuit is provided to a corresponding transmission lines. Each noise protection circuit includes a ground potential detector and an impedance controller. The ground potential detector detects a potential of the corresponding transmission line with respect to the ground line. The impedance controller causes an impedance of the corresponding transmission line with respect to the ground line to become equal to an impedance of the other transmission line with respect to the ground line, when the detected potential becomes outside a predetermined potential range. | 04-14-2011 |
20110089973 | Semiconductor device and information processing system including the same - A semiconductor device includes a plurality of core chips and an interface chip stacked together. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and a bidirectional buffer circuit that drives the through silicon vias. The interface chip also includes a logic-level holding circuit that holds a logic level of the through silicon vias. The bidirectional buffer circuit includes an input buffer and an output buffer. The driving capability of a first inverter of the logic-level holding circuit is smaller than the driving capability of the output buffer of the bidirectional buffer circuit. | 04-21-2011 |
20110095784 | APPARATUS AND METHOD FOR PROVIDING MULTI-MODE CLOCK SIGNALS - Apparatus and methods for providing multi-mode clock signals are disclosed. In some embodiments, a multi-mode driver configured to receive a first clock signal, and to selectively output a different clock signal in response to one or more signals from a controller is provided. The driver can include an H-bridge circuit without substantial increases in the size of the design area. Advantageously, lower jitter and improved impedance matching can be accomplished. | 04-28-2011 |
20110121861 | MULTIVALUED LOGIC CIRCUIT - In a bridge adder circuit, a first and a second complementary pair of current mirrors is connected between the input terminals and a positive and a negative supply voltage bus, respectively, to control a first and a second push-pull output stage. The outputs of the push-pull output stages are connected to the respective inputs through first resistors and to a common output node through second resistors. As a result, a universal circuit element for a multivalued logic element, such as ternary logic or 5-valued logic is provided. | 05-26-2011 |
20110163782 | FLEXIBLE BUS DRIVER - A bus driver has a ground terminal and a first and a second terminal. In a first operation mode the bus driver provides at the first terminal a first output voltage comprising a first data signal; and at the second terminal the bus driver provides a second output voltage comprising a second data signal. In a second operation mode the bus driver provides at the first terminal a first output voltage comprising a third data signal; and at the second terminal the bus driver provides a second output voltage, wherein a curve of the second output voltage is synchronous however inverted in relation to a curve of the first output voltage. An engine comprises a bus driver as set out above. | 07-07-2011 |
20110169527 | SEMICONDUCTOR DEVICE HAVING OUTPUT DRIVER - To provide an output driver that outputs read data to outside and a mode register that sets a swing capability of the output driver. A transition start timing of the read data driven by the output driver is made relatively earlier when a swing capability of the output driver set by the mode register is set to be relatively large, and the transition start timing is relatively delayed when the swing capability of the output driver set by the mode register is set to be relatively small. With this configuration, a timing when the read data exceeds a threshold level can be caused to coincide with a desired timing regardless of the swing capability of the output driver. | 07-14-2011 |
20110187411 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR CONTROLLING OUTPUT DRIVING FORCE - A semiconductor integrated circuit includes a pre driver unit configured to receive a pre drive signal and a driving force control signal and output a main drive signal; a main driver unit configured to receive the main drive signal and output output data to an output terminal; a terminal connecting unit configured to receive a determination signal and connect to or disconnect from the output terminal in response to the determination signal; a terminal sensing unit configured to sense the output terminal and output a terminal state signal; and a driving force determining unit configured to receive a reset signal and the terminal state signal and output the driving force control signal. | 08-04-2011 |
20110227606 | PROGRAMMABLE HIGH-SPEED INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. | 09-22-2011 |
20110285423 | SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS - First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. | 11-24-2011 |
20110304356 | TRANSMITTER AND RECEIVER OF DIFFERENTIAL CURRENT DRIVING MODE, AND INTERFACE SYSTEM OF DIFFERENTIAL CURRENT DRIVING MODE INCLUDING THE SAME - Differential current driving type transmitter and receiver, and an interface system having the transmitter and receiver. The transmitter includes a current source, a current direction selecting block, and a balancing switch block. The current source sources currents to a pair of transmission lines or sinks currents flowing through the pair of transmission lines. The current direction selecting block transfers a current flowing from the current source to one transmission line of the pair of transmission lines and a current flowing through the other transmission line of the pair of transmission lines to the current source. The balancing switch block initializes the pair of transmission lines to a balanced state. | 12-15-2011 |
20120169372 | DIFFERENTIAL LOGIC CIRCUIT, FREQUENCY DIVIDER, AND FREQUENCY SYNTHESIZER - A differential logic circuit including a current source circuit which is connected to a current control terminal and generates a current, the current value is controlled by a signal received from the current control terminal, a differential unit which, based on the current from the current source circuit, inputs a plurality of logic signals, performs a logic operation, and outputs a result of the logic operation from a pair of differential signal output terminals thereof, a load circuit which is connected to the pair of differential signal output terminals, and a load control circuit which monitors a change of the current value and controls a load of the load circuit based on a result of the monitoring. | 07-05-2012 |
20120217999 | Low Voltage Differential Signal Driving Circuit and Digital Signal Transmitter - A low voltage differential signal (LVDS) driving circuit and a digital signal transmitter with the LVDS driving circuit are provided. The LVDS driving circuit includes a positive differential output terminal and a negative differential output terminal and a transition accelerator. A differential output signal is provided by the positive and negative differential output terminals. When the differential output signal transits from low to high, the transition accelerator couples the positive differential output terminal to a high voltage source and couples the negative differential output terminal to a low voltage source. When the differential output signal transits from high to low, the transition accelerator couples the positive differential output terminal to the low voltage source and couples the positive output terminal to the high voltage source. | 08-30-2012 |
20120229165 | CONFIGURATION AND METHOD FOR IMPROVING NOISE IMMUNITY OF A FLOATING GATE DRIVER CIRCUIT - A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node. | 09-13-2012 |
20130021063 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 01-24-2013 |
20130093464 | SIGNAL TRANSFER CIRCUIT - A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal. | 04-18-2013 |
20130113523 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main driving unit configured to serialize first and second data applied in parallel and output the serialized data to a data output pad, and an auxiliary driving unit configured to drive the data output pad in a period when the first and second data have different logic levels. | 05-09-2013 |
20130135010 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A device including first and second semiconductor chips, each of first and second semiconductor chips including first to M-th penetration electrodes, M being an integer equal to or greater than 3, each of the first to M-th penetration electrodes penetrating through a semiconductor substrate, and the first semiconductor chip including a first input circuit coupled to the M-th penetration electrode of the first semiconductor chip at an input node thereof, the first and second semiconductor chips being stacked with each other in which the first to M-th penetration electrodes of the second semiconductor chip are vertically arranged respectively with the first to M-th penetration electrodes of the first semiconductor chip, in which the first to (M−2)-th penetration electrodes of the second semiconductor chip are electrically coupled to the second to (M−1)-th penetration electrodes of the first semiconductor chip, respectively. | 05-30-2013 |
20130207689 | PROGRAMMABLE TRANSCEIVER CIRCUIT - A multi-function programmable transceiver is described. The transceiver includes a driver circuit and a receiver circuit, which allows an Application Specific Integrated Circuit (ASIC) device to drive and receive data from other ASIC devices. Both the driver and receiver circuits share a common input/output (I/O) pin. The driver circuit can be programmed to provide one of the several driver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS. Other functional features of the transceiver that can be programmed are driving strengths or output impedance, output power supply voltage, single ended or differential mode of HSTL/SSTL transceivers, and class 1 or class 2 operations for SSTL/HSTL transceivers. The receiver circuit can also be programmed to provide one of the several receiver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS. | 08-15-2013 |
20130285701 | SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS - First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. | 10-31-2013 |
20130285702 | BUFFERING CIRCUIT, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHODS THEREOF - A multipoint low-voltage differential signaling (mLVDS)receiver of a semiconductor device and a buffering circuit of a semiconductor device, includes: an even-number data buffering unit configured to: sample even-number data from input data, amplify and output the even-number data in a section in which a positive clock is activated, and latch the even-number data in a section in which the positive clock is inactivated, and an odd-number data buffering unit configured to: sample odd-number data from the input data, amplify and output the odd-number data in a section in which a negative clock is activated, and latch the odd-number data in a section in which the negative clock is inactivated. | 10-31-2013 |
20130300455 | MULTIPLE SIGNAL FORMAT OUTPUT DRIVER WITH CONFIGURABLE INTERNAL LOAD - A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal. | 11-14-2013 |
20130335117 | PRE-DRIVER AND DIFFERENTIAL SIGNAL TRANSMITTER USING THE SAME - A pre-driver and a differential signal transmitter using the same are provided. The pre-driver includes a latch circuit and a driver buffer. The latch circuit includes latch units, first inverters, and second inverters. The latch units are coupled in series between a pair of differential input terminals and a pair of differential latch terminals, receive a pair of differential input signals through the pair of differential input terminals, and latch the pair of differential input signals according to a clock signal to provide a pair of differential latch signals through the pair of differential latch terminals. The first and second inverters are respectively coupled in series between the pair of differential latch terminals and a pair of differential output terminals. The driver buffer is coupled to the pair of differential output terminals to receive a pair of differential output signals, and accordingly provides a pair of differential pre-driver output signals. | 12-19-2013 |
20140028349 | DIFFERENTIAL OUTPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances. | 01-30-2014 |
20140070845 | TRANSMITTER SWING CONTROL CIRCUIT AND METHOD - Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver. | 03-13-2014 |
20140070846 | Interface Circuitry For A Test Apparatus - In one embodiment, a test apparatus includes a field programmable gate array (FPGA) including a first transmitter to communicate first signals according to current mode logic (CML) signaling and a first receiver to receive second signals according to the CML signaling, and an interface circuit to couple the FPGA to a device that is to communicate according to voltage mode signaling. The interface circuit may adapt the first signals communicated by the first transmitter according to the CML signaling to voltage mode signaling signals for receipt by the device. Other embodiments are described and claimed. | 03-13-2014 |
20140125380 | HIGH SPEED BUFFER WITH HIGH NOISE IMMUNITY - This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal. | 05-08-2014 |
20140145760 | High-Speed Low Power Stacked Transceiver - A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat. | 05-29-2014 |
20140159774 | DYNAMIC HIGH SPEED BUFFER WITH WIDE INPUT NOISE MARGIN - This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation and a high noise margin. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal. The first buffer exhibits a first hysteresis range while configured in a first hysteresis state and a second hysteresis range while configured in a second hysteresis state. The first buffer is configured to transition from the first to the second hysteresis state and vice versa in response to the control signal. The circuit includes a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal. The second buffer exhibits a third hysteresis range with a lower threshold and an upper threshold. | 06-12-2014 |
20140184270 | WIDTH SCALABLE CONNECTOR FOR HIGH BANDWIDTH IO INTERFACES - Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer. | 07-03-2014 |
20140266302 | ELEMENTS TO COUNTER TRANSMITTER CIRCUIT PERFORMANCE LIMITATIONS - Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit. | 09-18-2014 |
20140306734 | DATA OUTPUT CIRCUIT AND METHOD FOR DRIVING THE SAME - A data output circuit includes a data driving unit suitable for driving a data transmission line with a driving voltage corresponding to data during a data transmission operation, and a charging/discharging unit suitable for storing charges on the data transmission line and reuse the stored charges as the driving voltage. | 10-16-2014 |
20150109027 | DATA CONTROL CIRCUIT - A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit. | 04-23-2015 |
20150130510 | LEAKAGE REDUCTION IN OUTPUT DRIVER CIRCUITS - An output driver circuit may include a electrically conductive medium, an output logic inverter having a first switch adapted to couple a first positive supply voltage to the electrically conductive medium and a second switch adapted to couple a ground supply voltage to the conductive medium. A first biasing network includes a first input that is coupled to the conductive medium, a second input that receives a clock signal, and a first output that is adapted to couple a second positive supply voltage to each input of the first and the second switch. Based on the second switch coupling the conductive medium to the ground supply voltage and the received clock signal generating a logic low, the biasing network reverse biases the first switch by coupling the second positive supply voltage to the respective input of the first switch causing a leakage current reduction in the first switch. | 05-14-2015 |
20150381177 | COMMUNICATION CELL FOR AN INTEGRATED CIRCUIT OPERATING IN CONTACT AND CONTACTLESS MODE, ELECTRONIC CHIP COMPRISING THE COMMUNICATION CELL, ELECTRONIC SYSTEM INCLUDING THE CHIP, AND TEST APPARATUS - A communication cell for an integrated circuit includes a physical interface configured to supply an input signal (for example, a capacitive signal or an ohmic signal). A receiver circuit operates to receive the capacitive signal and generate a first intermediate signal. A buffer circuit operates to receive the ohmic signal and generate a second intermediate signal. An output stage including a selector device (for example, a multiplexer) configured to receive the first and second intermediate signals and selectively pass only one of those signals to the integrated circuit based on operating condition. The input signal may further be an inductive signal, with the output stage further functioning to selectively pass that signal based on operating condition. | 12-31-2015 |