| Entries |
| Document | Title | Date |
|---|
| 20080203468 | FinFET with Reduced Gate to Fin Overlay Sensitivity - Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure. | 08-28-2008 |
| 20080203469 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS HAVING DUAL GATE TRANSISTORS - An integrated circuit including an array of memory cells having dual gate transistors with curved current flow, and method for operation and fabrication is disclosed. In one embodiment, in a substrate an array of transistors is formed for selecting one of a plurality of memory cells by selecting a pair of adjacent word lines and a bit line. For minimizing the area of a memory cell and reducing complexity in production an array of dual gate transistors having a curved current flow is disclosed, wherein a small portion of a current is allowed to flow through adjacent memory cells. | 08-28-2008 |
| 20080224203 | SEMICONDUCTOR DEVICE HAVING ISLAND REGION - A semiconductor device includes a semiconductor substrate which includes an active region defined by an isolation film, and a source region and a drain region defined in the active region and spaced apart from each other in the active region. The source region and the drain region each have a first conductivity type. The semiconductor device further includes an island region defined in the active region between the source region and the drain region. The island region has the first conductivity type. | 09-18-2008 |
| 20080230832 | TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck. | 09-25-2008 |
| 20080258206 | Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same - A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second gate region is adjacent to the first gate region and extends above a surface of the semiconductor substrate. The second gate region includes a second conductive material. | 10-23-2008 |
| 20080258207 | Block Contact Architectures for Nanoscale Channel Transistors - A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch. | 10-23-2008 |
| 20080283906 | SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS - A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. | 11-20-2008 |
| 20080290402 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate. | 11-27-2008 |
| 20080296665 | MASK FOR MANUFACTURING TFT, TFT, AND MANUFACTURING THEREOF - A mask comprises a channel region half-exposure mask structure, a drain mask structure, and a source mask structure, wherein the channel region half-exposure mask structure comprises a channel region peripheral half-exposure mask structure, which extends from a portion that corresponds to a channel region of the TFT and is outside the portion. According to the present invention, problems such as a connection of the source/drain and a disconnection of the active layer in the channel region can be effectively prevented. | 12-04-2008 |
| 20080296666 | SEMICONDUCTOR DEVICE INCLUDING AN EMBEDDED CONTACT PLUG - A semiconductor device includes an active area isolated by an isolation area on a semiconductor substrate. A transistor includes a gate electrode extending across the active area, source/drain regions formed in the active area on both sides of the gate electrode, and impurity-containing contact plugs connected to the source/drain regions. The source/drain regions are formed by thermal diffusion of impurities from the impurity-containing contact plugs toward the active area, | 12-04-2008 |
| 20080296667 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a fin active region with a tapered side surface, a gate electrode that has a side surface covering portion covering a part of the side surface of the fin active region and a top surface covering portion covering a part of a top surface of the fin active region, and a source region and drain region formed in the fin active region. In at least a part of the side surface covering portion of the gate electrode, the width is wider at its bottom than at its top. Control of electric field by the gate electrode is improved. Punch-through is thus prevented. | 12-04-2008 |
| 20080308861 | DUAL GATE FINFET - A circuit has a fin supported by a substrate. A source is formed at a first end of the fin and a drain is formed at a second end of the fin. A pair of independently accessible gates are laterally spaced along the fin between the source and the drain. Each gate is formed around approximately three sides of the fin. | 12-18-2008 |
| 20090001453 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION - A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection. | 01-01-2009 |
| 20090001454 | SEMICONDUCTOR DEVICE AND TRANSISTOR - A semiconductor device includes active areas which are insulatedly separated from each other by element-separation insulating films; a gate insulating film formed on each active area; a gate electrode which extends across the active area via the gate insulating film; a source area and a drain area formed in the active area so as to interpose the gate electrode; and a fin-channel structure in which at the intersection between the active area and the gate electrode, trenches are provided at both sides of the active area, and part of the gate electrode is embedded in each trench via the gate insulating film, so that the gate electrode extends across a fin which rises between the trenches. In the gate insulating film, the film thickness of a part which contacts the bottom surface of each trench is larger than that of a part which contacts the upper surface of the fin. | 01-01-2009 |
| 20090008705 | BODY-CONTACTED FINFET - A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin. | 01-08-2009 |
| 20090014782 | Semiconductor Device and Manufacturing Method of the Same - Disclosed is a semiconductor device. The semiconductor device includes a first gate formed in a trench of a semiconductor substrate, a first gate oxide layer on the semiconductor substrate including the first gate, a first epitaxial layer on the first gate oxide layer, first source and drain regions in the first epitaxial layer at sides of the first gate, an insulating layer on the first epitaxial layer, a second epitaxial layer on the insulating layer, a second gate oxide layer on the second epitaxial layer, a second gate on the second gate oxide layer, and second source and drain regions in the second epitaxial layer below sides of the second gate. | 01-15-2009 |
| 20090020806 | ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R | 01-22-2009 |
| 20090020807 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed are a semiconductor device and a method for fabrication of the same. The fabrication method may include selectively forming an oxide layer pattern on a semiconductor substrate, forming an insulation layer pattern on the same substrate to cover edge portions of the oxide layer pattern, etching the oxide layer pattern and the substrate to form a recess as well as first and second oxide layer patterns corresponding to the edge portions of the oxide layer pattern, forming a third oxide layer pattern on the substrate in the recess to produce a gate insulation layer comprising the first, second, and third oxide layer patterns, and forming a gate pattern in the recess. The fabricated semiconductor device minimizes occurrence of current leakage such as gate induction drain leakage, among other things, thereby improving transistor performance. | 01-22-2009 |
| 20090039418 | MULTIPLE DEVICE TYPES INCLUDING AN INVERTED-T CHANNEL TRANSISTOR AND METHOD THEREFOR - A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region. | 02-12-2009 |
| 20090045456 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. The method includes forming a gate structure on a substrate. The gate structure includes a patterned gate dielectric layer, a patterned gate conductor layer, a cap layer and a spacer. Next, a first and a second recesses are formed in the substrate on the two sides of the gate structure. Thereafter, a protection layer is formed on the bottom surfaces of the first and the second recesses, and then a etching process is performed to laterally enlarge first and the second recesses towards the direction of the gate structure. Thereafter, a material layer is respectively formed in the first recess and the second recess. Afterward, two source/drain contact regions are respectively formed in the material layers of the first recess and the second recess. | 02-19-2009 |
| 20090065853 | FIN FIELD EFFECT TRANSISTOR - Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si | 03-12-2009 |
| 20090065854 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes second-conductive-type drift areas formed in a first-conductive-type well of a semiconductor substrate while being spaced apart from each other a vertical area protruding from the drift areas, and a second-conductive-type source/drain area formed on the vertical area. The vertical area can provide an extended drift area for a current path | 03-12-2009 |
| 20090072299 | SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE MOS TRANSISTOR AND FABRICATION METHOD THEREOF - A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an opening in a high voltage region. An oxide layer is deposited over the substrate and anisotropically etched to remain only on sidewalls of the opening. A first gate oxide layer is formed on the substrate in the opening, and the nitride layer is removed. Then a second gate oxide layer is formed over the substrate such that the second gate oxide layer has a relatively thinner thickness than the first gate oxide layer. Gate electrodes are then formed in the high voltage region and the low voltage region. | 03-19-2009 |
| 20090078991 | STRESS ENHANCED SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME - A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region. | 03-26-2009 |
| 20090085097 | METHODS OF FORMING NITRIDE STRESSING LAYER FOR REPLACEMENT METAL GATE AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include removing residual dielectric material from a metal gate structure, and then forming a stress relief layer on a top surface and on a sidewall region of the metal gate structure. A stress is introduced into a channel region disposed beneath the metal gate structure. | 04-02-2009 |
| 20090085098 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL MOS TRANSISTORS - A semiconductor device includes: a plurality of vertical MOS transistors sharing a gate electrode ( | 04-02-2009 |
| 20090101968 | STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A field effect transistor configured in a convex type Fin structure, in which diffusion layer | 04-23-2009 |
| 20090108335 | STRESS TRANSFER BY SEQUENTIALLY PROVIDING A HIGHLY STRESSED ETCH STOP MATERIAL AND AN INTERLAYER DIELECTRIC IN A CONTACT LAYER STACK OF A SEMICONDUCTOR DEVICE - By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly scaled semiconductor devices. | 04-30-2009 |
| 20090108336 | METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE - By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions. | 04-30-2009 |
| 20090114978 | VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions. | 05-07-2009 |
| 20090114979 | FinFET Device with Gate Electrode and Spacers - A semiconductor device includes a source region, a drain region, and a fin that connects the source region to the drain region. A gate electrode having a substantially planar surface overlies the fin and is positioned between the drain region and the source region. A first set of spacers is positioned between a first sidewall of the gate electrode and the source region and between a second sidewall of the gate electrode and the drain region. A second set of spacers is positioned on at least a portion of a top surface of the source region and the drain region and alongside at least a portion of the first set of spacers. At least a portion of sidewalls of the second set of spacers contacts a portion of the first or second sidewall of the gate electrode. | 05-07-2009 |
| 20090134454 | Fin-type field effect transistor, semiconductor device and manufacturing process therefor - A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode comprising an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion comprises an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer. | 05-28-2009 |
| 20090134455 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device including a substrate, a first well, a second well, a gate, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the substrate. The gate is formed on the substrate and overlaps the first and the second wells. The first doped region includes the second conductive type. The first doped region is formed in the first well and self-aligned with the gate. The second doped region includes the second conductive type. The second doped region is formed in the second well and self-aligned with the gate. The gate, the first and the second doped regions constitute a transistor. | 05-28-2009 |
| 20090152622 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region having a channel region, and containing silicon as a main component, second semiconductor regions sandwiching the first semiconductor region, formed of SiGe, and applying stress to the first semiconductor region, cap layers provided on the second semiconductor regions, and formed of silicon containing carbon or SiGe containing carbon, and silicide layers provided on the cap layers, and formed of nickel silicide or nickel-platinum alloy silicide. | 06-18-2009 |
| 20090166718 | METHOD OF PREDICTING DRAIN CURRENT IN MOS TRANSISTOR - Embodiments relate to a method of predicting a drain current that may accurately predict drain current in a linear region, a saturation region, and a breakdown region by modeling a drain current in the breakdown region, in which inconsistency occurs when a drain current depending on a drain voltage is calculated by a related are BSIM3-based modeling scheme, by an expression with a ternary operator, and adding the modeled drain current to the result of a related art BSIM3-based modeling scheme. | 07-02-2009 |
| 20090166719 | LDMOS SEMICONDUCTOR DEVICE MASK - Embodiments relate to an LDMOS semiconductor device mask that may reduce current leakage under a gate-off condition. According to embodiments, an LDMOS semiconductor device mask may include a moat mask to define a moat region, an NDT mask to define an N drift region, a PDT mask to define a P drift region, and a gate mask to form a gate. According to embodiments, a PDT mask may be configured to expose a field region of a semiconductor device. | 07-02-2009 |
| 20090173992 | SEMICONDUCTOR DEVICE WITH IMPROVED PERFORMANCE CHARACTERISTICS - The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess. | 07-09-2009 |
| 20090206394 | Strained Channel PMOS Transistor and Corresponding Production Method - The PMOS transistor (TR) has a channel width W of less than 1 micrometer, a channel length of less than or equal to 0.1 micrometer, and a distance of more than 0.5 micrometer between one edge of the channel and the corresponding edge of the active zone. The production of the active zone includes epitaxy on a first semiconductor material (SB) of an intermediate layer (CI) formed by a second semiconductor material having a lattice parameter greater than that of the first material, and epitaxy on the intermediate layer (CI) of an upper layer (CS) formed by the first material, anisotropic etching (GR) of the upper layer and the intermediate layer on either side of the two sidewalls of the gate region, and filling of the recesses thus formed by epitaxy (EPX) of the first material. | 08-20-2009 |
| 20090230463 | INTEGRATED CIRCUIT LONG AND SHORT CHANNEL METAL GATE DEVICES AND METHOD OF MANUFACTURE - A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench. | 09-17-2009 |
| 20090261407 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed is a semiconductor device. The semiconductor device includes a first gate formed in a trench of a semiconductor substrate, a first gate oxide layer on the semiconductor substrate including the first gate, a first epitaxial layer on the first gate oxide layer, first source and drain regions in the first epitaxial layer at sides of the first gate, an insulating layer on the first epitaxial layer, a second epitaxial layer on the insulating layer, a second gate oxide layer on the second epitaxial layer, a second gate on the second gate oxide layer, and second source and drain regions in the second epitaxial layer below sides of the second gate. | 10-22-2009 |
| 20090289298 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by a silicon-germanium intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 11-26-2009 |
| 20090294839 | RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION - Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure. | 12-03-2009 |
| 20090294840 | METHODS OF PROVIDING ELECTRICAL ISOLATION AND SEMICONDUCTOR STRUCTURES INCLUDING SAME - Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase the effective gate length (“L | 12-03-2009 |
| 20090302372 | Fin Field Effect Transistor Devices with Self-Aligned Source and Drain Regions - Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A filler layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins. The filler layer is removed to reveal the source and drain regions of the device, wherein the source and drain regions are intact and self-aligned with the gate stack. | 12-10-2009 |
| 20090309155 | VERTICAL TRANSISTOR WITH INTEGRATED ISOLATION - A vertical transistor with integrated isolation is provided. The vertical transistor includes a vertical semiconductor structure and an isolation layer on a bottom surface of the vertical semiconductor structure. The vertical transistor further includes a plurality of terminals on a top surface of the vertical semiconductor structure. | 12-17-2009 |
| 20090315101 | NOTCHED-BASE SPACER PROFILE FOR NON-PLANAR TRANSISTORS - A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin. | 12-24-2009 |
| 20100006926 | METHODS FOR FORMING HIGH PERFORMANCE GATES AND STRUCTURES THEREOF - Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different. | 01-14-2010 |
| 20100013004 | RECESSED CHANNEL TRANSISTOR AND METHOD FOR PREPARING THE SAME - A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor. | 01-21-2010 |
| 20100019313 | SEMICONDUCTOR CIRCUIT INCLUDING A LONG CHANNEL DEVICE AND A SHORT CHANNEL DEVICE - A semiconductor circuit is provided that includes a short channel device, and a long channel device that is electrically isolated from the short channel device. The long channel device comprises a plurality of first gate electrodes, a first source region adjacent one of the plurality of first gate electrodes, a first drain region adjacent another of the plurality of first gate electrodes, and a plurality of common source/drain regions positioned between adjacent ones of the plurality of first gate electrodes. The first gate electrodes each overlie portions of a layer of high-dielectric constant (k) gate insulator material. Each of the first gate electrodes are electrically coupled to at least one of the other first gate electrodes. | 01-28-2010 |
| 20100032748 | CMOS Thermoelectric Refrigerator - A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less than 300 nanometers wide, to reduce thermal conduction between the cold terminal and the IC substrate. Drain nodes of the NMOS and PMOS transistors are connected through hot terminals to a biasing circuit. The drain node of the NMOS transistor is biased positive with respect to the drain node of the PMOS transistor, to extract hot electrons and hot holes from the cold terminal. Biases on the drain nodes and gates of the NMOS and PMOS transistors may be adjusted to optimize the efficiency of the CMOS thermoelectric refrigerator or maximize the thermal power of the CMOS thermoelectric refrigerator. The cold terminal may be configured to cool a selected component in the IC, such as a transistor. | 02-11-2010 |
| 20100038705 | FIELD EFFECT DEVICE WITH GATE ELECTRODE EDGE ENHANCED GATE DIELECTRIC AND METHOD FOR FABRICATION - A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method. | 02-18-2010 |
| 20100044780 | TRANSISTOR WITH GAIN VARIATION COMPENSATION - A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel. | 02-25-2010 |
| 20100044781 | SEMICONDUCTOR DEVICE - To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon substrate. A silicon germanium layer having a dielectric constant higher than that of the p-type silicon substrate is formed to have a thickness of 30 nm or less on the p-type well. Then, on the silicon germanium layer, a germanium layer having a dielectric constant higher than that of the silicon germanium layer is formed to have a thickness of 3-40 nm by epitaxial growing. The germanium layer is permitted to be a channel region; and a gate insulating film, a gate electrode, a side wall insulating film, an n-type impurity diffusion region and a silicide layer are formed. | 02-25-2010 |
| 20100044782 | INTEGRATED CIRCUIT HAVING LONG AND SHORT CHANNEL METAL GATE DEVICES AND METHOD OF MANUFACTURE - Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the device, and is formed substantially from the same metal as is the LC metal gate. | 02-25-2010 |
| 20100096690 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL AREA - A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region. | 04-22-2010 |
| 20100117142 | Semiconductor Device for Improving the Peak Induced Voltage in Switching Converter - A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region. | 05-13-2010 |
| 20100127321 | Semiconductor and Manufacturing Method for the Same - A semiconductor device and a manufacturing method for the same are disclosed. The semiconductor device includes a gate pattern formed at an upper part of the semiconductor substrate to overlap one side of a drift region, and a shallow oxide region disposed adjacent to the gate pattern, having a shallower depth than a plurality of device isolation layers. | 05-27-2010 |
| 20100148243 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate. | 06-17-2010 |
| 20100155827 | Semiconductor device having a multi-channel type MOS transistor - In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor. | 06-24-2010 |
| 20100163970 | Trigate transistor having extended metal gate electrode - A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer. | 07-01-2010 |
| 20100163971 | Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights - A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate. | 07-01-2010 |
| 20100171170 | SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 07-08-2010 |
| 20100193860 | SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION - In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions. | 08-05-2010 |
| 20100207196 | SEMICONDUCTOR DEVICE HAVING INTERNAL GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a main gate formed on a semiconductor substrate and a source region and a drain region formed in a surface of the semiconductor substrate on opposite sides of the main gate. An internal gate formed within a portion of the main gate that adjoins the source region. | 08-19-2010 |
| 20100320529 | INTEGRATED CIRCUIT SYSTEM WITH HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor. | 12-23-2010 |
| 20110001185 | DEVICE - A semiconductor device includes a first diffusion region and a second diffusion region in an active region surrounded by an isolation insulation region, a recessed trench region formed between the first diffusion region and the second diffusion region, a gate insulation film formed on the trench region, a gate electrode formed on the gate insulation film to fill the trench region therewith, and a protection insulation film formed in an upper part of the region interposed between the gate insulation film and the isolation insulation region. | 01-06-2011 |
| 20110006359 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material. | 01-13-2011 |
| 20110049613 | ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF - A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer. | 03-03-2011 |
| 20110057253 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area. | 03-10-2011 |
| 20110062512 | NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION - A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 03-17-2011 |
| 20110108908 | MULTILAYERED BOX IN FDSOI MOSFETS - A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long. | 05-12-2011 |
| 20110147828 | SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION - Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance. | 06-23-2011 |
| 20110156133 | SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME - A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm. | 06-30-2011 |
| 20110204434 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes, a gate structure having a gate dielectric layer, a gate electrode, and a spacer, which are each formed on a substrate, a first impurity area formed in a portion of the substrate located below the spacer, a second impurity area in contact with a sidewall of the first impurity area and formed in the substrate on both sides of the gate structure, and a dielectric pattern in contact with a portion of the first impurity area and formed on a sidewall of the second impurity area. At this time, the second impurity area may include an upper part with an upward-narrowing width and a lower part with a downward-narrowing width. | 08-25-2011 |
| 20110210388 | Integrated native device without a halo implanted channel region and method for its fabrication - According to one embodiment, a semiconductor structure including an integrated native device without a halo implanted channel region comprises an arrangement of semiconductor devices formed over a common substrate, the arrangement includes native devices disposed substantially perpendicular to non-native devices, wherein each of the native and non-native devices includes a respective channel region. The arrangement is configured to prevent formation of halo implants in the native device channel regions during halo implantation of the non-native device channel regions. In one embodiment, the disclosed native devices comprise native transistors capable of avoiding threshold voltage roll-up for channel lengths less than approximately 0.5 um. | 09-01-2011 |
| 20110227144 | HIGH-PERFORMANCE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process. Through the present invention, the dopants in the Halo ion-implanted region improperly introduced to the source region and the drain region may be reduced, and then the overlap between the Halo ion-implantation region and the dopant region of the source/drain regions may be reduced, thus to reduce the band-band leakage current in the MOSFET, and hence improve the performance of the device. | 09-22-2011 |
| 20110254080 | TUNNEL FIELD EFFECT TRANSISTOR - A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack. | 10-20-2011 |
| 20110266613 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shield electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shield electrodes. A gate electrode in at least one of the trenches is connected to at least one shield electrode in the trenches. | 11-03-2011 |
| 20120001254 | Transistor With Embedded Si/Ge Material Having Reduced Offset and Superior Uniformity - In sophisticated semiconductor devices, a strain-inducing embedded semiconductor alloy may be provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, wherein transistors which may not require an embedded strain-inducing semiconductor alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration. Consequently, superior strain conditions may be achieved in one type of transistor, while generally reduced variations in transistor characteristics may be obtained for any type of transistors. | 01-05-2012 |
| 20120007168 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING SHORT CHANNEL EFFECT - A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region. | 01-12-2012 |
| 20120086071 | STRESS MEMORIZATION PROCESS IMPROVEMENT FOR IMPROVED TECHNOLOGY PERFORMANCE - Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions. | 04-12-2012 |
| 20120104486 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein only the source region comprises at least one dislocation. The method for forming a transistor according to the present invention comprises forming a mask layer on a semiconductor substrate on which a gate has been formed so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer to only expose at least a portion of a source region; performing a first ion implantation to the exposed portion of the source region; and annealing the semiconductor substrate so as to form a dislocation in the exposed portion of the source region. | 05-03-2012 |
| 20120119284 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material. | 05-17-2012 |
| 20120139033 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Semiconductors devices and methods of making semiconductor devices are provided. According to one embodiment, a semiconductor device can include a p-type field effect transistor area having an active region with an epitaxial layer grown thereupon and an isolation feature adjacent to the active region. A height of the isolation feature equals or exceeds a height of an interface between the epitaxial layer and the active region. More particularly, a height of the isolation feature in the corner of a junction between the isolation feature and the action region equals or exceeds the height to the interface between the epitaxial layer and the active region. | 06-07-2012 |
| 20120217574 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor clement is formed in the clement region, the transistor clement having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer. | 08-30-2012 |
| 20120286350 | TUNNEL FIELD EFFECT TRANSISTOR - An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side. | 11-15-2012 |
| 20120306002 | ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF - This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate. | 12-06-2012 |
| 20120319188 | ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE AND A GATE TAP AND A PROCESS OF FORMING THE SAME - An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device. | 12-20-2012 |
| 20130032876 | Replacement Gate ETSOI with Sharp Junction - A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure. | 02-07-2013 |
| 20130140625 | Field-Effect Transistor and Method of Making - The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor. | 06-06-2013 |
| 20130240979 | GATE STRUCTURES - A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening. | 09-19-2013 |
| 20130320427 | GATED CIRCUIT STRUCTURE WITH SELF-ALIGNED TUNNELING REGION - A tunnel field-effect transistor is provided, which includes a fin-shaped, source-drain circuit structure with a source region and a drain region. The circuit structure is angled in cross-sectional elevation, and includes a first portion and a second portion. The first portion extends away from the second portion, and the source region is disposed in the first or second portion, and the drain region is disposed in the other of the first or second portion. The transistor further includes a gate electrode for gating the circuit structure and a self-aligned tunneling region. The tunneling region is self-aligned to at least a portion of the circuit structure and extends between the gate electrode and the first or second portion of the fin-shaped circuit structure, and the self-aligned tunneling region is at least partially disposed in parallel, spaced opposing relation to a control surface of the gate electrode. | 12-05-2013 |
| 20130320428 | ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE AND A GATE TAP - An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device. | 12-05-2013 |
| 20130341704 | VARIABLE GATE WIDTH FOR GATE ALL-AROUND TRANSISTORS - Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active. | 12-26-2013 |
| 20140042521 | MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created. | 02-13-2014 |
| 20140077286 | FIELD-EFFECT TRANSISTOR - According to one embodiment, a field-effect transistor is provided with a first conductivity-type first semiconductor layer, a source layer formed of a second conductivity-type semiconductor, a drain layer formed of a second conductivity-type semiconductor, and a gate electrode. The source layer is located on the first semiconductor layer. The drain layer is also located on the first semiconductor layer and is separated from the source layer. The gate electrode is located adjacent to the side wall of the drain layer which faces the source layer, and may also be located adjacent to the side wall of the source layer facing the drain layer, and on the first semiconductor layer with a gate insulating film formed therebetween. The upper surface of the gate electrode is recessed with respect to at least the upper surface of the drain layer. | 03-20-2014 |
| 20140084359 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a first electrode, and a contact region. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The first electrode has a first and a second portion. The first portion is provided in a first direction and has a lower end being positioned below a lower end of the third semiconductor region. The second portion is in contact with the first portion and is provided on the third semiconductor region. The contact region is provided between the first portion and the second semiconductor region and is electrically connected to the first electrode and the second semiconductor region. | 03-27-2014 |
| 20140097487 | PLASMA DOPING A NON-PLANAR SEMICONDUCTOR DEVICE - In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different. | 04-10-2014 |
| 20140117435 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 05-01-2014 |
| 20140131790 | FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES - A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants. | 05-15-2014 |
| 20140159139 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A transistor includes a substrate, a gate over the substrate, a source and a drain over the substrate on opposite sides of the gate, a first silicide on the source, and a second silicide on the drain. Only one of the drain or the source has an unsilicided region adjacent to the gate to provide a resistive region. | 06-12-2014 |
| 20140203348 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions. | 07-24-2014 |
| 20140209997 | THIN FILM TRANSISTOR - A thin film transistor based on carbon nanotubes includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconductor layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The work-functions of the source electrode and of the drain electrode are different from that of the semiconductor layer, enabling the creation of both p-type and n-type field-effect transistors. | 07-31-2014 |
| 20140264555 | SILICON ON GERMANIUM - A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide. | 09-18-2014 |
| 20140346587 | INTEGRATED CIRCUIT HAVING MOSFET WITH EMBEDDED STRESSOR AND METHOD TO FABRICATE SAME - A method includes forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a channel region of a transistor; depositing a layer of crystalline dielectric material onto a surface of the substrate that is exposed within the recess; and depositing stressor material into the recess such that the layer of dielectric material is disposed between the stressor material and the surface of the substrate. A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 11-27-2014 |
| 20140353741 | BOTTLED EPITAXY IN SOURCE AND DRAIN REGIONS OF FETS - A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions. | 12-04-2014 |
| 20140367768 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution. | 12-18-2014 |
| 20150035046 | SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR - A semiconductor device includes a fin portion protruding from a substrate. The fin portion includes a base part, an intermediate part on the base part, and a channel part on the intermediate part. A width of the intermediate part is less than a width of the base part and greater than a width of the channel part. A gate electrode coves both sidewalls and a top surface of the channel part, and a device isolation pattern covers both sidewalls of the base part and both sidewalls of the intermediate part. | 02-05-2015 |
| 20150084116 | DEVICES INCLUDING ULTRA-SHORT GATES AND METHODS OF FORMING SAME - Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width, A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess. | 03-26-2015 |
| 20150372102 | SEMICONDUCTOR DEVICE - The parasitic capacitance formed by a gate electrode, a contact, and a side wall is reduced. | 12-24-2015 |
| 20160013272 | FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING FIELD EFFECT TRANSISTOR | 01-14-2016 |
| 20160043177 | SEMICONDUCTOR DEVICE WITH THINNED CHANNEL REGION AND RELATED METHODS - A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers. | 02-11-2016 |
| 20160049399 | GATE STRUCTURES FOR SEMICONDUCTOR DEVICES WITH A CONDUCTIVE ETCH STOP LAYER - One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers. | 02-18-2016 |
| 20160049498 | FIELD EFFECT TRANSISTOR WITH NON-DOPED CHANNEL - Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a top surface; a first doped region in proximity to the top surface; a non-doped region positioned in proximity to the top surface and adjacent to the first doped region, having a first width; a metal gate positioned over the non-doped region and over a portion of the first doped region, having a second width. The first width is smaller than the second width, and material constituting the non-doped region is different from material constituting the substrate. | 02-18-2016 |
| 20160163798 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode. | 06-09-2016 |
| 20160181394 | III-V MOSFETS With Halo-Doped Bottom Barrier Layer | 06-23-2016 |
| 20160190233 | TRANSISTOR WITH WURTZITE CHANNEL - A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [−2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric. | 06-30-2016 |
| 20160190281 | EXTENDED-DRAIN TRANSISTOR USING INNER SPACER - An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device. | 06-30-2016 |
| 20160204214 | ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE | 07-14-2016 |
| 20160254358 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 09-01-2016 |
| 20190148547 | SEMICONDUCTOR DEVICE | 05-16-2019 |
