| Entries |
| Document | Title | Date |
|---|
| 20080197412 | MULTI-LAYER SOURCE/DRAIN STRESSOR - A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element. | 08-21-2008 |
| 20080217685 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation layer for dividing a silicon substrate into an active region and an inactive region, a gate electrode formed over the silicon substrate, a gate oxide layer formed around a sidewall of the gate electrode to expose an upper portion of the sidewall of the gate electrode, a gate insulation layer formed between the silicon substrate and the gate electrode, an epitaxial layer formed over the gate electrode and the active region around the gate electrode; a lightly doped drain region formed in a surface of the silicon substrate around the gate electrode, a gate spacer formed around the sidewall of the gate electrode including the gate oxide layer; source and drain regions formed in the surface of the silicon substrate at sides of the gate spacer, and a protective layer formed over the entire surface of the silicon substrate. | 09-11-2008 |
| 20080224212 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is provided. A first insulation layer and a second insulation layer are formed over the substrate having a gate. A spacer etching process is performed to form an etched first insulation layer and an etched second insulation layer. The etched first insulation layer partially protrudes from the substrate and contacts sidewalls of the gate. The etched second insulation layer is removed through a selective epitaxial growth (SEG) process that forms an epitaxial layer over the exposed substrate. One of facets of the epitaxial layer is formed on the protruding portion of the etched first insulation layer. A third insulation layer is formed on sidewalls of the etched first insulation layer and the one of the facets of the epitaxial layer is covered by the third insulation layer. | 09-18-2008 |
| 20080237707 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, having a lower impurity concentration than the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, a base region of the second conductivity type provided in the third semiconductor layer, a source region of the first conductivity type provided in the base region, a first drain region of the first conductivity type provided in the third semiconductor layer, the first drain region being apart from the base region, a lightly doped drain region of the first conductivity type provided between the first drain region and the source region, the lightly doped drain region being in contact with the first drain region, the lightly doped drain having lower impurity concentration than the first drain region, a second drain region of the first conductivity type provided in the third semiconductor layer, and provided between the second semiconductor layer and the first drain region, the second drain region being in contact with the first drain region, a third drain region of the second conductivity type provided in the third semiconductor layer, provided between the second drain region and the second semiconductor layer, the third drain region being in contact with the second drain region. | 10-02-2008 |
| 20080246087 | MOS TRANSISTOR FOR REDUCING SHORT-CHANNEL EFFECTS AND ITS PRODUCTION - The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove. And the process for the MOS transistor includes the following steps: forming the groove; carrying out well implantation, anti-punchthrough implantation and threshold-voltage adjustment implantation; forming the gate stack in the groove which comprising patterning the gate electrode; carrying lightly doped drain implantation and halo implantation; forming the gate sidewall spacer; carrying source and drain implantation to get the source and drain areas; forming a metal silicide layer on the source and drain areas. | 10-09-2008 |
| 20080246088 | Self-Aligned Lightly Doped Drain Recessed-Gate Thin-Film Transistor - A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench. | 10-09-2008 |
| 20080258216 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a field effect transistor including a semiconductor substrate having a channel-forming region, an insulating film formed on the semiconductor substrate, a gate electrode trench formed in the insulating film, a gate insulating film formed at the bottom of the gate electrode trench, a gate electrode formed by filling the gate electrode trench with a layer on the gate insulating film, offset spacers composed of silicon oxide or boron-containing silicon nitride and formed as a portion of the insulating film to constitute the sidewall of the gate electrode trench, sidewall spacers formed as a portion of the insulating film on both sides of the offset spacers on the side away from the gate electrode, and source-drain regions having an extension region and formed in the semiconductor substrate and below at least the offset spacers and the sidewall spacers. | 10-23-2008 |
| 20080265321 | Fin Field-Effect Transistors - A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used. | 10-30-2008 |
| 20080283915 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a high voltage semiconductor device and a method of manufacturing the same. The high voltage semiconductor device includes: a semiconductor substrate; a first high voltage N-type well formed on the semiconductor substrate; a first high voltage P-type well formed inside the first high voltage N-type well; a second high voltage N-type well formed to surround the first high voltage P-type well inside the first high voltage N-type well; a gate dielectric layer and a gate electrode formed to be stacked on the upper of the first high voltage P-type well; and a first N-type high-concentration impurity region formed at both sides of the gate electrode in the first high voltage P-type well, wherein the concentration of the upper region of the first high voltage N-type well is lower than that of the lower region thereof, based on a portion formed with the first high voltage P-type well. Therefore, the present invention can apply bulk bias, simplify a process, improve punch through breakdown voltage in the P-type well formed inside a low-concentration deep N-type well, reduce field of a high-concentration N-type impurity region, and reduce resistance. | 11-20-2008 |
| 20080290412 | SUPPRESSING SHORT CHANNEL EFFECTS - An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate. | 11-27-2008 |
| 20080308864 | ASYMMETRICAL MOS TRANSISTOR AND FABRICATION METHOD THEREOF AND DEVICES USING THE SAME - An asymmetrical MOS transistor having characteristics of a variable resistor and a transistor is provided. The asymmetrical MOS transistor comprises a substrate, a gate structure, a pair of spacers, a pair of offset spacers, a source region, a drain region, and an extension region. Herein, the extension region is disposed in the substrate under apportion of the gate structure and one of the pair of spacers. And, the extension region connects one of the source region or the drain region. The extension region is a heavily doping region. | 12-18-2008 |
| 20090001463 | FINFET FIELD EFFECT TRANSISTOR INSULTATED FROM THE SUBSTRATE - A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates. | 01-01-2009 |
| 20090014793 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; a pair of first diffusion layer regions provided near a top face of the semiconductor substrate; a channel region provided between the first diffusion layer regions of the semiconductor substrate; a gate insulation film provided on the channel region and on the semiconductor substrate such as to overlap with at least part of the first diffusion layer regions; a gate electrode provided on the insulation film; a pair of silicon selective growth layers provided on the semiconductor substrate at both sides of the gate electrode, each of the pair of silicon selective growth layers overlapping with at least part of the first diffusion layer regions, and being provided at a distance from the gate electrode; second diffusion layer regions provided in each of the silicon selective growth layers, peak positions of impurity concentration of the second diffusion layer regions being shallower than bottoms of the silicon selective growth layers; and third diffusion layer regions provided near side faces of the silicon selective growth layers, and electrically connecting the first diffusion layer regions to the second diffusion layer regions. | 01-15-2009 |
| 20090014794 | MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME - The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content. | 01-15-2009 |
| 20090020815 | Semiconductor device and manufacturing method of the same - An object of the present invention is to provide a semiconductor device having a structure which can realize not only suppressing a punch-through current but also reusing a silicon wafer which is used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. The semiconductor device can suppress the punch-through current by forming a semiconductor film in which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted over a substrate having an insulating surface, and forming a channel formation region using a semiconductor film of stacked layers obtained by bonding a single crystal semiconductor film to the semiconductor film by an SOI technique. | 01-22-2009 |
| 20090026540 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2 | 01-29-2009 |
| 20090039426 | EXTREMELY-THIN SILICON-ON-INSULATOR TRANSISTOR WITH RAISED SOURCE/DRAIN - An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor. | 02-12-2009 |
| 20090039427 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET. | 02-12-2009 |
| 20090050962 | MOSFET WITH ISOLATION STRUCTURE FOR MONOLITHIC INTEGRATION AND FABRICATION METHOD THEREOF - A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors. | 02-26-2009 |
| 20090050963 | STRESSED MOS DEVICE AND METHODS FOR ITS FABRICATION - Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The vertical portion overlies a channel region in an underlying substrate and has a first width; the horizontal portion has a second greater width. A tensile stressed film is formed overlying the second horizontal portion, and a material having a second Young's modulus less than the first Young's modulus fills the space below the second horizontal portion. The tensile stressed film imparts a stress on the horizontal portion of the gate electrode and this stress is transmitted through the vertical portion to the channel of the device. The stress imparted to the channel is amplified by the ratio of the second width to the first width. | 02-26-2009 |
| 20090057760 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and fabricating method thereof are disclosed, by which channel mobility is enhanced and by which effect of flicker noise can be minimized. Embodiments relate to a method of fabricating a semiconductor device which includes forming a first epi-layer over a substrate, forming a second epi-layer over the first epi-layer, forming a gate electrode over the second epi-layer, forming a spacer over both sides of the gate electrode, etching an area adjacent both sides of the spacer to a depth of the substrate, forming an LDD region in a region under the spacer, and forming a third epi-layer for a source/drain region over the etched area adjacent both of the sides of the spacer. | 03-05-2009 |
| 20090057761 | Fin field effect transistor and method of manufacturing the same - Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current. | 03-05-2009 |
| 20090065865 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a transistor structure including a gate electrode and a first channel region and source/drain regions on a substrate, and a second channel region and source/drain regions provided on the transistor structure. Accordingly, transistor operations can utilize the current path above and below the gate electrode. | 03-12-2009 |
| 20090072310 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE - A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure. | 03-19-2009 |
| 20090096023 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device that eliminates the cause of increase in leakage current and therefore suppresses power increase in a highly integrated circuit by forming a shallow junction using a dopant-containing oxide film after etching a semiconductor substrate in source and drain regions. | 04-16-2009 |
| 20090121286 | Integrated Circuit Comprising a Field Effect Transistor and Method of Fabricating the Same - An integrated circuit includes a field effect transistor including: a gate electrode disposed adjacent to a surface of semiconductor substrate and a source/drain region disposed in the semiconductor substrate and adjacent to the surface. A net dopant concentration of a first section of the source/drain region decreases towards the gate electrode along a direction perpendicular to the surface. | 05-14-2009 |
| 20090140335 | Drain-Extended Field Effect Transistor - A drain-extended field effect transistor includes a drain contact region and a drain extension region. The drain-extended field effect transistor further includes an electrostatic discharge protection region that is electrically connected between the drain contact region and the drain extension region to protect the drain-extended field effect transistor against electrostatic discharge. The electrostatic discharge protection region has a dopant concentration level such that in case of an electrostatic discharge event, a base push-out is prevented from reaching the drain contact region. | 06-04-2009 |
| 20090152629 | METHODS OF SELECTIVELY OXIDIZING SEMICONDUCTOR STRUCTURES, AND STRUCTURES RESULTING THEREFROM - Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed. | 06-18-2009 |
| 20090166737 | Method for Manufacturing a Transistor - A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure. | 07-02-2009 |
| 20090242983 | SEMICONDUCTOR DEVICE HAVING A FIELD EFFECT TRANSISTOR USING A HIGH DIELECTRIC CONSTANT GATE INSULATING FILM AND MANUFACTURING METHOD OF THE SAME - In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film. | 10-01-2009 |
| 20090289300 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r | 11-26-2009 |
| 20090294850 | METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer. | 12-03-2009 |
| 20090315110 | High voltage MOS array with gate contact on extended drain region - In an extended drain MOS device used in high voltage applications, switching characteristics are improved by providing for at least one base contact in the active region in the extended drain space. | 12-24-2009 |
| 20100038713 | Self-aligned tunneling pocket in field-effect transistors and processes to form same - A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body. | 02-18-2010 |
| 20100065910 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first MISFET and a second MISFET, wherein the first MISFET includes a semiconductor substrate | 03-18-2010 |
| 20100078721 | SEMICONDUCTOR DEVICE - A field-effect transistor ( | 04-01-2010 |
| 20100096698 | STRESS ENHANCED TRANSISTOR - Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer | 04-22-2010 |
| 20100181618 | EXTENDED DRAIN TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - An extended drain transistor ( | 07-22-2010 |
| 20110012197 | METHOD OF FABRICATING TRANSISTORS AND A TRANSISTOR STRUCTURE FOR IMPROVING SHORT CHANNEL EFFECT AND DRAIN INDUCED BARRIER LOWERING - A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively. | 01-20-2011 |
| 20110073946 | LDMOS TRANSISTOR - An LDMOS transistor ( | 03-31-2011 |
| 20110079850 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE - A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure. | 04-07-2011 |
| 20110108917 | SEMICONDUCTOR DEVICE WITH HIGH VOLTAGE TRANSISTOR - A semiconductor device includes: a p-type active region; a gate electrode traversing the active region; an n-type LDD region having a first impurity concentration and formed from a drain side region to a region under the gate electrode; a p-type channel region having a second impurity concentration and formed from a source side region to a region under the gate electrode to form an overlap region with the LDD region under the gate electrode, the channel region being shallower than the LDD region; an n-type source region formed outside the gate electrode; and an n | 05-12-2011 |
| 20110186928 | Semiconductor device - A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type having a top surface and a rear surface, a semiconductor layer of a second conductivity type formed on the top surface of the semiconductor substrate, having a top surface and a rear surface, and having the rear surface in contact with the top surface of the semiconductor substrate, a body region of the first conductivity type formed in a top layer portion of the semiconductor layer, a first impurity region of the second conductivity type formed in a top layer portion of the semiconductor layer and spaced apart from the body region, a second impurity region of the second conductivity type formed in a top layer portion of the body region and spaced apart from a peripheral edge of the body region, a gate electrode formed on the semiconductor layer and opposed to a portion between the peripheral edge of the body region and a peripheral edge of the second impurity region, a field insulating film formed in a portion of the top surface of the semiconductor layer between the body region and the first impurity region, and a plurality of field plates formed on the field insulating film and spaced apart from each other, and a spacing between adjacent field plates decreases as the body region is approached from the first impurity region. | 08-04-2011 |
| 20110221000 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region. | 09-15-2011 |
| 20110254089 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME - A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring. | 10-20-2011 |
| 20110298049 | CMOS Device with Raised Source and Drain Regions - A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate. | 12-08-2011 |
| 20110316079 | Shallow Junction Formation and High Dopant Activation Rate of MOS Devices - A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer. | 12-29-2011 |
| 20120007179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped with impurity different from the first well region's in a second location on a surface of the substrate, an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist, a gate insulating layer formed on the surface of the first and the second well regions and the surface of the overlapping region, a gate electrode formed on the gate insulating layer, a source region formed on an upper portion of the first well region, and a drain region formed on an upper portion of the second well region. The semiconductor device may also include a separating unit, which is formed in the second well region on the drain side and may be formed as a shallow trench isolation (STI) region having a lower depth than the second well region. | 01-12-2012 |
| 20120139042 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench. | 06-07-2012 |
| 20120292698 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An LDMOS device includes a gate which is formed on and/over over a substrate; a source and a drain which are arranged to be separated from each other on both sides of the substrate with the gate interposed therebetween; and a field oxide film formed to have a step between the gate and the drain. The LDMOS device further includes a drift region formed of first conduction type impurity ions between the gate and the drain in the substrate; and at least one internal field ring formed in the drift region by selectively implanting a second conduction type impurity in accordance with the step of the field oxide film. | 11-22-2012 |
| 20120292699 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A semiconductor apparatus and a manufacturing method therefor is described. The semiconductor apparatus comprises a substrate and a gate structure for a N-channel semiconductor device above the substrate. A recess is formed at a lower end portion of at least one of two sides of the gate where it is adjacent to a source region and a drain region, of the N-channel semiconductor. The channel region of the N-channel semiconductor device has enhanced strain. The apparatus can further have a gate structure for a P-channel semiconductor device above the substrate. | 11-22-2012 |
| 20120299097 | Semiconductor Architecture Having Field-effect Transistors Especially Suitable for Analog Applications - An insulated-gate field-effect transistor ( | 11-29-2012 |
| 20120313167 | SEMICONDUCTOR DEVICE HAVING GRADIENT DOPING PROFILE - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate over a substrate. The method includes performing a first implantation process to form a first doped region in the substrate, the first doped region being adjacent to the gate. The method includes performing a second implantation process to form a second doped region in the substrate, the second doped region being formed farther away from the gate than the first doped region, the second doped region having a higher doping concentration level than the first doped region. The method includes removing portions of the first and second doped regions to form a recess in the substrate. The method includes epitaxially growing a third doped region in the recess, the third doped region having a higher doping concentration level than the second doped region. | 12-13-2012 |
| 20130015524 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOFAANM Hsu; Chun-WeiAACI Taipei CityAACO TWAAGP Hsu; Chun-Wei Taipei City TWAANM Huang; Po-ChengAACI Chiayi CityAACO TWAAGP Huang; Po-Cheng Chiayi City TWAANM Tsai; Teng-ChunAACI Tainan CityAACO TWAAGP Tsai; Teng-Chun Tainan City TWAANM Hsu; Chia-LinAACI Tainan CityAACO TWAAGP Hsu; Chia-Lin Tainan City TWAANM Lin; Chih-HsunAACI Ping-Tung CountyAACO TWAAGP Lin; Chih-Hsun Ping-Tung County TWAANM Chen; Yen-MingAACI New Taipei CityAACO TWAAGP Chen; Yen-Ming New Taipei City TWAANM Chen; Chia-HsiAACI Kao-Hsiung CityAACO TWAAGP Chen; Chia-Hsi Kao-Hsiung City TWAANM Kung; Chang-HungAACI Kaohsiung CityAACO TWAAGP Kung; Chang-Hung Kaohsiung City TW - A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate. | 01-17-2013 |
| 20130026569 | METHODS AND APPARATUS RELATED TO HOT CARRIER INJECTION RELIABILITY IMPROVEMENT - In one general aspect, an apparatus can include a substrate, a gate electrode, and a gate dielectric having at least a portion disposed between the gate electrode and the substrate. The apparatus can include a heavily doped drain region disposed within the substrate, and a lightly doped drain region within the substrate and in contact with the heavily doped drain region. The apparatus can also include a medium doped drain region disposed within the lightly doped drain region and having a dopant concentration between a dopant concentration of the heavily doped drain region and a dopant concentration of the lightly doped drain region. | 01-31-2013 |
| 20130056825 | MOS DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 03-07-2013 |
| 20130161743 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 06-27-2013 |
| 20130187227 | FLATBAND SHIFT FOR IMPROVED TRANSISTOR PERFORMANCE - An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. | 07-25-2013 |
| 20130256796 | MOSFET WITH SLECTIVE DOPANT DEACTIVATION UNDERNEATH GATE - A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device. | 10-03-2013 |
| 20130299905 | BUTTED CONTACT SHAPE TO IMPROVE SRAM LEAKAGE CURRENT - The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends along a length (i.e., the larger dimension of the butted contact) from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current. | 11-14-2013 |
| 20130313642 | Semiconductor Device Having Gradient Doping Profile - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate over a substrate. The method includes performing a first implantation process to form a first doped region in the substrate, the first doped region being adjacent to the gate. The method includes performing a second implantation process to form a second doped region in the substrate, the second doped region being formed farther away from the gate than the first doped region, the second doped region having a higher doping concentration level than the first doped region. The method includes removing portions of the first and second doped regions to form a recess in the substrate. The method includes epitaxially growing a third doped region in the recess, the third doped region having a higher doping concentration level than the second doped region. | 11-28-2013 |
| 20140001553 | METHOD AND SYSTEM FOR IMPROVED ANALOG PERFORMANCE IN SUB-100 NANOMETER CMOS TRANSISTORS | 01-02-2014 |
| 20140021545 | POCKET COUNTERDOPING FOR GATE-EDGE DIODE LEAKAGE REDUCTION - A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions. | 01-23-2014 |
| 20140021546 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in the semiconductor substrate, a second region of the first conductivity type formed in the first region, a source region of the second conductivity type formed in the second region, a drain region of the second conductivity type formed in the first region, a first junction part including a part of a border between the first region and the second region, which is on the side of the drain region, a second junction part including a part of the border between the first region and the second region, which is at a location different from the first junction part, a gate electrode formed above the first junction, and a conductor pattern formed above the second junction part and being electrically independent from the gate electrode. | 01-23-2014 |
| 20140084369 | SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION - Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance. | 03-27-2014 |
| 20140103433 | HIGH-VOLTAGE METAL-DIELECTRIC-SEMICONDUCTOR DEVICE AND METHOD OF THE SAME - A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region. | 04-17-2014 |
| 20140110783 | HIGH GAIN DEVICE - A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions. | 04-24-2014 |
| 20140131799 | METHOD AND APPARATUS FOR SELECTIVELY IMPROVING INTEGRATED DEVICE PERFORMANCE - An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom. | 05-15-2014 |
| 20140175548 | High Temperature Gate Replacement Process - A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate. | 06-26-2014 |
| 20140191318 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR, METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface. | 07-10-2014 |
| 20140264589 | SEMICONDUCTOR STRUCTURE PROFILE - One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. In some embodiments, a semiconductor structure includes a substrate, a first lightly doped drain (LDD), a second LDD, an interface layer (IL), a high-k stack, a gate region, a dummy poly region, a first hard mask (HM) region, a second HM region, and a seal spacer region. The HK stack has a HK stack width and the gate region has a gate region width that is less than or substantially equal to the HK stack width. Because of the increased width of the HK stack, some of the HK stack likely overlaps some of the first LDD or the second LDD. In this manner, a saturation current and a threshold voltage associated with the semiconductor structure are improved. The increased width of the HK stack also protects more of the IL during LDD implanting. | 09-18-2014 |
| 20140264590 | FinFET with Bottom SiGe Layer in Source/Drain - A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer. | 09-18-2014 |
| 20150021688 | MOS Devices with Non-Uniform P-type Impurity Profile - An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration. | 01-22-2015 |
| 20150028418 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - Embodiments of the invention provide a thin film transistor, an array substrate and a manufacturing method thereof, and a display panel. The thin film transistor comprises: an active layer pattern, a source electrode, a drain electrode and a gate electrode. The gate electrode is positioned above the active layer pattern, the source electrode is connected with the active layer pattern, the drain electrode is connected with the active layer pattern, and the source electrode and the drain electrode are disposed in an adjacent layer of the active layer pattern. | 01-29-2015 |
| 20150035057 | SEMICONDUCTOR DEVICE INCLUDING METAL SILICIDE LAYER AND METHOD FOR MANUFACTURING THE SAME - A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon. | 02-05-2015 |
| 20150041895 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region. | 02-12-2015 |
| 20150041896 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE - A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device. | 02-12-2015 |
| 20150061010 | STRUCTURE FOR IMPROVED CONTACT RESISTANCE AND EXTENSION DIFFUSION CONTROL - Semiconductor structures are provided including a raised source region comprising, from bottom to top, a source-side phosphorus doped epitaxial semiconductor material portion and a source-side arsenic doped epitaxial semiconductor material portion and located on one side of a gate structure, and a raised drain region comprising from bottom to top, a drain-side phosphorus doped epitaxial semiconductor material portion and a drain-side arsenic doped epitaxial semiconductor material portion and located on another side of the gate structure. | 03-05-2015 |
| 20150061011 | MOS TRANSISTOR - A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously. | 03-05-2015 |
| 20150061012 | HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES - A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control. | 03-05-2015 |
| 20150137233 | HIGH VOLTAGE DEVICE FABRICATED USING LOW-VOLTAGE PROCESSES - A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. A gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation. | 05-21-2015 |
| 20150145040 | METAL OXIDE SEMICONDUCTOR AND METHOD OF MAKING - A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component. | 05-28-2015 |
| 20150303302 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a channel in a semiconductor composite. The active area includes a first active area layer having a first dopant concentration, a second active area layer having a second dopant concentration over the first active area layer, and a third active area layer having a third dopant concentration, over the second active area. The third dopant concentration is greater than the second dopant concentration, and the second dopant concentration is greater than the first dopant concentration. The channel includes a second channel layer comprising carbon over a first channel layer and a third channel layer over the second channel layer. The active area configuration improves drive current and reduces contact resistance, and the channel configuration increases short channel control, as compared to a semiconductor device without the active area and channel configuration. | 10-22-2015 |
| 20150380550 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a technique for promoting miniaturization of a MISFET. A p-type well region is disposed between LDDs (n-type low-concentration regions) of a MISFET (Qn) to cause both the well region and the low-concentration region to partially overlap each other, whereby an overlap region formed of an n-type semiconductor region having a higher resistance than that of the n-type low-concentration region is provided between the p-type well region and each of the n-type low-concentration regions. In this way, the overlap region can relieve an electric field concentration at the end of the n-type low-concentration region, thereby suppressing the occurrence of hot carriers without elongating an offset length of the LDD, which can promote the miniaturization of the MISFET (Qn), particularly, that operates at high voltage. | 12-31-2015 |
| 20160013264 | ELECTRO-OPTICAL DEVICE, ELECTRONIC APPARATUS, AND DRIVE CIRCUIT | 01-14-2016 |
| 20160056285 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE WITH INCREASED CUTOFF FREQUENCY - A HVMOS transistor structure includes a semiconductor substrate; a gate overlying the semiconductor substrate; a gate dielectric layer between the gate and the semiconductor substrate; a sidewall spacer on each sidewall of the gate; a drain structure in the semiconductor substrate on one side of the gate; an ion well of the first conductivity type in the semiconductor substrate; a source structure in the semiconductor substrate being space apart from the drain structure; and a channel region between the drain structure and the source structure, wherein the channel region substantially consisting of two gate-overlapping regions of the first conductivity type having doping concentrations different from each other. | 02-25-2016 |
| 20160056286 | HIGH GAIN DEVICE - A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions. | 02-25-2016 |
| 20160079417 | Semiconductor Device and Method of Manufacturing the Same - To satisfy both suppression of rise in contact resistance and improvement of breakdown voltage near the end part of a trench part. The trench part GT is provided between a source offset region and a drain offset region at least in plan view in a semiconductor layer, and is provided in a source-drain direction from the source offset region toward the drain offset region in plan view. A gate insulating film GI covers the side surface and the bottom surface of the trench part GT. A gate electrode is provided in the trench part at least in plan view, and contacts the gate insulating film GI. A contact GC contacts the gate electrode GE. The contact GC is disposed, shifted in a first direction perpendicular to the source-drain direction relative to the centerline in the trench part GT extending in the source-drain direction in plan view, and is provided in the trench part GT in plan view. | 03-17-2016 |
| 20160087062 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device includes: a plurality of fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of fin structures, wherein the gate stack structure includes a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of fin structures and beneath the gate stack structure; and source/drain regions on the plurality of fin structures and at both sides of the gate stack structure along the first direction. | 03-24-2016 |
| 20160087063 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided. | 03-24-2016 |
| 20160087098 | Semiconductor Devices Having Gate Structures and Methods of Manufacturing the Same - Semiconductor devices are provided including an active layer, a gate structure, a spacer, and a source/drain layer. The active layer is on the substrate and includes germanium. The active layer includes a first region having a first germanium concentration, and a second region on both sides of the first region. The second region has a top surface getting higher from a first portion of the second region adjacent to the first region toward a second portion of the second region far from the first region, and has a second germanium concentration less than the first germanium concentration. The gate structure is formed on the first region of the active layer. The spacer is formed on the second region of the active layer, and contacts a sidewall of the gate structure. The source/drain layer is adjacent to the second region of the active layer. | 03-24-2016 |
| 20180026093 | MOSFET AND A METHOD FOR MANUFACTURING THE SAME | 01-25-2018 |
| 20180026115 | TRANSISTOR WITH CONTACTED DEEP WELL REGION | 01-25-2018 |
