| Entries |
| Document | Title | Date |
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| 20080203470 | Lateral compensation component - A transistor is provided which includes a lateral compensation component. The lateral compensation component includes a plurality of n (or nā) layer/p (or pā) layer pairs, wherein adjacent ones of said pairs are separated by one of an insulator region and/or an intrinsic silicon region. | 08-28-2008 |
| 20080211012 | Structure and Method for Forming Accumulation-mode Field Effect Transistor with Improved Current Capability - An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions. | 09-04-2008 |
| 20080211013 | SEMICONDUCTOR MEMORY DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions. | 09-04-2008 |
| 20080224204 | PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE - A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain epitaxial layer on the semiconductor substrate, forming first sub-regions of a second type of conductivity by means of a first selective implant step with a first implant dose, forming second sub-regions of the first type of conductivity by means of a second implant step with a second implant dose, forming a surface semiconductor layer wherein body regions of the second type of conductivity are formed being aligned with the first sub-regions, carrying out a thermal diffusion process so that the first sub-regions form a single electrically continuous column region being aligned and in electric contact with the body regions. | 09-18-2008 |
| 20080237701 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT - A semiconductor component includes a semiconductor body having an edge with an edge zone of a first conductivity type. Charge compensation regions of a second conductivity type are embedded into the edge zone, with the charge compensation regions extending from a top side of the semiconductor component vertically into the semiconductor body. For the number N | 10-02-2008 |
| 20080246079 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode. | 10-09-2008 |
| 20080246080 | Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device further includes a shallow trench isolation (STI) region to increase the resistance from the drain region to the source region. The STI region includes a first side vertically aligned with a second side of the gate region. The STI region extends from the first side to a second side in contact with a second side of the drain region. The breakdown voltage of the n-type semiconductor device is directly proportional to a vertical length, or a depth, of the first side and/or the second side of the STI region. The horizontal length, or distance from the first side to the second side, of the STI region does not substantially contribute to the breakdown voltage of the semiconductor device. As a result, a conventional CMOS logic foundry technology may fabricate the STI region of the semiconductor device using a low operating voltage process minimum design rule. | 10-09-2008 |
| 20080258208 | SEMICONDUCTOR COMPONENT INCLUDING COMPENSATION ZONES AND DISCHARGE STRUCTURES FOR THE COMPENSATION ZONES - A semiconductor component including compensation zones and discharge structures for the compensation zones. One embodiment provides a drift zone of a first conduction type, at least one compensation zone of a second conduction type, complementary to the first conduction type, the at least one compensation zone being arranged in the drift zone, at least one discharge structure which is arranged between the at least one compensation zone and a section of the drift zone that surrounds the compensation zone or in the compensation zone and designed to enable a charge carrier exchange between the compensation zone and the drift zone if a potential difference between an electrical potential of the compensation zone and an electrical potential of the section of the drift zone that surrounds the compensation zone is greater than a threshold value predetermined by the construction and/or the positioning of the discharge structure. | 10-23-2008 |
| 20080265311 | VERTICAL TRANSISTOR AND METHOD FOR PREPARING THE SAME - A vertical transistor comprises a substrate having a step structure, two doped regions positioned in the substrate at the two sides of the step structure, and a carrier channel positioned in the substrate between the two doped regions, wherein the step structure includes an inclined edge and the width of the carrier channel at the inclined edge is larger than the width of the doped regions. The step structure comprises two non-rectangular surfaces, such as the trapezoid or triangular surfaces, and a rectangular surface. The non-rectangular surfaces connect to the doped regions, and the rectangular surface is perpendicular to the non-rectangular surface. | 10-30-2008 |
| 20080265312 | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout - This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region. | 10-30-2008 |
| 20080283907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with first and second silicon pillars formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surfaces of the first and second silicon pillars via a gate insulation film, first and second diffusion layers provided on a lower part and an upper part of the first silicon pillar, respectively, a cap insulation film covering an upper part of the second silicon pillar, a gate contact connected to the gate electrode, and a protection insulation film in contact with the upper surfaces of the first and second silicon pillars. The gate contact is connected to an upper region of the gate electrode provided at the periphery of the cap insulation film. An opening is formed on the protection insulation film provided at the side of the first silicon pillar. | 11-20-2008 |
| 20080283908 | LATERAL DMOS DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - A lateral DMOS device having a structure that prevents breakdown of a semiconductor device while enhancing the breakdown voltage property. The lateral DMOS device can include a body diode region having a second conduction type well region formed in a first conduction type semiconductor substrate, the second conduction type well region including a first conduction type body region and a drain region each formed in the second conduction type well region, a first conduction type impurity region formed in the first conduction type body region, a source region formed in the first conduction type body region, and a gate insulating film and a gate electrode formed on the first conduction type semiconductor substrate, wherein the first conduction type body region and the second conduction type well region compose a body diode; and a protective diode region in which the first conduction type impurity region is formed at a prescribed interval, wherein the first conduction type body region and the second conduction type well region compose a protective diode. | 11-20-2008 |
| 20080296668 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such that the contact area contacts the same mesa stripes at two positions between which the opening region is arranged, and the opening region having a region of elongate extension which intersects the mesa stripes in a skewed or perpendicular manner. | 12-04-2008 |
| 20080303081 | Device configuration and method to manufacture trench mosfet with solderable front metal - A vertical semiconductor power device includes a plurality of semiconductor power cells connected to a bottom electric terminal disposed on a bottom surface of a semiconductor substrate and at least a top electrical terminal disposed on a top surface of the substrate and connected to the semiconductor power cells. The top electrical terminal further includes a solderable front metal for soldering to a conductor for providing an electric connection therefrom. In an exemplary embodiment, the conductor soldering to the solderable front metal includes a conductor of a high-heat-conductivity metal plate. In another exemplary embodiment, the conductor soldering to the solderable front metal includes a copper plate. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Au front metal. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Ag front metal. | 12-11-2008 |
| 20080303082 | CHARGE-BALANCE POWER DEVICE COMPRISING COLUMNAR STRUCTURES AND HAVING REDUCED RESISTANCE - A charge-balance power device formed in an epitaxial layer having a first conductivity type and housing at least two columnar structures of a second conductivity type, which extend through the epitaxial layer. A first surface region of the second conductivity type extends along the surface of the epitaxial layer on top of, and in contact with, the columns, and a second surface region of the first conductivity type extends within the first surface region, and also faces the surface of the epitaxial layer. The columns extend at a distance from one another from the first surface region so as to delimit between them an epitaxial portion that defines a current path so as to reduce the on-resistivity of the device. | 12-11-2008 |
| 20080308862 | Mos Transistor and Method of Manufacturing a Mos Transistor - The MOS transistor ( | 12-18-2008 |
| 20080315297 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having a drift layer with a pillar structure including first semiconductor layer portions of the first conduction type and second semiconductor layer portions of the second conduction type formed in pillars alternately and periodically on a semiconductor substrate. A device region includes a plurality of arrayed transistors composed of the first semiconductor layer portions and the second semiconductor layer portions. A terminal region is formed at the periphery of the device region without the transistors formed therein. The drift layer in the terminal region has a carrier lifetime lower than ā
the carrier lifetime in the drift layer in the device region. | 12-25-2008 |
| 20080315298 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced. | 12-25-2008 |
| 20090001455 | ACCUFET WITH SCHOTTKY SOURCE CONTACT - An accumulation mode FET (ACCUFET) having a source contact that makes Schottky contact with the base region thereof. | 01-01-2009 |
| 20090008706 | Power Semiconductor Devices with Shield and Gate Contacts and Methods of Manufacture - A semiconductor power device includes active trenches that define an active area and an edge area that is located outside of the active area. The active trenches include a lower shield poly, an upper gate poly, a first oxide layer and a second oxide layer wherein the first oxide layer separates the lower shield poly from the upper gate poly and the second oxide layer covers the upper gate poly. The lower shield poly, upper gate poly, first oxide layer and second oxide layer conform to the shape of the active trench and extend from the active trench to a surface of the edge area. The edge area includes a first opening that extends through the first oxide layer to the lower shield poly and a second opening that extends through the second oxide layer to the upper gate poly. The first opening is filled with a conductive material that makes electrical contact with the lower shield poly and the second opening is filled with conductive material that makes electrical contact with the upper gate poly. The lower shield poly is electrically insulated from the substrate. The second oxide layer can be directly over the upper gate poly, the upper gate poly can be directly over the first oxide layer, the first oxide layer can be directly over the lower shield poly, and the first opening can be lower than the second opening. The device can further include a perimeter trench with extensions in the longitudinal direction that are staggered with respect to the active trenches so that there can be offset between the extensions of the perimeter trench and the active trenches. | 01-08-2009 |
| 20090026530 | METHODS OF FABRICATING DUAL FIN STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FINS - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 01-29-2009 |
| 20090032865 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT - A semiconductor component having differently structured cell regions, and a method for producing it. For this purpose, the semiconductor component includes a semiconductor body. A first electrode on the top side of the semiconductor body is electrically connected to a first zone near the surface of the semiconductor body. A second electrode is electrically connected to a second zone of the semiconductor body. Furthermore, the semiconductor body has a drift path region, which is arranged in the semiconductor body between the first electrode and the second electrode. A cell region of the semiconductor component is subdivided into a main cell region and an auxiliary cell region, wherein the breakdown voltage of the auxiliary cells is greater than the breakdown voltage of the main cells. | 02-05-2009 |
| 20090039419 | SEMICONDUCTOR COMPONENT WITH DYNAMIC BEHAVIOR - One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches. | 02-12-2009 |
| 20090045457 | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device. | 02-19-2009 |
| 20090050957 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device 1 has a metallic base substrate | 02-26-2009 |
| 20090057754 | Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region - A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween. A body region extends between each pair of adjacent trenches, and source regions extend in each body region adjacent to the trenches. A first interconnect layer contacts the source and body regions. The plurality of trenches extend in an active region of the FET, and the shield electrode and gate electrode extend out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer. The electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region. | 03-05-2009 |
| 20090065855 | MOS device with integrated schottky diode in active region contact trench - A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and at least part of the body into the drain, wherein the active region contact trench is shallower than the body bottom surface, and an active region contact electrode disposed within the active region contact trench. | 03-12-2009 |
| 20090072300 | Semiconductor device having trench gate structure - The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFET | 03-19-2009 |
| 20090072301 | Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact - This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode. | 03-19-2009 |
| 20090078992 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In the present invention, an npn junction is formed by circularly forming a pā type impurity region and n+ type impurity regions on a same single-crystalline substrate as a MOS transistor. Multiple npn junctions are formed apart from each other in concentric circular patterns. With this configuration, steep breakdown characteristics can be obtained, which results in good constant-voltage diode characteristics. Being formed in a manufacturing process of a MOS transistor, the present protection diode contributes to process streamlining and cost reduction. By selecting the number of npn junctions according to breakdown voltage, control of the breakdown voltage can be facilitated. | 03-26-2009 |
| 20090078993 | SEMICONDUCTOR DEVICE WITH REDUCED GATE-OVERLAP CAPACITANCE AND METHOD OF FORMING THE SAME - A semiconductor device includes a vertically extending semiconductor portion above a semiconductor substrate, first and second diffusion regions being disposed near the bottom and top portions of the vertically extending semiconductor portion, respectively. A gate insulating film extends along the side surface of the vertically extending semiconductor portion which is separated by the gate insulating film from a gate electrode. The level of the top portion of the gate electrode is nearly equal to or lower than the level of the bottom portion of the second diffusion regions and the level of the bottom portion of the gate electrode is nearly equal to or higher than the level of the top portion of the first diffusion region. | 03-26-2009 |
| 20090085099 | TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING THREE MASKS - In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device. | 04-02-2009 |
| 20090085100 | SEMICONDUCTOR DEVICE - A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device. | 04-02-2009 |
| 20090085101 | Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance - A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region. | 04-02-2009 |
| 20090090966 | HIGH DENSITY FET WITH INTEGRATED SCHOTTKY - A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween. | 04-09-2009 |
| 20090096018 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view. With respect to a column formed by the body contact regions aligned in a predetermined column direction, the trenches are disposed at both sides in a row direction orthogonal to the column direction in a plan view, extend in the column direction, and form meandering lines each connecting a plurality of curved portions so that a predetermined gap in the row direction is formed respectively between adjacent trenches extending in the column direction and between the trenches and the body contact regions. | 04-16-2009 |
| 20090108337 | Method of and circuit for protecting a transistor formed on a die - A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed. | 04-30-2009 |
| 20090108338 | Trench MOSFET with implanted drift region - A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees. | 04-30-2009 |
| 20090114980 | SEMICONDUCTOR DEVICE HAVING VERTICAL AND HORIZONTAL TYPE GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device having both vertical and horizontal type gates and a method for fabricating the same for obtaining high integration of the semiconductor device and integration with other devices while also maximizing the breakdown voltage and operational speed and preventing damage to the semiconductor device. | 05-07-2009 |
| 20090140326 | SHORT GATE HIGH POWER MOSFET AND METHOD OF MANUFACTURE - A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability. | 06-04-2009 |
| 20090140327 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N | 06-04-2009 |
| 20090159963 | Semiconductor device including a plurality of cells - A semiconductor device includes an insulated gate transistor and a resistor. The insulated gate transistor includes a plurality of first cells for supplying electric current to a load and a second cell for detecting an electric current that flows in the first cells. A gate terminal of the plurality of first cells is coupled with a gate terminal of the second cell and a source terminal of the plurality of first cells is coupled with a source terminal of the second cell on a lower potential side. The resistor has a first terminal coupled with a drain terminal of the second cell and a second terminal coupled with a drain terminal of the first cells on a higher potential side. A gate voltage of the insulated gate transistor is feedback-controlled based on an electric potential of the resistor. | 06-25-2009 |
| 20090166720 | SEMICONDUCTOR DEVICE, METHOD FOR OPERATING A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction. | 07-02-2009 |
| 20090166721 | QUASI-VERTICAL GATED NPN-PNP ESD PROTECTION DEVICE - Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process. | 07-02-2009 |
| 20090166722 | High voltage structures and methods for vertical power devices with improved manufacturability - This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers. | 07-02-2009 |
| 20090166723 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND LOW SHEET RESISTANCE AND METHOD FOR FABRICATING THE SAME - A memory device includes a substrate, a plurality of wordlines arranged over the substrate, a plurality of pillars formed over the substrate between the wordlines, a gate electrode surrounding external walls of the pillars to be connected to the wordlines, and an insulation layer for insulating one sidewall of each wordline from the gate electrode. | 07-02-2009 |
| 20090166724 | Semiconductor Device and Method for Manufacturing the Same - Disclosed is a vertically arranged semiconductor device. The semiconductor device can include a semiconductor substrate comprising a first conductive type buried layer, a first conductive type drift region formed on the first conductive type buried layer, and a second conductive type well formed on the first conductive type drift region. A gate insulating layer and a gate electrode can be formed in regions of the substrate from which the first conductive type drift region and the second conductive type well are selectively removed. A first conductive type source region can be formed at sides of the gate electrode. A n insulating layer can be formed on the semiconductor substrate including the gate electrode and can include a trench formed through the insulating layer and a portion of the second conductive type well. A barrier layer can be formed in the trench and a source contact including tungsten and aluminum can be deposited in the trench. A drain electrode layer can be formed on a bottom surface of the substrate below the first conductive type buried layer. | 07-02-2009 |
| 20090189216 | SEMICONDUCTOR COMPONENT INCLUDING A DRIFT ZONE AND A DRIFT CONTROL ZONE - Semiconductor component including a drift region and a drift control region. One embodiment provides a drift zone and a drift control zone. A drift control zone dielectric is arranged between the first drift zone and the drift control zone and has at least two sections arranged at a distance from one another in a current flow direction of the component. At least one separating structure is arranged between the drift zone and the drift control zone in the region of an interruption, defined by the at least two sections, of the drift control zone dielectric and has at least one PN junction. | 07-30-2009 |
| 20090206395 | Trench mosfet with double epitaxial structure - A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further includes a first epitaxial layer above heavily doped substrate and beyond the trench bottom and a second epitaxial layer above said first epitaxial layer wherein a resistivity N | 08-20-2009 |
| 20090212354 | TRENCH MOSEFT WITH TRENCH GATES UNDERNEATH CONTACT AREAS OF ESD DIODE FOR PREVENTION OF GATE AND SOURCE SHORTATE - A trench DMOS transistor having overvoltage protection and prevention for shortage between gate and source when contact trenches are applied includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. Trench gates extend through the body region and the substrate. An insulating oxide layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer defining the Zener diode region. A plurality of cathode regions of the first conductivity type is formed in undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions. Trench gates underneath the Zener diode act as the buffer layer for prevention of shortage between gate and source. | 08-27-2009 |
| 20090212355 | Metal-Oxide-Semiconductor Transistor Device and Method for Making the Same - A metal-oxide-semiconductor transistor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, an oxide layer formed on the epitaxial layer, a gate structure formed on the oxide layer, and a shallow junction well formed on the two lateral sides of the gate structure including a source region and a heavy doping region. The gate structure includes a conductive layer having a gap on top of the sidewall of the conductive layer and a spacer formed on the gap. | 08-27-2009 |
| 20090212356 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a double-diffused metal oxide semiconductor (DMOS) transistor having a gate electrode and a drain electrode region; and a protection element protecting the gate electrode with respect to overvoltage and coupled to the DMOS transistor on a structure of one semiconductor substrate. The DMOS transistor and the protection element are included in an element integrated structure. In the device, the protection element is formed on a diffusion region, which is separately formed with respect to a diffusion region for the DMOS transistor, in the drain electrode region of the DMOS transistor. | 08-27-2009 |
| 20090242971 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed. | 10-01-2009 |
| 20090267140 | MOSFET STRUCTURE WITH GUARD RING - A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body regions forming metal connections of the MOSFET; a plurality of contact metal plugs connected to respective metal layer regions; a plurality of gate structure filled with polysilicon to be formed on top of the epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; and a guard ring wrapping around the trench gates with contact metal plug underneath the gate metal layer | 10-29-2009 |
| 20090273022 | CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH - A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described. | 11-05-2009 |
| 20090278196 | FinFETs having dielectric punch-through stoppers - A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator. | 11-12-2009 |
| 20090294841 | Formation of a MOSFET Using an Angled Implant - A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n | 12-03-2009 |
| 20090302373 | SEMICONDUCTOR DEVICE - A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion. | 12-10-2009 |
| 20100006927 | Charge Balance Techniques for Power Devices - A vertically-conducting charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state, and a non-active perimeter region surrounding the active area. No current flows along the vertical dimension through the non-active perimeter region when the plurality of cells is biased in the conducting state. Strips of p pillars and strips of n pillars are arranged in an alternating manner. The strips of p pillars have a depth extending along the vertical dimension, a width, and a length. The strips of p and n pillars extend through both the active area and the non-active perimeter region along a length of a die that contains the semiconductor power device. The length of the die extends parallel to the length of the strips of p pillars. Each of the strips of p pillars includes a plurality of discontinuities forming portions of a plurality of strips of n regions. The plurality of strips of n regions extends in the non-active perimeter region perpendicular to the length of the die. | 01-14-2010 |
| 20100025756 | Dual Current Path LDMOSFET with Graded PBL for Ultra High Voltage Smart Power Applications - A dual current path LDMOSFET transistor ( | 02-04-2010 |
| 20100032749 | Field-Effect Device and Manufacturing Method Thereof - Embodiments relate to a field-effect transistor that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region of the first conductivity type, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region. | 02-11-2010 |
| 20100038706 | SEMICONDUCTOR DEVICE - Provided is an ESD protection element, in which: LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to easily satisfy a function required for the ESD protection element, the function of being constantly in an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again. | 02-18-2010 |
| 20100038707 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor substrate; a first main electrode provided on a first main surface of said semiconductor substrate; a second main electrode provided on a second main surface of said semiconductor substrate, wherein a main current flows in a thickness direction of said semiconductor substrate; a trench that extends from the first main surface of said semiconductor substrate towards the second main surface; a gate insulating film covering an inner surface of said trench; and a gate electrode buried in said trench and surrounded by said gate insulating film. | 02-18-2010 |
| 20100038708 | Method and Structure for Forming a Shielded Gate Field Effect Transistor - A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type. | 02-18-2010 |
| 20100044783 | INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION - A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate. | 02-25-2010 |
| 20100052044 | SEMICONDUCTOR DEVICE WITH A TRENCH GATE STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF - A semiconductor device with a trench gate structure includes a semiconductor body with switching electrodes. At least gate electrode controls the off state and the on state between the switching electrodes. The at least one gate electrode in the trench gate structure controls at least one vertical switching channel through at least one body zone. The trench gate structure includes at least one trench with side walls, wherein the at least one gate electrode, which is insulated against the side walls in the region of the at least one body zone alternately by at least one gate oxide section and at least one trench oxide section and forms a switching channel with a gate oxide section in the at least one region, is located in the at least one trench. | 03-04-2010 |
| 20100052045 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed herein is a semiconductor device including: a main body transistor region; and an electrostatic discharge protection element region, wherein the main body transistor region includes, a drain region; a drift region; body regions; a gate insulating film; gate electrodes; source regions; channel regions; and potential extraction regions, and the electrostatic discharge protection element region includes, the body regions; the gate insulating film; the gate electrodes; source regions and drain regions; and potential extraction regions, and a gate length in the electrostatic discharge protection element region is equal to or less than twice a channel length in the main body transistor region. | 03-04-2010 |
| 20100072540 | ELECTRONIC CIRCUIT CONTROL ELEMENT WITH TAP ELEMENT - A technique for controlling a power supply with power supply control element with a tap element. An example power supply control element includes a power transistor that has first and second main terminals, a control terminal and a tap terminal. A control circuit is coupled to the control terminal. The tap terminal and the second main terminal of the power transistor are to control switching of the power transistor. The tap terminal is coupled to provide a signal to the control circuit substantially proportional to a voltage between the first and second main terminals when the voltage is less than a pinch off voltage. The tap terminal is coupled to provide a substantially constant voltage that is less than the voltage between the first and second main terminals to the control circuit when the voltage between the first and second main terminals is greater than the pinch-off voltage. | 03-25-2010 |
| 20100078707 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region. | 04-01-2010 |
| 20100078708 | MOS TRANSISTOR HAVING AN INCREASED GATE-DRAIN CAPACITANCE - A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which s dieletrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode. | 04-01-2010 |
| 20100078709 | SEMICONDUCTOR DEVICE - In a conventional semiconductor device, protection of a to-be-protected element from a surge voltage is difficult because the to-be-protected element is turned on before a protection element due to variations in manufacturing conditions. In a semiconductor device of the present invention, a protection element and a MOS transistor have part of their structures formed under common conditions. N type diffusion layers of the protection element and the MOS transistor are formed in the same process, while the N type diffusion layer of the protection element has a larger diffusion width than the N type diffusion layer of the MOS transistor. With this structure, when a surge voltage is applied to an output terminal, the protection element is turned on before the MOS transistor, and thereby the MOS transistor is protected from an avalanche current. | 04-01-2010 |
| 20100090269 | TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN - A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength. | 04-15-2010 |
| 20100090270 | TRENCH MOSFET WITH SHORT CHANNEL FORMED BY PN DOUBLE EPITAXIAL LAYERS - A power MOS device includes double epitaxial (P/N) structure is disclosed for reduction of channel length and better avalanche capability. In some embodiments, the power MOS device further includes an arsenic Ion implantation area underneath each rounded trench bottom to further enhance breakdown voltage and further reduce Rds, and the concentration of said arsenic doped area is higher than that of N-type epitaxial layer. As the gate contact trench could be easily etched over to penetrate the gate oxide, which will lead to a shortage of tungsten plug filled in gate contact trench to epitaixial layer, a terrace poly gate is designed in a preferred embodiment of present invention. By using this method, the gate contact trench is lifted to avoid the shortage problem. | 04-15-2010 |
| 20100090271 | Power Switching Semiconductor Devices Including Rectifying Junction-Shunts - A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse biase the p-n junction between the drift region and the body region. | 04-15-2010 |
| 20100102379 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - A LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, two body regions of the first conductivity type, a body connection region of the first conductivity type, two source regions of the second conductivity type, a drain region of the second conductivity type, a channel region, and a gate electrode. The body regions are disposed in the deep well region configured in the substrate. The body connection region is disposed in the deep well region to connect the body regions. Each of the source regions is disposed in the body region. The drain region is disposed in the deep well between the source regions. The channel region is disposed in a portion of the body region. The gate electrode is disposed on the deep well region between the source regions and the drain region and covers the channel region. | 04-29-2010 |
| 20100109076 | STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A first doped region of the first conductivity type and a second doped region of the second conductivity type are located in the second well region. A first transistor includes the first doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event. | 05-06-2010 |
| 20100109077 | High-voltage vertical transistor with a multi-gradient drain doping profile - A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 05-06-2010 |
| 20100123185 | MSD integrated circuits with trench contact structures for device shrinkage and performance improvement - A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for GS clamp diodes and avalanche protection for GD clamp diodes. | 05-20-2010 |
| 20100140687 | High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates - An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region. | 06-10-2010 |
| 20100148244 | SEMICONDUCTOR ELEMENT AND ELECTRICAL APPARATUS - In a semiconductor element ( | 06-17-2010 |
| 20100148245 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped re-ion lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 mĪ©*nC. | 06-17-2010 |
| 20100155828 | FIELD-EFFECT SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first conductivity type formed in the body region. The first region extends from the first surface of the semiconductor layer and provides a current electrode region of the semiconductor device. The second region surrounds the first region. The doping concentration of the first conductivity type in the second region is greater than a doping concentration of the first conductivity type in the body region. | 06-24-2010 |
| 20100155829 | DEVICE FOR PROTECTING SEMICONDUCTOR DEVICE FROM ELECTROSTATIC DISCHARGE AND METHOD FOR FABRICATING THE SAME - A device for protecting a semiconductor device from electrostatic discharge may include a high voltage first conductivity type well formed in a semiconductor substrate. A first stack region may have a first conductivity type drift region, and a first conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A second stack region may have a second conductivity type drift region, and a second conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A device isolating film formed between the first stack region and the second stack region for isolating the first stack region from the second stack region. | 06-24-2010 |
| 20100155830 | ELECTRONIC SWITCHING DEVICE - An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate electrode of the switching IGFET. The protector IGFET has its gate electrode connected to the source electrode of the switching IGFET. The protector IGFET turns on in response to an application of a verse voltage to the switching IGFET thereby protecting the same from a reverse current flow. | 06-24-2010 |
| 20100163972 | MULTI-DRAIN SEMICONDUCTOR POWER DEVICE AND EDGE-TERMINATION STRUCTURE THEREOF - An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area. | 07-01-2010 |
| 20100163973 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a P-type substrate | 07-01-2010 |
| 20100176443 | Semiconductor Device - Provided is a semiconductor device in which on-resistance is largely reduced. In a region ( | 07-15-2010 |
| 20100200910 | Semiconductor Devices with Stable and Controlled Avalanche Characteristics and Methods of Fabricating the Same - Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art. | 08-12-2010 |
| 20100200911 | ELECTROSTATIC DISCHARGE FAILURE PROTECTIVE ELEMENT, ELECTROSTATIC DISCHARGE FAILURE PROTECTIVE CIRCUIT, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An electrostatic discharge failure protective element ( | 08-12-2010 |
| 20100207197 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented. | 08-19-2010 |
| 20100207198 | METHOD FOR FABRICATING A POWER SEMICONDUCTOR DEVICE HAVING A VOLTAGE SUSTAINING LAYER WITH A TERRACED TRENCH FACILITATING FORMATION OF FLOATING ISLANDS - A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween. | 08-19-2010 |
| 20100219461 | Structure With PN Clamp Regions Under Trenches - A structure that includes a rectifier further comprises a semiconductor region of a first conductivity type, and trenches that extend into the semiconductor region. A dielectric layer lines lower sidewalls of each trench but is discontinuous along a bottom of each trench. A silicon region of a second conductivity type extends along the bottom of each trench and forms a PN junction with the semiconductor region. A shield electrode in a bottom portion of each trench is in direct contact with the silicon region. A gate electrode extends over the shield electrode. An interconnect layer extends over the semiconductor region and is in electrical contact with the shield electrode. The interconnect layer further contacts mesa surfaces of the semiconductor region between adjacent trenches to form Schottky contacts therebetween. | 09-02-2010 |
| 20100224931 | TRENCH MOSEFT WITH TRENCH GATES UNDERNEATH CONTACT AREAS OF ESD DIODE FOR PREVENTION OF GATE AND SOURCE SHORTAGE - A trench DMOS transistor employing trench contacts has overvoltage protection for prevention of shortage between gate and source, comprising a plurality of first-type function trenched gates, at least one second-type function trenched gate and at least two third-type function trenched gates extending through body regions and into an epitaxial layer. The first-type function trenched gates are located in active area surrounded by a source region encompassed in the body region in the epitaxial layer for current conduction. The second-type function trenched gates are disposed underneath a gate metal with a gate trenched contacts filled with metal plug for gate metal connection. The third type function trenched gates are disposed directly and symmetrically underneath ESD trenched contact areas of anode and cathode in an ESD protection diode, serving as a buffer layer for prevention of gate-body shortage. | 09-09-2010 |
| 20100244123 | FIELD-EFFECT TRANSISTOR WITH SELF-LIMITED CURRENT - A field-effect transistor is integrated in a chip of semiconductor material of a first type of conductivity, which has a first main surface and a second main surface, opposite to each other. The transistor includes a plurality of body regions of a second type of conductivity, each one extending from the second main surface in the chip. A plurality of drain columns of the second type of conductivity are provided, each one extending from a body region towards the first main surface, at a pre-defined distance from the first main surface. A plurality of drain columns are defined in the chip, each one extending longitudinally between a pair of adjacent drain columns. The transistor includes a plurality of source regions of the first type of conductivity, each one of them extending from the second main surface in a body region; a plurality of channel areas are defined, each one in a body region between a source region of the body region and each drain channel adjacent to the body region. There are then provided a gate terminal extending over the cannel areas (with the gate terminal that is insulated from the second main surface), a source terminal contacting the source regions on the second main surface, and a drain terminal contacting the chip on the first main surface. In the transistor according to an embodiment of the invention, each drain channel includes a first residual portion having a first transversal width and a second prevalent portion having a second transversal width higher than the first transversal width. | 09-30-2010 |
| 20100258853 | TRENCH SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A trench semiconductor device and a method of making the same are provided. The trench semiconductor device includes a trench MOS device and a trench ESD protection device. The trench ESD protection device is electrically connected between the gate electrode and source electrode of the trench MOS device so as to provide ESD protection. The fabrication of the ESD protection device is integrated into the process of the trench MOS device, and therefore no extra mask is required to define the doped regions of the trench ESD protection device. Consequently, the trench semiconductor device is advantageous for its simplified manufacturing process and low cost. | 10-14-2010 |
| 20100258854 | SEMICONDUCTOR DEVICE - A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion. | 10-14-2010 |
| 20100258855 | Field Effect Transistor with Self-aligned Source and Heavy Body Regions and Method of Manufacturing Same - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 10-14-2010 |
| 20100258856 | MOSFET STRUCTURE WITH GUARD RING - A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; and a guard ring wrapping around the trench gates with contact metal plug underneath the gate metal layer. | 10-14-2010 |
| 20100289073 | Trench MOSFETS with ESD Zener diode - A semiconductor power device with Zener diode for providing an electrostatic discharge (ESD) protection and a thick insulation layer to insulate the Zener diode from a doped body region. The semiconductor power device further includes a Nitride layer underneath the thick oxide layer working as a stopper layer for protecting the thin oxide layer and the body region underneath whereby the over-etch damage and punch-through issues in process steps are eliminated. | 11-18-2010 |
| 20100314681 | Power semiconductor devices integrated with clamp diodes sharing same gate metal pad - A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon. | 12-16-2010 |
| 20100314682 | Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions - This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches. | 12-16-2010 |
| 20100327342 | TRANSIENT OVER-VOLTAGE CLAMP - In various embodiments, the invention relates to semiconductor structures, such as planar MOS structures, suitable as voltage clamp devices. Additional doped regions formed in the structures may improve over-voltage protection characteristics. | 12-30-2010 |
| 20100327343 | BOND PAD WITH INTEGRATED TRANSIENT OVER-VOLTAGE PROTECTION - In various embodiments, the invention relates to bond pad structures including planar transistor structures operable as over-voltage clamps. | 12-30-2010 |
| 20110012192 | Vertical Channel Transistor Structure and Manufacturing Method Thereof - A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate. | 01-20-2011 |
| 20110018054 | Method for Preventing Gate Oxide Damage of a Trench MOSFET during Wafer Processing while Adding an ESD Protection Module Atop - A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: | 01-27-2011 |
| 20110049614 | SUPER JUNCTION TRENCH POWER MOSFET DEVICES - In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant. | 03-03-2011 |
| 20110057254 | METAL-OXIDE-SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF - A metal-oxide-semiconductor chip having a semiconductor substrate, an epitaxial layer, at least a MOS cell, and a metal pattern layer is provided. The epitaxial layer is located on the semiconductor substrate and has an active region, a termination region, and a scribe line preserving region defined on an upper surface thereof. An etched sidewall of the epitaxial layer is located in the scribe line preserving region. The boundary portion of the upper surface of the semiconductor substrate is thus exposed. The MOS cell is located in the active region. The metal pattern layer is located on the epitaxial layer and has a gate pad coupled to the gate of the MOS cell, a source pad coupled to the source of the MOS cell, and a drain pattern, which is partly located on the upper surface of the semiconductor substrate. | 03-10-2011 |
| 20110068386 | DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS - A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer. | 03-24-2011 |
| 20110073938 | FIELD-EFFECT SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor substrate of an IGFET has drain regions, a p-type first body region, a p | 03-31-2011 |
| 20110089481 | MOS TRANSISTOR WITH ELEVATED GATE DRAIN CAPACITY - A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode. | 04-21-2011 |
| 20110095358 | DOUBLE-SIDED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME - A semiconductor structure including a substrate of semiconductor material of a first type of conductivity; a first semiconductor layer set in direct electrical contact with the substrate on a first side of the substrate; a second semiconductor layer set in direct electrical contact with the substrate on a second side of the substrate; a first active electronic device formed in the first semiconductor layer; and a second active electronic device formed in the second semiconductor layer. | 04-28-2011 |
| 20110101444 | ELECTROSTATIC PROTECTION DEVICE - An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device. | 05-05-2011 |
| 20110101445 | SUBSTRATE STRUCTURES INCLUDING BURIED WIRING, SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE STRUCTURES, AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure. The vertical transistor includes a gate electrode and a semiconductor pillar, and the buried wiring is one of source electrode or a drain electrode of the vertical transistor | 05-05-2011 |
| 20110133269 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes, below a high-voltage wiring, a p | 06-09-2011 |
| 20110140194 | Enhancing Schottky breakdown voltage (BV) without affecting an integrated Mosfet-Schottky device layout - This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region. | 06-16-2011 |
| 20110163372 | SEMICONDUCTOR DEVICE - A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device. | 07-07-2011 |
| 20110227145 | DUAL VERTICAL CHANNEL TRANSISTOR AND FABRICATION METHOD THEREOF - A dual vertical channel transistor includes a tuning fork-shaped substrate body; a buried bit line embedded at a bottom of a recess between two prong portions of the tuning fork-shaped substrate body; an out-diffused drain region adjacent to the buried bit line in the tuning fork-shaped substrate body; a source region situated at a top portion of each of the two prong portions of the tuning fork-shaped substrate body; an epitaxial portion connecting the two prong portions of the tuning fork-shaped substrate body between the out-diffused drain region and the source region; a front gate situated on a first side surface of the tuning fork-shaped substrate body; and a back gate situated on a second side surface opposite to the first side surface of the tuning fork-shaped substrate body. | 09-22-2011 |
| 20110227146 | POWER MOS TRANSISTOR DEVICE - A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces, is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer. | 09-22-2011 |
| 20110266614 | LDMOS WITH ENHANCED SAFE OPERATING AREA (SOA) AND METHOD THEREFOR - A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed. | 11-03-2011 |
| 20110272758 | Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit - A semiconductor device comprises an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which comprises the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET. This abstract is provided to allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 11-10-2011 |
| 20110291181 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device including a cell region and a terminal region includes a first semiconductor region of a first conductivity type, semiconductor pillars of the first and a second conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor pillars of the first and second conductivity type are and arranged alternately on the first semiconductor region. The second semiconductor region is provided on the semiconductor pillar of the second conductivity type. The third semiconductor region is provided on the second semiconductor region. A semiconductor pillar other than a semiconductor pillar most proximal to the terminal region is provided in a stripe configuration. The semiconductor pillar most proximal to the terminal region includes regions having a high and a low impurity concentration. The regions are provided alternately. | 12-01-2011 |
| 20110316071 | POWER SEMICONDUCTOR DEVICE - Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate. | 12-29-2011 |
| 20120007169 | SEMICONDUCTOR DEVICE AND ITS PRODUCTION METHOD - The present invention provides a semiconductor device including:a semiconductor substrate of a first conductive type; a first well region of the first conductive type formed in the semiconductor substrate; an epitaxial region of a second conductive type formed in the semiconductor substrate and arranged in a region adjacent to the first well region; a buried region of the second conductive type that is formed in a region at a lower part of the epitaxial region and that has an impurity concentration higher than that of the epitaxial region; a trench formed at boundaries between the first well region and the epitaxial region, and between the first well region and the buried region; a first semiconductor element that is formed on the first well; and a second semiconductor element that is formed on the epitaxial region. | 01-12-2012 |
| 20120018798 | Method for Protecting a Semiconductor Device Against Degradation, a Semiconductor Device Protected Against Hot Charge Carriers and a Manufacturing Method Therefor - A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided. | 01-26-2012 |
| 20120032254 | ESD PROTECTION DEVICE AND METHOD FOR FABRICATING THE SAME - An electrostatic discharge (ESD) protection device includes a substrate; a source region of a first conductivity type in the substrate; a drain region of the first conductivity type in the substrate; a gate electrode overlying the substrate between the source region and the drain region; and a core pocket doping region of the second conductivity type within the drain region. The core pocket doping region does not overlap with an edge of the drain region. | 02-09-2012 |
| 20120074488 | VERTICAL TRANSISTOR WITH HARDENING IMPLATATION - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 03-29-2012 |
| 20120091521 | MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF - Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion. For other embodiments, thicknesses of respective control gates of the memory cells and/or thicknesses of the dielectrics between successively adjacent control gates may increase as the distances of the respective control gates/dielectrics from the opposing end of the substantially vertical portion increase. | 04-19-2012 |
| 20120146129 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device capable of ensuring a withstand voltage of a transistor and reducing a forward voltage of a Schottky barrier diode in a package with the transistor and the Schottky barrier diode formed on chip, and a semiconductor package formed by a resin package covering the semiconductor device are provided. The semiconductor device | 06-14-2012 |
| 20120161224 | Semiconductor Device Including Diode - A semiconductor device includes a cathode and an anode. The anode includes a first p-type semiconductor anode region and a second p-type semiconductor anode region. The first p-type semiconductor anode region is electrically connected to an anode contact area. The second p-type semiconductor anode region is electrically coupled to the anode contact area via a switch configured to provide an electrical connection or an electrical disconnection between the second p-type anode region and the anode contact area. | 06-28-2012 |
| 20120161225 | INTEGRATED MOSFET DEVICES WITH SCHOTTKY DIODES AND ASSOCIATED METHODS OF MANUFACTURING - The present technology discloses a semiconductor die integrating a MOSFET device and a Schottky diode. The semiconductor die comprises a MOSFET area comprising the active region of MOSFET, a Schottky diode area comprising the active region of Schottky diode, and a termination area comprising termination structures. Wherein the Schottky diode area is placed between the MOSFET area and the termination area such that the Schottky diode area surrounds the MOSFET area. | 06-28-2012 |
| 20120187472 | TRENCH POLY ESD FORMATION FOR TRENCH MOS AND SGT - A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a PāNāP or NāPāN structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench. | 07-26-2012 |
| 20120193701 | POWER SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device. | 08-02-2012 |
| 20120228695 | LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a field plate over the n | 09-13-2012 |
| 20120241847 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion. | 09-27-2012 |
| 20120256250 | Power Transistor Device Vertical Integration - A semiconductor component includes a sequence of layers, the sequence of layers including a first insulator layer, a first semiconductor layer disposed on the first insulator layer, a second insulator layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the second insulator layer. The semiconductor component also includes a plurality of devices at least partly formed in the first semiconductor layer. A first one of the plurality of devices is a power transistor formed in a first region of the first semiconductor layer and a first region of the second semiconductor layer. The first region of the first and second semiconductor layers are in electrical contact with one another through a first opening in the second insulator layer. | 10-11-2012 |
| 20120256251 | SEMICONDUCTOR DEVICE - An ESD protection element is disclosed in which LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to maintain an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again. | 10-11-2012 |
| 20120267704 | TRANSISTOR ARRANGEMENT WITH A MOSFET - A semiconductor arrangement includes a MOSFET having a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a source electrode contacting the source region and the body region. The semiconductor arrangement further includes a normally-off JFET having a channel region of the first conductivity type that is coupled between the source electrode and the drift region and extends adjacent the body region so that a p-n junction is formed between the body region and the channel region. | 10-25-2012 |
| 20120267705 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A method of making a semiconductor device having an ESD protection element which can achieve compatibility between high drain-to-backgate withstand voltage and ESD protection of DMOSFET gates. | 10-25-2012 |
| 20120280307 | INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET - A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa. | 11-08-2012 |
| 20120319189 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE - The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type. | 12-20-2012 |
| 20130020632 | LATERAL TRANSISTOR WITH CAPACITIVELY DEPLETED DRIFT REGION - A lateral transistor includes a gate formed over a gate oxide and a field plate formed over a thick gate oxide. The field plate is electrically connected to a source. The field plate is configured to capacitively deplete a drift region when the lateral transistor is in the OFF state. | 01-24-2013 |
| 20130020633 | SEMICONDUCTOR DEVICE - A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device. | 01-24-2013 |
| 20130043524 | SEMICONDUCTOR DEVICE - Each insulating gate portion forms a channel in part of a first well region located between a drift region and source region. A first main electrode forms junctions with part of the drift region exposed in the major surface of the drift region to constitute unipolar diodes and is connected to the first well regions and the source regions. The plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface. Between each pair of adjacent insulating gate portions, junction portions in which the first main electrode forms junctions with the drift region and the first well regions are arranged along the direction that the insulating gate portions extend. The channels are formed at least in the normal direction of the major surface. | 02-21-2013 |
| 20130075808 | Trench MOSFET with Integrated Schottky Barrier Diode - A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate. | 03-28-2013 |
| 20130075809 | SEMICONDUCTOR POWER DEVICE WITH EMBEDDED DIODES AND RESISTORS USING REDUCED MASK PROCESSES - A trench semiconductor power device integrated with a Gate-Source and a Gate-Drain clamp diodes without using source mask is disclosed, wherein a plurality source regions of a first conductivity type of the trench semiconductor device and multiple doped regions of the first conductivity type of the clamp diodes are formed simultaneously through contact open areas defined by a contact mask. | 03-28-2013 |
| 20130075810 | SEMICONDUCTOR POWER DEVICES INTEGRATED WITH A TRENCHED CLAMP DIODE - A semiconductor power device having shielded gate structure integrated with a trenched clamp diode formed in a semiconductor silicon layer, wherein the shielded gate structure comprises a shielded electrode formed by a first poly-silicon layer and a gate electrode formed by a second poly-silicon layer. The trenched clamp diode is formed by the first poly-silicon layer. A shielded gate mask used to define the shielded gate is also used to define the trenched clamp diode. Therefore, one poly-silicon layer and a mask for the trenched clamp diode are saved. | 03-28-2013 |
| 20130113036 | Transistor Assembly as an ESD Protection Measure | 05-09-2013 |
| 20130140626 | Field-Effect Device and Manufacturing Method Thereof - Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region. | 06-06-2013 |
| 20130175605 | FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials. | 07-11-2013 |
| 20130187218 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well. | 07-25-2013 |
| 20130187219 | High-Voltage Vertical Transistor With a Varied Width Silicon Pillar - In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. | 07-25-2013 |
| 20130207179 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well. | 08-15-2013 |
| 20130207180 | SYMMETRIC LDMOS TRANSISTOR AND METHOD OF PRODUCTION - The symmetric LDMOS transistor comprises a semiconductor substrate ( | 08-15-2013 |
| 20130234237 | SEMICONDUCTOR POWER DEVICE INTEGRATED WITH CLAMP DIODES HAVING DOPANT OUT-DIFFUSION SUPPRESSION LAYERS - A semiconductor power device integrated with clamp diodes is disclosed by offering dopant out-diffusion suppression layers to enhance the ESD protection between gate and source, and avalanche capability between drain and source. | 09-12-2013 |
| 20130234238 | SEMICONDUCTOR POWER DEVICE INTEGRATED WITH ESD PROTECTION DIODES - A semiconductor power device integrated with ESD protection diode is disclosed by offering a dopant out-diffusion suppression layers prior to source dopant activation or diffusion to enhance ESD protection capability between gate and source. | 09-12-2013 |
| 20130240980 | Schottky diode integrated into LDMOS - In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by blocking the formation of one or more n+ source regions and providing a metalized region adjacent to an underlying n-epitaxial region. | 09-19-2013 |
| 20130240981 | TRANSISTOR ARRAY WITH A MOSFET AND MANUFACTURING METHOD - Disclosed are a semiconductor device and a method for producing a semiconductor device. A MOSFET may have a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type disposed between the source region and the drift region, and a gate electrode disposed adjacent to said body region. The gate electrode may be isolated from the body region by a dielectric, and have a source electrode contacting the source region and the body region. A self-locking JFET, associated with the MOSFET, may have a channel region of the first conductivity type, the channel region connected between the source electrode and the drift region, and coupled to and adjacent the body region. | 09-19-2013 |
| 20130256783 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n | 10-03-2013 |
| 20130285136 | Schottky diode with enhanced breakdown voltage - An apparatus of and method for making enhanced Schottky diodes having p-body regions operable to pinch a current flow path in a high-voltage n-well region and field plate structures operable to distribute an electric potential of the Schottky diode allow for a device with enhanced breakdown voltage properties. N-well regions implanted into the substrate over a p-type epitaxial layer may act as an anode of the Schottky diode and n-type well regions implanted in the high-voltage n-well regions may act as cathodes of the Schottky diode. The Schottky diode may also be used as a low-side mosfet structure device. | 10-31-2013 |
| 20130285137 | PROGRAMMABLE SCR FOR LDMOS ESD PROTECTION - A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type ( | 10-31-2013 |
| 20130307055 | ELECTRONIC DEVICE COMPRISING RF-LDMOS TRANSISTOR HAVING IMPROVED RUGGEDNESS - The invention relates to an electronic device comprising an RF-LDMOS transistor ( | 11-21-2013 |
| 20130341705 | SCHOTTKY DIODE INTEGRATED INTO LDMOS - In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes. | 12-26-2013 |
| 20140001539 | INSULATED GATE SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20140042522 | RF LDMOS DEVICE AND FABRICATION METHOD THEREOF - A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate, a p-type epitaxial layer, a p-type well, a lightly doped n-type drain region, a gate oxide layer, a polysilicon gate, a dielectric layer and a Faraday shield. The Faraday shield includes: a horizontal portion covering a portion of the polysilicon gate and isolated from the polysilicon gate by the dielectric layer; a step-like portion with at least two steps covering a portion of the lightly doped n-type drain region and isolated from the lightly doped n-type drain region by the dielectric layer; and a vertical portion connecting the horizontal portion with the step-like portion and isolated from the polysilicon gate and the lightly doped n-type drain region by the dielectric layer. A method of fabricating such an RF LDMOS device is also disclosed. | 02-13-2014 |
| 20140042523 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An anode region | 02-13-2014 |
| 20140061774 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device capable of ensuring a withstand voltage of a transistor and reducing a forward voltage of a Schottky barrier diode in a package with the transistor and the Schottky barrier diode formed on chip, and a semiconductor package formed by a resin package covering the semiconductor device are provided. The semiconductor device | 03-06-2014 |
| 20140077287 | BREAKDOWN VOLTAGE BLOCKING DEVICE - In one embodiment, a breakdown voltage blocking device can include an epitaxial region located above a substrate and a plurality of source trenches formed in the epitaxial region. Each source trench can include a dielectric layer surrounding a conductive region. The breakdown voltage blocking device can also include a contact region located in an upper surface of the epitaxial region along with a gate trench formed in the epitaxial region. The gate trench can include a dielectric layer that lines the sidewalls and bottom of the gate trench and a conductive region located between the dielectric layer. The breakdown voltage blocking device can include source metal located above the plurality of source trenches and the contact region. The breakdown voltage blocking device can include gate metal located above the gate trench. | 03-20-2014 |
| 20140084360 | INTEGRATED VERTICAL TRENCH MOS TRANSISTOR - A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip. | 03-27-2014 |
| 20140103420 | ADVANCED FARADAY SHIELD FOR A SEMICONDUCTOR DEVICE - One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate. | 04-17-2014 |
| 20140138762 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having high ESD tolerance. A first via ( | 05-22-2014 |
| 20140175536 | HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD FOR MAKING SUCH DEVICES - Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T | 06-26-2014 |
| 20140183620 | SEMICONDUCTOR DEVICE - A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure. | 07-03-2014 |
| 20140197475 | POWER MOSFET DEVICE WITH A GATE CONDUCTOR SURROUNDING SOURCE AND DRAIN PILLARS - A power MOSFET device includes at least one MOSFET unit disposed over a substrate, wherein the MOSFET unit includes a plurality of cells and a boundary surrounding the cells. In one embodiment of the present invention, the cell is configured to provide a unit current, and comprises at least one source pillar and at least one drain pillar, a gate conductor surrounding the source pillar and the drain pillar, and an insulating structure electrically separating the gate conductor from the source pillar and the drain pillar, wherein the gate conductor extends from the cell to the boundary. | 07-17-2014 |
| 20140203349 | METHOD OF PRODUCING A HIGH-VOLTAGE-RESISTANT SEMICONDUCTOR COMPONENT HAVING VERTICALLY CONDUCTIVE SEMICONDUCTOR BODY AREAS AND A TRENCH STRUCTURE - A high-voltage-resistant semiconductor component ( | 07-24-2014 |
| 20140217495 | Integrated Circuit with Power and Sense Transistors - An integrated circuit may include a semiconductor portion with a power transistor including first gate trenches that cross a first region and a sense transistor including second gate trenches that cross a second region. Each gate trench extends in a longitudinal direction and comprises a gate electrode and a field electrode. The first and second regions are arranged along the longitudinal direction. A first termination trench intersects at least the second gate trenches in a third region between the first and second regions. The first termination trench includes a first conductive structure that is electrically connected to the field electrodes in the second gate trenches. The characteristics of the sense transistor formed in the second region reliably and precisely replicate the characteristics of the power transistor. | 08-07-2014 |
| 20140231901 | Monolithic MOSFET and Schottky Diode for Mobile Phone Boost Converter - A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power metal oxide semiconductor field effect transistor (MOSFET) and Schottky diode. The semiconductor device has the lateral diffused MOSFET formed on a surface of the semiconductor device. The MOSFET is formed with a plurality conduction fingers. The Schottky diode is also formed on the surface of the semiconductor device and integrated between the plurality of conduction fingers of the MOSFET. The drain of the MOSFET is connected to the anode of the diode on the surface of the monolithic semiconductor device. | 08-21-2014 |
| 20140239381 | INSULATED GATE FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - An insulated gate field effect transistor configured to reduce the occurrence of a short-circuit fault, and a method of manufacturing the insulated gate field effect transistor are provided. A FET includes a semiconductor substrate, a gate insulator, a gate electrode, and a conductive member. The semiconductor substrate has an insulation groove that splits a channel region into a first channel region on a drain region side and a second channel region on a source region side. The conductive member is supported by a drain-side end face and a source-side end face of the insulation groove. When the temperature of the conductive member is equal to or higher than a predetermined temperature, the conductive member is cut. | 08-28-2014 |
| 20140239382 | HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD - Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 08-28-2014 |
| 20140264556 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate. | 09-18-2014 |
| 20140284700 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor layer having an opening formed therein, a first insulating layer disposed on a bottom surface of the opening and on a sidewall of the opening, a second insulating layer disposed on the sidewall of the opening above the first insulating layer, the second insulating layer being thinner than the first insulating layer, a field plate electrode disposed on the first insulating layer and the second insulating layer and having a recess extending from an upper surface of the field plate electrode towards the bottom surface of the opening, and a first layer disposed in the recess and including a material that is different from a material of the field plate electrode. | 09-25-2014 |
| 20140284701 | POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE - A MOSFET includes an active region formed on an SOI substrate. A buried well is formed in the active region. A drain region having the first conductivity type is formed in the active region and spaced laterally from a source region and the buried well. A body region is formed in the active region between the source and drain regions on the buried well, and a drift region is formed in the active region between the drain and body regions on at least a portion of the buried well. A shielding structure is formed proximate the upper surface of the active region, overlapping a gate. During conduction, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes the drift region. The MOSFET is configured to sustain a linear mode of operation of an inversion channel formed under the gate. | 09-25-2014 |
| 20140284702 | FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials. | 09-25-2014 |
| 20140319598 | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device. | 10-30-2014 |
| 20140332877 | Semiconductor Device - A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element. The first transistor element includes first transistors, gate electrodes of which are disposed in first trenches in a first main surface of a semiconductor substrate. The second transistor element includes second transistors, gate electrodes of which are disposed in second trenches in the first main surface, and a second gate conductive line in contact with the gate electrodes in the second trenches. The control element is configured to control a potential applied to the second gate conductive line. | 11-13-2014 |
| 20140332878 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - In a non-insulated DC-DC converter having a circuit in which a power MOSā¢FET high-side switch and a power MOSā¢FET low-side switch are connected in series, the power MOSā¢FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOSā¢FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOSā¢FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them. | 11-13-2014 |
| 20150008510 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer. | 01-08-2015 |
| 20150021680 | FIELD EFFECT TRANSISTOR INCORPORATING A SCHOTTKY DIODE - A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region. | 01-22-2015 |
| 20150035047 | Dual Trench Rectifier and Method for Forming the Same - A structure of dual trench rectifier comprises of the following elements. A plurality of trenches are formed parallel in an nā epitaxial layer on an n+ semiconductor substrate and spaced with each other by a mesa. A plurality of recesses are formed on the mesas. Each the trench has a trench oxide layer formed on the sidewalls and bottom thereof, and a first poly silicon layer is filled therein to form MOS structures. Each the recess has a recess oxide layer formed on the sidewalls and bottom thereof, and a second poly silicon layer is filled therein to form MOS structures. A plurality of p type bodies are formed at two sides of the MOS structures in recesses. A top metal is formed above the semiconductor substrate for serving as an anode. A bottom metal is formed beneath the semiconductor substrate for serving as a cathode. | 02-05-2015 |
| 20150041883 | SEMICONDUCTOR DEVICE - An object of the present invention is to improve the ESD resistance of an electrostatic protection element. | 02-12-2015 |
| 20150054060 | PROTECTION DIODE - A protection diode includes: a semiconductor substrate; a well region of a first conductivity type in the semiconductor substrate; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; a grounding electrode connected to the grounding side diffusion region; and an insulating film on the well region. The grounding electrode extends to the well region on the insulating film. | 02-26-2015 |
| 20150054061 | PROTECTION DIODE - A protection diode includes a semiconductor substrate; a gate side well region of a first conductivity type in the semiconductor substrate; a grounding side well region of the first conductivity type in the semiconductor substrate and joined to the gate side well region; a gate side diffusion region of a second conductivity type in the semiconductor substrate and joined to the gate side well region; a grounding side diffusion region of the second conductivity type in the semiconductor substrate, separated from the gate side diffusion region, and joined to the grounding side well region; a gate side electrode connected between a gate of a transistor and the gate side diffusion region; and a grounding electrode connected to the grounding side diffusion region. Dopant impurity concentration in the grounding side well region is lower than dopant impurity concentration in the gate side well region. | 02-26-2015 |
| 20150084117 | BOTTOM SOURCE NMOS TRIGGERED ZENER CLAMP FOR CONFIGURING AN ULTRA-LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR (TVS) - A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal. | 03-26-2015 |
| 20150115351 | Integrated Circuit and Method of Manufacturing an Integrated Circuit - An integrated circuit includes a power component including a plurality of first trenches in a cell array and a first conductive material in the first trenches electrically coupled to a gate terminal of the power component, and a diode component including a first diode device trench and a second diode device trench disposed adjacent to each other. A second conductive material in the first and the second diode device trenches is electrically coupled to a source terminal of the diode component. The first trenches, the first diode device trench and the second diode device trench are disposed in a first main surface of a semiconductor substrate. The integrated circuit further includes a diode gate contact including a connection structure between the first and the second diode device trenches. The connection structure is in contact with the second conductive material in the first and the second diode device trenches. | 04-30-2015 |
| 20150129954 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel. | 05-14-2015 |
| 20150303301 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film formed around the fin-shaped semiconductor layer, a first metal film formed around the first insulating film, a pillar-shaped semiconductor layer formed on the fin-shaped semiconductor layer, a gate insulating film formed around the pillar-shaped semiconductor layer, a gate electrode formed around the gate insulating film and made of a third metal, a gate line connected to the gate electrode, a second insulating film formed around a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second metal film formed around the second insulating film. The upper portion of the pillar-shaped semiconductor layer and the second metal film are connected to each other, and an upper portion of the fin-shaped semiconductor layer and the first metal film are connected to each other. | 10-22-2015 |
| 20150325567 | SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE | 11-12-2015 |
| 20150333052 | SEMICONDUCTOR STRUCTURE AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - A semiconductor structure and an electrostatic discharge protection circuit are disclosed. The semiconductor structure includes a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure. The second well region has conductivity type opposite to a conductivity type of the first well region. The drain has a conductivity type same as a conductivity type of the source. The source and the drain are formed in the first well region and the second well region respectively. The extending doped region is adjoined with drain and extended under the drain. The extending doped region has a conductivity type same as the conductivity type of the drain. The gate structure is on the first well region. | 11-19-2015 |
| 20150357459 | INTEGRATED CHANNEL DIODE - A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor. | 12-10-2015 |
| 20150372134 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure comprises a substrate, a first well formed in the substrate, a first heavily doped region formed in the first well, a second heavily doped region formed in the substrate and separated apart from the first well, a second well formed in the substrate and under the second heavily doped region, a gate dielectric formed on the substrate between the first heavily doped region and the second heavily doped region, and a gate electrode formed on the gate dielectric. The gate dielectric has a substantially uniform thickness across at least a portion extending from a side close to the second heavily doped region. The first well has a first type of doping. The first heavily doped region, the second heavily doped region and the second well have a second type of doping. | 12-24-2015 |
| 20160035823 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively sides of the gate, a first well region formed in the substrate, and a plurality of first doped islands formed in the source region. The drain region and the source region include a first conductivity, and the first well region and the first doped islands include a second conductivity. The source region is formed in the first well region, and the first doped islands are spaced apart from the first well region. | 02-04-2016 |
| 20160043168 | POWER TRENCH MOSFET WITH IMPROVED UNCLAMPED INDUCTIVE SWITCHING (UIS) PERFORMANCE AND PREPARATION METHOD THEREOF - A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. | 02-11-2016 |
| 20160043216 | SEMICONDUCTOR DEVICE - A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region. | 02-11-2016 |
| 20160049391 | VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE - An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region. | 02-18-2016 |
| 20160064551 | HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD FOR MAKING SUCH DEVICES - Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 03-03-2016 |
| 20160079239 | SERIES-CONNECTED TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other. | 03-17-2016 |
| 20160079376 | Semiconductor Device with Field Electrode Structure - According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm. | 03-17-2016 |
| 20160086942 | SINGLE DIE OUTPUT POWER STAGE USING TRENCH-GATE LOW-SIDE AND LDMOS HIGH-SIDE MOSFETS, STRUCTURE AND METHOD - A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a āPowerDieā). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit. | 03-24-2016 |
| 20160104766 | Power Semiconductor Device with Source Trench and Termination Trench Implants - A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench. | 04-14-2016 |
| 20160148923 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode. | 05-26-2016 |
| 20160149026 | VERTICAL DMOS TRANSISTOR - A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor. | 05-26-2016 |
| 20160155734 | VERTICAL TRANSISTOR WITH FLASHOVER PROTECTION | 06-02-2016 |
| 20160379972 | ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE - Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion. | 12-29-2016 |
| 20220139908 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region. | 05-05-2022 |
