| Entries |
| Document | Title | Date |
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| 20080203439 | Semiconductor integrated circuit having plural transistors - A layout for placing a circuit having a plurality of transistors in a small-width region. A search section inputs data on a circuit and searches for a set of routes formed so that passage through a transistor occurs only one time and so that the combination of routes covers the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes. A width determination section determines the layout width from source and drain electrodes, the region between the source and drain electrodes, the region between adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms a layout in which the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region. | 08-28-2008 |
| 20080224178 | RESISTIVE MEMORY AND METHOD - A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. | 09-18-2008 |
| 20080290376 | Semiconductor Integrated Circuit - [The problems] In a semiconductor integrated circuit in which tilted wiring is used, the tilted wiring cannot be used effectively since the arrangement of blocks is restricted. | 11-27-2008 |
| 20080290377 | THIN FILM TRANSISTOR ARRAY PANEL FOR A LIQUID CRYSTAL DISPLAY - A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines are included. An overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Accordingly, the difference in the RC delays due to the difference of the length of the signal lines is compensated to be reduced. | 11-27-2008 |
| 20080303066 | SEMICONDUCTOR DEVICE - A semiconductor device is provided which can suppress the deterioration of its reliability caused by liquid soaking into a gap. The semiconductor device includes plural gate electrode layers and an interlayer insulating film. The gate electrode layers are formed so as to extend in the same direction in a planar layout and each have a gate wiring portion and a contact pad portion. The interlayer insulating film is formed over the gate electrode layers and gaps so as to leave the gaps each between adjacent gate wiring portions and also between adjacent gate wiring portion and contact pad portion. A second spacing which is the distance between adjacent gate wiring portion and contact pad portion is 2.1 times or less as large as a first spacing which is the distance between adjacent gate wiring portions. | 12-11-2008 |
| 20090085069 | NAND-type Flash Array with Reduced Inter-cell Coupling Resistance - In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of the inter-cell coupling region. The diffusion zone includes a shallow implant region and a deep implant region. In one embodiment, the shallow implant region defines shallow source/drain regions for floating gate transistors of the memory cells. The size of the metal silicide insets are controlled to not compromise isolation PN junctions defined by the shallow and deep implant region. In one embodiment, the metal silicide insets include nickel. | 04-02-2009 |
| 20090134430 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including an element region having a polygonal shape defined by a plurality of edges, and an isolation region surrounding the element region, and a plurality of gate electrodes provided on the substrate, crossing the element region, arranged in parallel with each other, and electrically connected with each other, wherein at least one of the edges does not cross any of the gate electrodes, and is not parallel to the gate electrodes. | 05-28-2009 |
| 20090140298 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - Embodiments relate to a layout structure of a dual port SRAM and a method for forming a SRAM. According to embodiments, a structure where a plurality lines and vias are electrically connected may include first lines that may be electrically connected to a cell region of a memory cell, and a first via, a second line, a second via, a third line, a third via, and a fourth line on and/or over an upper side of the first line,. According to embodiments, the fourth lines arranged on the upper side of the cell region may be formed in a substantially straight form parallel with each other. According to embodiments, the fourth lines may be formed and positioned to prevent bit lines positioned in a cell region of the dual port SRAM from becoming electrically connected to each other. | 06-04-2009 |
| 20090152595 | SEMICONDUCTOR DEVICES AND METHOD OF TESTING SAME - There are provided a semiconductor device having a pattern which allows electric failures to be sensitively detected at high speeds, and a method of testing the same. In one embodiment, the semiconductor device comprises a pair of row wires including a plurality of first wires arranged in a first layer at predetermined intervals in a row direction, where the first wires have ends connected to second wires arranged in a second layer at a predetermined intervals through vias, and the first wire and second wire are at the same potential. In the pair of row wires, a first wire positioned at a right end of one row wire is connected to a first conductor, and a first wire positioned at a left end in the other row wire is connected to a second conductor. By sequentially scanning the first conductor and second conductor using an electron beam, a change in the amount of emitted secondary electrons due to a difference in potential between these conductors is detected to detect electric anomalies. | 06-18-2009 |
| 20090230435 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a plurality of memory cells arranged at intersections of the first lines and the second lines, each memory cell having one end connected to the first line and the other end connected to the second line; a first control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the first line to select and drive the first line; and a second control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the second line to select and drive the second line. | 09-17-2009 |
| 20090236638 | Semiconductor Constructions - The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region. | 09-24-2009 |
| 20090289281 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines. | 11-26-2009 |
| 20090315080 | TRANSISTOR ARRAY WITH SHARED BODY CONTACT AND METHOD OF MANUFACTURING - An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate. | 12-24-2009 |
| 20100001321 | Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions - A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. Each of a number of interconnect level layouts is defined to pattern conductive features within corresponding interconnect levels above the gate electrode level. | 01-07-2010 |
| 20100006901 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The plurality of diffusion regions are separated from each other by one or more non-active regions of the substrate portion. The plurality of diffusion regions are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The number of conductive features within the gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction across the gate electrode level region. | 01-14-2010 |
| 20100006902 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions - A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The conductive features within the gate electrode level region are defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. | 01-14-2010 |
| 20100006903 | Semiconductor Device Portion Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction and fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction. Within a five wavelength photolithographic interaction radius within the gate electrode level region, the width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features. | 01-14-2010 |
| 20100012980 | Contact Structures in Substrate Having Bonded Interface, Semiconductor Device Including the Same, Methods of Fabricating the Same - On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer. | 01-21-2010 |
| 20100012981 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. | 01-21-2010 |
| 20100012982 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features separated by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Conductive features are defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. | 01-21-2010 |
| 20100012983 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features within the gate electrode level region extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 01-21-2010 |
| 20100012984 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a substantially equal and minimum size across the gate electrode level region. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 01-21-2010 |
| 20100012985 | Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight. | 01-21-2010 |
| 20100012986 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level. | 01-21-2010 |
| 20100019280 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level. | 01-28-2010 |
| 20100019281 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within the gate electrode level is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. The cell also includes a number of interconnect levels formed above the gate electrode level. | 01-28-2010 |
| 20100019282 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. The cell also includes a number of interconnect levels formed above the gate electrode level. | 01-28-2010 |
| 20100019283 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a substrate portion including a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level. The cell also includes a number of interconnect levels formed above the gate electrode level. | 01-28-2010 |
| 20100019284 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors - A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level. | 01-28-2010 |
| 20100019285 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors - A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level. | 01-28-2010 |
| 20100019286 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level. | 01-28-2010 |
| 20100019287 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. | 01-28-2010 |
| 20100025734 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication. | 02-04-2010 |
| 20100025735 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. | 02-04-2010 |
| 20100025736 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level. | 02-04-2010 |
| 20100052017 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer. | 03-04-2010 |
| 20100059796 | Shared masks for x-lines and shared masks for y-lines for fabrication of 3D memory arrays - A structure and a method of manufacturing a three dimensional memory using a number of bit line masks that is less than the number of device layers. A first bit line mask is used to form a first bit line layer in a first device level. The first bit line layer comprises first bit lines. The first bit line mask is also used to form a second bit line layer in a second device level. The second bit line layer comprises second bit lines. The first bit lines and the second bit lines have different electrical connections to a bit line connection level despite employing the same mask pattern. | 03-11-2010 |
| 20100096672 | SELF-ALIGNED, INTEGRATED CIRCUIT CONTACT - Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer due to contact misalignment. Embodiments for forming the integrated circuit include performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments also include performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments can be used to form vias and other interconnect structures as well. The modified contacts and vias are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits. | 04-22-2010 |
| 20100117121 | MIRRORED-GATE CELL FOR NON-VOLATILE MEMORY - A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate. | 05-13-2010 |
| 20100123170 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a transistor, a conductive pad, and a contact. The conductive pad is electrically connected to the transistor. The conductive pad may include, but is not limited to, a first region and a second region. The contact is electrically connected to the conductive pad. At least a main part of the first region overlaps the transistor in plan view. At least a main part of the second region does not overlap the transistor in plan view. At least a main part of the contact overlaps the second region in plan view. The at least main part of the contact does not overlap the first region in plan view. The at least main part of the contact does not overlap the transistor in plan view. | 05-20-2010 |
| 20100127309 | INTEGRATED CAPACITOR WITH ALTERNATING LAYERED SEGMENTS - A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed in a second metal layer of the IC extending along the axis and connected to the first node plate with a via. A third node plate link formed in the first metal layer is electrically connected to and forming a portion of a second node of the capacitor and extends along a second axis (x) of the node plate array transverse to the first node plate link, proximate to an end of the first node plate link and overlying a portion of the second node plate link. | 05-27-2010 |
| 20100148220 | STACK ARRAY STRUCTURE FOR A SEMICONDUCTOR MEMORY DEVICE - In a stack array structure for a semiconductor memory device, a first semiconductor layer includes a plurality of first cell strings, and a second semiconductor including a plurality of second cell strings. Bit-line contact plugs are configured to couple a bit-line to two adjacent first cell strings aligned in series in a bit-line direction, and to further couple the bit-line to two adjacent second cell strings respectively located over the two adjacent first cell strings. Common source line contact plugs are configured to couple a common source line to the two adjacent first cell strings and the two adjacent second cell strings. Pocket p-well contact plugs are located at positions corresponding to a layout of the bit-line plugs and/or common source line plugs, and are configured to couple a pocket p-well line to the first semiconductor layer and the second semiconductor layer. | 06-17-2010 |
| 20100171152 | INTEGRATED CIRCUIT INCORPORATING DECODERS DISPOSED BENEATH MEMORY ARRAYS - A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate. | 07-08-2010 |
| 20100176422 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval. | 07-15-2010 |
| 20100270593 | INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD - A 3D memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable element and a rectifier. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension. | 10-28-2010 |
| 20110018035 | Offset Geometries for Area Reduction in Memory Arrays - An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other. | 01-27-2011 |
| 20110018036 | VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines. | 01-27-2011 |
| 20110042722 | INTEGRATED CIRCUIT STRUCTURE AND MEMORY ARRAY - An integrated circuit structure includes a plurality of first doped regions disposed in a substrate in a matrix having odd columns and even columns each immediately adjacent to a corresponding one of the odd columns, a plurality of buried bit lines disposed in the substrate to electrically connect to the plurality of first doped regions of the same odd column in the matrix, and a plurality of surface bit lines disposed above an uppermost surface of the substrate, wherein each of the surface bit lines electrically connects to the first doped regions of the same even column in the matrix. | 02-24-2011 |
| 20110049576 | Homogenous Cell Array - A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently connected than a rest of the homogenous cells of the column. | 03-03-2011 |
| 20110073917 | Method of high density memory fabrication - The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level. | 03-31-2011 |
| 20110108889 | SEMICONDUCTOR DEVICE WITH A 7F2 CELL STRUCTURE - A semiconductor device with a 7F | 05-12-2011 |
| 20110121367 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including transistors B on an output side of a current mirror, arranged uniformly in a surrounding area of a transistor A on an input side of the current mirror. The transistors B are arranged at equal distances, adjacently to the transistor A, on both sides of the transistor A. | 05-26-2011 |
| 20110133254 | CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING - An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair and at least one other signal conductor, and the arrangement includes the at least one other signal conductor disposed at a substantially same distance from each conductor of the first differentially driven signal conductor pair. | 06-09-2011 |
| 20110147800 | SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINES WITH FINE LINE WIDTH AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process. | 06-23-2011 |
| 20110156102 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line. | 06-30-2011 |
| 20110175143 | SEMICONDUCTOR MEMORY APPARATUS - The semiconductor memory apparatus related to an embodiment of the present invention includes a wiring substrate arranged with a device mounting part and connection pads aligned along one exterior side of the wiring substrate, a plurality of semiconductor memory devices including electrode pads which are arranged along one external side of the wiring substrate, a semiconductor memory device group in which the plurality of semiconductor memory devices are stacked on the device mounting part of the wiring substrate so that pad arrangement sides all face in the same direction, and a controller device including the electrode pads arranged along at least one external side of the wiring substrate, wherein the electrode pads of the plurality of semiconductor memory devices and the electrode pads of the controller device are arranged parallel to an arrangement position of the connection pads of the wiring substrate. | 07-21-2011 |
| 20110220968 | DEVICE - A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line. | 09-15-2011 |
| 20110241077 | INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD - A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable element and a rectifier. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection. | 10-06-2011 |
| 20110248317 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes lateral and upper hydrogen blocking patterns disposed to prevent hydrogen from diffusing into the cell array region. Accordingly, hydrogen is effectively prevented from being trapped in a tunnel dielectric, thereby improving the reliability of the semiconductor device. In the method, when a cell array contact plug is formed, a lateral hydrogen blocking pattern and an upper hydrogen blocking pattern are formed at the same time. Thus, an additional process for forming a hydrogen blocking pattern is unnecessary, thereby simplifying a process. | 10-13-2011 |
| 20110248318 | METHOD AND APPARATUS FOR CONFIGURABLE SYSTEMS - The present invention relates to a flexible analog/digital configuration, preferably on a chip, that can be used for receiving various inputs, processing those inputs, and displaying/communicating the results and/or providing a response thereto. More particularly, the present invention can measure multiple parameters and, when properly programmed, can easily organize the data from multiple sensors or other analog or digital sources. It can present or display different, or similar, pages for setting up each measurement (or each measured parameter) (e.g., by sensor, class of sensors, etc.) to enable an easy to use approach for individuals without needing to know the specifics as to many parameters. This user-friendly approach can be performed using a configurable chip module system. A configurable chip module system can include analog elements, digital elements, and connection elements between the analog and digital elements, where some of the analog elements and/or digital elements receive inputs from one or more sources and where some of the analog elements and/or digital elements generate output signals for generating control signals and/or outputs that present measurements to output receiving elements. The system includes a configuration mechanism that automatically configures the connection elements in response to receiving selections entered on a user interface, where the user interface allows a user to input commands to modify the structure of the chip module system. | 10-13-2011 |
| 20110298013 | Vertical Structure Semiconductor Memory Devices And Methods Of Manufacturing The Same - A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes. | 12-08-2011 |
| 20110309414 | Diode polarity for diode array - A memory-array is disclosed in which an array of non-linear conductors such as diodes is constructed having an area per memory cell of 4F | 12-22-2011 |
| 20120001232 | ROM CELL CIRCUIT FOR FINFET DEVICES - The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a Vss line, and each cell of a second subset of ROM cells has a source electrically isolated. Each cell of the first subset of ROM cells includes a drain contact having a first contact area and a source contact having a second contact area at least 30% greater than the first contact area. | 01-05-2012 |
| 20120001233 | Novel embedded NOR flash memory process with NAND cell and true logic compatible low voltage device - An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line. | 01-05-2012 |
| 20120012897 | Vertically Fabricated BEOL Non-Volatile Two-Terminal Cross-Trench Memory Array with Two-Terminal Memory Elements and Method of Fabricating the Same - A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required. | 01-19-2012 |
| 20120074467 | SWITCH ARRAY - According to one embodiment, a switch array includes first and second switches provided in a switch unit. The first switch includes first and second memory cell transistors and a first pass transistor. A second switch includes third and fourth memory cell transistors and a second pass transistor. The first and second memory cell transistor is provided in a first active region. The first pass transistor is provided in a second active region in the substrate. The third and fourth memory cell transistor is provided in the first active region. The second pass transistor is provided in the second active region adjacent to the first pass transistor in the channel length direction. The first and second active regions are adjacent to each other in a channel width direction. | 03-29-2012 |
| 20120080725 | VERTICAL TRANSISTOR MEMORY ARRAY - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array. | 04-05-2012 |
| 20120091510 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, MASK FOR SEMICONDUCTOR MANUFACTURE, AND OPTICAL PROXIMITY CORRECTION METHOD - An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area ( | 04-19-2012 |
| 20120119263 | WAFER LEVEL PACKAGING - Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die. | 05-17-2012 |
| 20120181580 | Semiconductor Structure and Manufacturing Method of the Same - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric element, a conductive line, and conductive islands. The stacked structure is formed on the substrate. The stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is formed on the stacked structure. The conductive line is formed on the dielectric element. The conductive line is extended in a direction perpendicular to a direction which the stacked structure is extended in. The conductive islands are formed on the dielectric element. The conductive islands on the opposite sidewalls of the single stacked structure are separated from each other. | 07-19-2012 |
| 20120193681 | 3D SEMICONDUCTOR DEVICE - A wafer includes a group of tiles of programmable logic formed thereon, wherein each tile comprises a micro control unit (MCU) communicating with adjacent MCUs, and wherein each MCU is controlled in a predetermined order of priority by adjacent MCUs; and dice lines on the wafer to separate the group into one or more end-devices. | 08-02-2012 |
| 20120223369 | Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors - Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors. | 09-06-2012 |
| 20120248504 | Arrays Of Memory Cells And Methods Of Forming An Array Of Vertically Stacked Tiers Of Memory Cells - An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed. | 10-04-2012 |
| 20120261723 | SEMICONDUCTOR DEVICE - A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch. | 10-18-2012 |
| 20120273841 | Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same - A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell. | 11-01-2012 |
| 20120273842 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line. | 11-01-2012 |
| 20120299063 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer. | 11-29-2012 |
| 20120299064 | SEMICONDUCTOR DEVICE - A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor. | 11-29-2012 |
| 20130001649 | SEMICONDUCTOR DEVICE EMPLOYING CIRCUIT BLOCKS HAVING THE SAME CHARACTERISTICS - A semiconductor device is disclosed, which comprises First and second inputs ports, first and second output nodes, and first and second transistors. The first transistor includes first and second diffusion regions defining a first channel region and a first gate electrode and connected to the first input port, the first diffusion region being connected to the first output node, the second diffusion region being disposed between the first diffusion region and the first input port and supplied with a first operating potential. The second transistor includes third and fourth diffusion regions defining a second channel region and a second gate electrode and connected to the second input port, the third diffusion region being supplied with the first operating potential, the fourth diffusion region being disposed between the third diffusion region and the second input port and connected to the second output node. | 01-03-2013 |
| 20130037859 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF - A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application. | 02-14-2013 |
| 20130043509 | 3-D STRUCTURED NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line. | 02-21-2013 |
| 20130049074 | METHODS FOR FORMING CONNECTIONS TO A MEMORY ARRAY AND PERIPHERY - Methods are disclosed for forming connections to a memory array and a periphery of the array. The methods include forming stacks of conductive materials on the array and the periphery and forming a step between the periphery stack and the array stack. The step is removed during subsequent processing, and connections are formed from the conductive materials remaining on the array and the periphery. In some embodiments, the step is removed before any photolithographic processes. | 02-28-2013 |
| 20130256761 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, and a method of fabrication the same, include selection gate patterns extending in a first direction on a substrate, cell gate patterns extending in parallel in the first direction between the selection gate patterns adjacent to each other, and contact pads connected to first end parts of the cell gate patterns, respectively. An insulating layer covers the selection gate patterns, the cell gate patterns, and the contact pads. The insulating layer includes a void or seam between the contact pads. A filling insulating layer fills the void or seam in the insulating layer. | 10-03-2013 |
| 20130256762 | PROGRAMMABLE LOGIC DEVICE - An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal. | 10-03-2013 |
| 20140183603 | SIGNAL PATH AND METHOD OF MANUFACTURING A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks having signal track patterns, determining a quality characteristic of the signal track patterns, and selecting a photomask for etching vias. | 07-03-2014 |
| 20140327050 | STANDARD CELL HAVING CELL HEIGHT BEING NON-INTEGRAL MULTIPLE OF NOMINAL MINIMUM PITCH - An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch. | 11-06-2014 |
| 20150048424 | STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD - A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern. | 02-19-2015 |
| 20150303216 | SEMICONDUCTOR DEVICE - A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect. | 10-22-2015 |
| 20160079276 | Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same - A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration. | 03-17-2016 |
| 20160172375 | Methods for Cell Boundary Encroachment and Semiconductor Devices Implementing the Same | 06-16-2016 |
