| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257210000 | With wiring channel area | 7 |
| 20090134431 | NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage apparatus includes: a plurality of first wirings; a plurality of second wirings which cross the plurality of first wirings; and a memory cell which is connected between both the wirings at an intersection of the first and second wirings, and includes a variable resistive element operative to store information according to a change in resistance and includes a variable resistive element, wherein the memory cell is formed so that a cross section area of the variable resistive element becomes smaller than a cross section area of the other portion. | 05-28-2009 |
| 20090200579 | Semiconductor device and layout method thereof - A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines and the second lines so as to match the arrangement order. In the semiconductor device, at least adjacent two tracks are defined in a linear manner parallel to a second direction perpendicular to the first direction. Then, each of the second lines includes a first line portion extending along one of the two tracks, a second line portion extending along another of the two tracks, and a connection portion connecting between the first and second line portions, while two or more of the contacts are formed at the connection portion. | 08-13-2009 |
| 20090261386 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF ARRANGING WIRINGS IN THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a first component, a second component, a plurality of first, second and third contacts, and a plurality of signal lines having a plurality of first wires, and connecting the first and second component, each of the first wires having a first, second, third and fourth part, each of the parts having a resistivity, the second part having a first resistivity, a different value of the first resistance being set for each of the plurality of first wires, the first, third and fourth parts having a second or third resistivity which is lower than the first resistivity, the first and second part being electrically connected in series by the first contact, the second and third part being electrically connected in series by the second contact, and the third and fourth part being electrically connected in series by the third contact. | 10-22-2009 |
| 20090283803 | ELECTROMECHANICAL MEMORY ARRAY USING NANOTUBE RIBBONS AND METHOD FOR MAKING SAME - Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes. | 11-19-2009 |
| 20100006905 | SEMICONDUCTOR MEMORY DEVICE - To facilitate counting of memory cells in failure analysis, without limiting the arrangement of memory cells or increasing the number of processes. A memory cell array region | 01-14-2010 |
| 20100140666 | Semiconductor devices having L-shaped cell blocks - Semiconductor devices are provided including a plurality of L-shaped cell blocks each including,a cell array and a plurality of decoders disposed in horizontal and vertical directions of the cell array. The plurality of L-shaped cell blocks are oriented in a diagonal direction intersecting the horizontal and vertical directions. Related methods are also provided herein. | 06-10-2010 |
| 20110068373 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n | 03-24-2011 |
