Entries |
Document | Title | Date |
20080210978 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts. | 09-04-2008 |
20080217655 | INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES - An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines. | 09-11-2008 |
20080224176 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C | 09-18-2008 |
20080237644 | SPATIALLY AWARE DRIVE STRENGTH DEPENDENT DIE SIZE INDEPENDENT COMBINATORIAL SPARE CELL INSERTION MANNER AND RELATED SYSTEM AND METHOD - A design method for an integrated circuit adds spare cells in a System-on-Chip to allow for Engineering Change Orders (ECOs) to be performed at a later stage in the design. This method can be used to provide a second version of the chip having minimal alterations performed in a short cycle time. The spare cells can be divided into combinational and sequential cells. There is an optimum spread of combinational cells in the design for post placement repairs of the chip with just metal layer changes. The method takes into account the drive strength of the spare cells as the main factor in their placement on the chip. | 10-02-2008 |
20080265284 | SEMICONDUCTOR DEVICE - A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region. | 10-30-2008 |
20080265285 | MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME - A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure. | 10-30-2008 |
20080290373 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides. | 11-27-2008 |
20080290374 | LAYOUT FOR HIGH DENSITY CONDUCTIVE INTERCONNECTS - In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry. | 11-27-2008 |
20080296628 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING SAME - A semiconductor integrated circuit includes at least one first circuit portion and at least one second circuit portion. The first circuit portion includes a first interconnect or a diffusion layer formed by exposure using a high-precision mask. The second circuit portion includes a second interconnect or a diffusion layer formed by exposure using a first low-precision mask having a lower precision than the high-precision mask. | 12-04-2008 |
20080315258 | CELL BASED INTEGRATED CIRCUIT AND UNIT CELL ARCHITECTURE THEREFOR - A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern extends in the first direction across the first conductive type active region and second conductive type active region. A first contact region is adjacent the first end of the first conductive type active region in the first direction. A second contact region is adjacent the second end of the second conductive type active region in the first direction. | 12-25-2008 |
20090001425 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film. | 01-01-2009 |
20090008680 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip. | 01-08-2009 |
20090085067 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD THEREFOR - A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer. It is possible to design a semiconductor device having a smaller area than that in the past and with a less design man-hour. | 04-02-2009 |
20090114951 | MEMORY DEVICE - A memory device can be implemented including word lines connected to an array of memory transistors. Each memory transistor is also connected to bit lines and a select transistor. The select transistors each have their sources connected to a conductive source line, by a shunt and the gate of each select transistor is connected to a select line. | 05-07-2009 |
20090146188 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device includes a plurality of integrated memory cells. Each cell includes a first inverter having a first driver transistor and a first load transistor which are formed on a semiconductor substrate in order to form a first storage node, a second inverter having a second driver transistor and a second load transistor which are formed on the semiconductor substrate in order to form a second storage node, a first transfer transistor connected between the first storage node and a bit line to serve as a transistor connecting the memory cell to the bit line, and a second transfer transistor connected between the second storage node and a complementary-bit line to serve as a transistor connecting the memory cell to the complementary-bit line. | 06-11-2009 |
20090189193 | SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE - A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class. | 07-30-2009 |
20090212327 | STANDARD CELL LIBRARIES AND INTEGRATED CIRCUIT INCLUDING STANDARD CELLS - A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction. The second power rail extends in the first direction, and is spaced apart from the first power rail by a predetermined spacing in a second direction perpendicular to the first direction. The third power rail extends in the first direction between the first power rail and the second power rail. The first standard cell has at least one cell having a first cell height, and is arranged between the first power rail and the second power rail. The second standard cells have at least two cells, each having a second cell height, that are in contact with each other in the second direction, and are in contact with the first standard cell in the first direction. | 08-27-2009 |
20090212328 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad. | 08-27-2009 |
20090218600 | Memory Cell Layout - A method for manufacturing an integrated circuit and an integrated circuit are described. In one embodiment, the method for manufacturing the integrated circuit includes determining a layout for numerous memory elements based on memory-specific parameters, and determining a layout for a front-end-of-line (FEOL) component of the integrated circuit based on electrical parameters. Once these two layouts are determined, the layouts are combined to produce a layout for a memory cell on the integrated circuit. | 09-03-2009 |
20090230434 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a semiconductor substrate; a memory block formed on the semiconductor substrate and including plural stacked cell array layers of cell arrays each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contacts extending in the stack direction of the cell array layers and connecting the first lines in the cell arrays with diffusion regions formed on the semiconductor substrate. A certain one of the cell array layers is smaller in the number of the first lines divided and the number of contacts connected than the cell array layers in a lower layer located closer to the semiconductor substrate than the certain one. | 09-17-2009 |
20090236636 | Closed Cell Array Structure Capable of Decreasing Area of non-well Junction Regions - A closed cell array structure capable of decreasing area of non-well junction regions includes a plurality of closed cell units, arranged in a plane, each shaped as a polygon, and a plurality of gate windows, each formed in a corner of a closed cell unit in a gate layer without doped source ion material. | 09-24-2009 |
20090321789 | Triangle two dimensional complementary patterning of pillars - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape. | 12-31-2009 |
20100006896 | Semiconductor integrated circuit - A semiconductor integrated circuit has: a substrate; a basic logic cell placed on the substrate and configured to function as a part of a logic circuit; and a dummy cell placed on the substrate and not configured to function as a part of a logic circuit. The basic logic cell includes a diffusion layer formed in the substrate, and a distance from the diffusion layer to a boundary between the basic logic cell and another cell adjacent to the basic logic cell is equal to a first distance. The dummy cell includes a dummy diffusion layer that is a diffusion layer formed in the substrate, and a distance from the dummy diffusion layer to a boundary between the dummy cell and another cell adjacent to the dummy cell is equal to the first distance. | 01-14-2010 |
20100096669 | MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES - An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines. | 04-22-2010 |
20100207168 | Cross-Point Memory Structures, And Methods Of Forming Memory Arrays - Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction. | 08-19-2010 |
20100230724 | METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES, AND RELATED STRUCTURES - Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example. | 09-16-2010 |
20100308377 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor. | 12-09-2010 |
20100327323 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional nonvolatile memory device includes: a plurality of channel structures extending in parallel in a first direction and comprising a plurality of channel layers that are alternatively stacked with a plurality of interlayer insulating layers over a substrate; a plurality of memory cells stacked along sidewalls of the channel structures and arranged in the first direction and a second direction crossing the first direction; and a plurality of word lines extending in parallel in the second direction and connected to the memory cells arranged in the second direction. | 12-30-2010 |
20110006347 | LAYOUT FOR HIGH DENSITY CONDUCTIVE INTERCONNECTS - In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry. | 01-13-2011 |
20110084312 | Methods for Cell Boundary Encroachment and Layouts Implementing the Same - A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device. | 04-14-2011 |
20110095338 | METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING - The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed. | 04-28-2011 |
20110233617 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 09-29-2011 |
20110278648 | METHOD OF INTRODUCING A STRUCTURE IN A SUBSTRATE - This invention relates to methods for the production of micro-structured substrates and their application in natural sciences and technology, in particular in semiconductor, microfluidic and analysis devices. It concerns a method of introducing a structure, such as a hole or cavity or channel or well or recess or a structural change by providing a controlled electrical discharge. | 11-17-2011 |
20120161206 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR WAFER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array unit and an alignment mark unit. The cell array unit includes a first memory string, a second memory string and a device isolation insulating layer. The first string is provided on a major surface of a semiconductor layer. The second string is juxtaposed with the first memory string. The device isolation insulating layer partitions the first and second memory strings from each other. The mark unit juxtaposed with the array unit includes a mark unit semiconductor layer and a mark unit insulating layer. The mark unit semiconductor layer is a part of the semiconductor layer. The mark unit insulating layer is juxtaposed with the mark unit semiconductor layer. An upper surface of the mark unit semiconductor layer is included in a plane different from a plane including an upper surface of the mark unit insulating layer. | 06-28-2012 |
20120175683 | Basic Cell Architecture For Structured ASICs - A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs. | 07-12-2012 |
20120261722 | Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells - A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed. | 10-18-2012 |
20120286331 | INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS - Integrated circuit ( | 11-15-2012 |
20120292666 | SEMICONDUCTOR DEVICE - In end portions of first and second gate patterns aligned in parallel relation to each other, and opposite end portions of third and fourth gate patterns aligned in parallel relation to each other, the end portion of the first gate pattern extends to be positioned closer to the third and fourth gate patterns than the end portion of the second gate pattern is, and the opposite end portion of the fourth gate pattern extends to be positioned closer to the first and second gate patterns than the opposite end portion of the third gate pattern is. | 11-22-2012 |
20130009213 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a pattern on a substrate. The semiconductor devices may also include a capping dielectric layer on the pattern. The semiconductor devices may further include a first nitride layer on the capping dielectric layer. Moreover, the semiconductor devices may include a second nitride layer on the first nitride layer. A concentration of nitrogen in the first nitride layer may be greater than that in the second nitride layer. | 01-10-2013 |
20130026542 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer having a plurality of active regions that are separated by element isolation grooves, a capacitive film having a sidewall covering portion covering a sidewall of the element isolation grooves, and an electrode film laminated on the capacitive film, and a capacitor element is formed by the semiconductor layer, the capacitive film and the electrode film. | 01-31-2013 |
20130056798 | Three-Dimensional Printed Memory - As technology scales, the mask cost rises sharply. It was generally believed that three-dimensional mask-programmed read-only memory (3D-MPROM) would become economically un-viable. The present invention discloses a three-dimensional printed memory (3D-P). It is a type of 3D-MPROM and uses shared data-masks to print data. By forming the mask-patterns for a plurality of distinct mass-contents on a same data-mask, the share of the data-mask cost on each mass-content is significantly reduced. For mass publication, the minimum feature size of the 3D-P is preferably less than 45 nm. | 03-07-2013 |
20130069118 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device according to an embodiment includes a semiconductor substrate and a transistor provided on the semiconductor substrate. The transistor includes a conductive layer, a gate insulating layer, a semiconductor layer, and an oxidation layer. The conductive layer functions as a gate of the transistor. The gate insulating layer contacts with a side surface of the conductive layer. The semiconductor layer has a side surface sandwiching the gate insulating layer with the conductive layer, extends a direction perpendicular to the semiconductor substrate, and functions as a body of the transistor. The oxidation layer contacts with the other side surface of the semiconductor layer. The semiconductor layer is made of silicon germanium. The oxidation layer is made of a silicon oxide. | 03-21-2013 |
20130105864 | LAYOUT CONFIGURATION FOR MEMORY CELL ARRAY | 05-02-2013 |
20130161700 | METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE - The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness. | 06-27-2013 |
20130193488 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer overlying the at least one metal layer; wherein the second layer includes second transistors, the second transistors include mono-crystal, the second transistors include P type transistors and N type transistors, and the second transistors are aligned to the first alignment mark with less than 40 nm alignment error. | 08-01-2013 |
20130207163 | Semiconductor Devices and Manufacturing Methods Thereof - Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less. | 08-15-2013 |
20130207164 | SEMICONDUCTOR DEVICE - To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR | 08-15-2013 |
20130234210 | METHOD OF MANUFACTURING METAL SILICIDE AND SEMICONDUCTOR STRUCTURE USING THE SAME - A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates. | 09-12-2013 |
20130334575 | Damascene Word Line - The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures. | 12-19-2013 |
20140021515 | MICROMECHANICAL STRUCTURE, IN PARTICULAR SENSOR ARRANGEMENT, AND CORRESPONDING OPERATING METHOD - A micromechanical structure, in particular a sensor arrangement, includes at least one micromechanical functional layer, a CMOS substrate region arranged below the at least one micromechanical functional layer, and an arrangement of one or more contact elements. The CMOS substrate region has at least one configurable circuit arrangement. The arrangement of one or more contact elements is arranged between the at least one micromechanical functional layer and the CMOS substrate region and is electrically connected to the micromechanical functional layer and the circuit arrangement. The configurable circuit arrangement is designed in such a way that the one or more contact elements are configured to be selectively connected to electrical connection lines in the CMOS substrate region. | 01-23-2014 |
20140027819 | CORNER LAYOUT FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES - A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform distance from the nearest termination device structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 01-30-2014 |
20140042496 | SEMICONDUCTOR DEVICE - A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor. | 02-13-2014 |
20140151751 | DENSITY GRADIENT CELL ARRAY - One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions. | 06-05-2014 |
20140167117 | Methods for Cell Boundary Encroachment and Layouts Implementing the Same - A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device. | 06-19-2014 |
20140183602 | ALTERNATING TAP-CELL STRATEGY IN A STANDARD CELL LOGIC BLOCK FOR AREA REDUCTION - An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located between the tap columns. A plurality of tap cells is disposed consecutively in the plurality of tap columns. Each tap cell further includes a first tap active and a second tap active. The first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell. The first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column. | 07-03-2014 |
20140252418 | ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE - A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals. | 09-11-2014 |
20140264460 | THREE-TERMINAL PRINTED DEVICES INTERCONNECTED AS CIRCUITS - A layer of microscopic, 3-terminal transistors is printed over a first conductor layer so that bottom electrodes of the transistors electrically contact the first conductor layer. A first dielectric layer overlies the first conductor layer, and a second conductor layer over the first dielectric layer contacts intermediate electrodes on the transistors between the bottom electrodes and top electrodes. A second dielectric layer overlies the second conductor layer, and a third conductor layer over the second dielectric layer contacts the top electrodes. The devices are thus electrically connected in parallel by a combination of the first conductor layer, the second conductor layer, and the third conductor layer. Separate groups of the devices may be interconnected to form more complex circuits. The resulting circuit may be a very thin flex-circuit. | 09-18-2014 |
20140291729 | MEMORY UNIT, MEMORY UNIT ARRAY AND METHOD OF MANUFACTURING THE SAME - A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region. | 10-02-2014 |
20140299920 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present disclosure provides a layout of a semiconductor integrated circuit device that can assure a lot of substrate contact regions, and can surely suppress latch-up without increasing an area of a whole semiconductor integrated circuit and without significantly decreasing a decoupling capacitance element. In a margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on a P-type well. In the margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on an N | 10-09-2014 |
20150129935 | Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells - A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed. | 05-14-2015 |
20150303177 | THREE-TERMINAL PRINTED DEVICES INTERCONNECTED AS CIRCUITS - A layer of microscopic, 3-terminal transistors is printed over a first conductor layer so that bottom electrodes of the transistors electrically contact the first conductor layer. A first dielectric layer overlies the first conductor layer, and a second conductor layer over the first dielectric layer contacts intermediate electrodes on the transistors between the bottom electrodes and top electrodes. A second dielectric layer overlies the second conductor layer, and a third conductor layer over the second dielectric layer contacts the top electrodes. The devices are thus electrically connected in parallel by a combination of the first conductor layer, the second conductor layer, and the third conductor layer. Separate groups of the devices may be interconnected to form more complex circuits. The resulting circuit may be a very thin flex-circuit. | 10-22-2015 |
20160020222 | DENSITY GRADIENT CELL ARRAY - One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions. | 01-21-2016 |
20190147132 | SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS | 05-16-2019 |