Entries |
Document | Title | Date |
20080251812 | Heteroepitaxial Crystal Quality Improvement - Methods and systems for improving heteroepitaxial crystal quality of semiconductor materials include forming a pattern on the semiconductor substrate over which the hetero-epitaxial layer is grown. The pattern provides predetermined sites for dislocation initiation and termination of dislocation propagation. The layer may be treated with a focused laser beam during or subsequent to the layer growth process. Laser light may be focused at a selected depth, where the light intensity is sufficient to cause structural and/or electronic changes localized at that depth. The laser beam may be selectively scanned to provide the desired change only at preferred spatial locations on the substrate. The laser wavelength and power may be selected to be appropriate for the materials being treated. | 10-16-2008 |
20080258173 | VERTICAL P-N JUNCTION DEVICE AND METHOD OF FORMING SAME - A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a conductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode. | 10-23-2008 |
20090065803 | Space-Charge-Free Semiconductor and Method - A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the Fermi-level of the n-type material is equal to the energy of the Fermi-level of the p-type material. This allows for the pre-alignment of the Fermi-levels of the n-type and the p-type materials. The semiconductor has minimal or no g-r noise. The semiconductor can be operated at T | 03-12-2009 |
20090114948 | SEMICONDUCTOR DEVICE - To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate ( | 05-07-2009 |
20090189184 | Semiconductor-On-Diamond Devices and Associated Methods - Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (Alp), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation. | 07-30-2009 |
20090189185 | EPITAXIAL GROWTH OF RELAXED SILICON GERMANIUM LAYERS - A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 10 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface. | 07-30-2009 |
20090194787 | VERTICAL OUTGASSING CHANNELS - InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H | 08-06-2009 |
20090278169 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers. | 11-12-2009 |
20090283800 | PHOTOELECTROCHEMICAL ETCHING OF P-TYPE SEMICONDUCTOR HETEROSTRUCTURES - A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer. | 11-19-2009 |
20100001316 | EPITAXIAL LIFT OFF STACK HAVING A NON-UNIFORM HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming a thin film material during an epitaxial lift off process is provided which includes forming an epitaxial material over a sacrificial layer on a substrate, adhering a non-uniform support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate while forming an etch crevice therebetween and bending the support handle to form compression in the epitaxial material during the etching process. In one example, the non-uniform support handle contains a wax film having a varying thickness. | 01-07-2010 |
20100012972 | Silicon-Germanium Hydrides and Methods for Making and Using Same - The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds. | 01-21-2010 |
20100025727 | ENHANCED SPONTANEOUS SEPARATION METHOD FOR PRODUCTION OF FREE-STANDING NITRIDE THIN FILMS, SUBSTRATES, AND HETEROSTRUCTURES - The present invention provides a superior method for the removal of nitride semiconductor thin films, thick films, heterostructures, and bulk material from initial substrates and/or templates. The method utilizes specially patterned mask layers between the initial substrates/templates and the nitride semiconductors to decrease adhesion between the nitride semiconductor and underlying material. Thermal stresses generated upon cooling the nitride semiconductor from its deposition temperature trigger spontaneous separation of the nitride semiconductor from the initial substrate or template at the mask layer. The invention remedies deficiencies in the prior art by providing a simple, reproducible, and effective means of removing initial substrates and templates from a variety of nitride semiconductor layers and structures. | 02-04-2010 |
20100038678 | Photodiode with a Reduced Dark Current and Method for the Production Thereof - A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of which additional doping the pn junction is shifted deeper into the substrate (SU). With the greater distance of the pn junction from defects at phase boundaries that is achieved in this way, the dark current within the photodiode is reduced. | 02-18-2010 |
20100052013 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is desired for semiconductor devices to reduce leakage currents. In a semiconductor device having a stacked structure including a GaAs layer and an InGaP layer, p-type impurity is doped to the GaAs layer. Consequently, the conduction band of the GaAs is raised to higher than the Fermi level. As a result, electron accumulation is suppressed and the gate leakage current can be reduced. | 03-04-2010 |
20100072513 | SEMICONDUCTOR HETEROSTRUCTURES AND MANUFACTURING THEREOF - A semiconductor heterostructure ( | 03-25-2010 |
20100078678 | SEMICONDUCTOR ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area to the upper layer area is bent at said boundary surface. | 04-01-2010 |
20100123169 | COMPOUND SEMICONDUCTOR SUBSTRATE AND DEVICE THEREWITH - A semiconductor device is formed on a semiconductor substrate, which is comprised of: a base substrate; and a multilayer being formed on the base substrate and having a surface serving for an interface with the semiconductor device, the multilayer including alternating layers of a first compound semiconductor and a second compound semiconductor materially distinguishable from the first compound semiconductor, one selected from the group consisting of the first compound semiconductor and the second compound semiconductor being doped with one selected from the group consisting of carbon and transition elements. | 05-20-2010 |
20100140660 | Semiconductor Heterostructure Diodes - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 06-10-2010 |
20100252861 | Devices Formed from a Non-Polar Plane of a Crystalline Material and Method of Making the Same - Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region. | 10-07-2010 |
20100264458 | METHOD FOR MANUFACTURING HETEROSTRUCTURES - A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure. | 10-21-2010 |
20100270588 | Formulations for voltage switchable dielectric material having a stepped voltage response and methods for making the same - Formulations for voltage switchable dielectric materials include two or more different types of semiconductive materials uniformly dispersed within a dielectric matrix material. The semiconductive materials are selected to have different bandgap energies in order to provide the voltage switchable dielectric material with a stepped voltage response. The semiconductive materials can comprise inorganic particles, organic particles, or an organic material that is soluble in, or miscible with, the dielectric matrix material. Formulations optionally can also include electrically conductive materials. At least one of the conductive or semiconductive materials in a formulation can comprise particles characterized by an aspect ratio of at least 3 or greater. | 10-28-2010 |
20100276730 | SEMICONDUCTOR DEVICE - Semiconductor devices having at least one barrier layer are disclosed. In some embodiments, a semiconductor device includes an active layer and one or more barrier layers disposed on either one side or both sides of the active layer. The active layer may be composed of a first compound semiconductor material, and the one or more barrier layers may be composed of a second compound semiconductor material. In some embodiments, the composition of the one or more barrier layers may be adjusted to increase an optical dipole matrix element. | 11-04-2010 |
20100289060 | METHOD OF FABRICATING FREE-FORM, HIGH-ASPECT RATIO COMPONENTS FOR HIGH-CURRENT, HIGH-SPEED MICROELECTRONICS - Microelectronic structures and devices, and method of fabricating a three-dimensional microelectronic structure is provided, comprising passing a first precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures to enhance formation of a first portion of said three-dimensional microelectronic structure; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said first portion of a selected three-dimensional microelectronic structure is formed from said first precursor material; positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs; passing a second precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures whereby a second portion of said three-dimensional microelectronic structure formation is enhanced; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said second portion of a selected three-dimensional microelectronic structure is formed from said second precursor material; and, positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs. | 11-18-2010 |
20100314661 | SEMICONDUCTOR SUBSTRATE, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING THE SAME - The present invention provides a fabrication method of a semiconductor substrate, by which a planar GaN substrate that is easily separated can be fabricated on a heterogeneous substrate, and a semiconductor device which is fabricated using the GaN substrate. The semiconductor substrate comprises a substrate, a first semiconductor layer arranged on the substrate, a metallic material layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and voids formed in the first semiconductor layer under the metallic material layer. | 12-16-2010 |
20110006343 | SEMICONDUCTOR WAFER, METHOD OF MANUFACTURING A SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE - The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that has an open portion reaching the silicon wafer; a Ge crystal formed in the open portion; a seed compound semiconductor crystal that is grown with the Ge crystal as a nucleus and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface. | 01-13-2011 |
20110057231 | Semiconductor device and method for manufacturing of the same - The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode. | 03-10-2011 |
20110220964 | SEMICONDUCTOR DEVICE HAVING FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall. | 09-15-2011 |
20110227129 | SEMICONDUCTOR SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A semiconductor wafer including: a base wafer; a seed crystal disposed on the base wafer; a compound semiconductor disposed above the seed crystal; and a high resistance layer disposed between the seed crystal and the compound semiconductor, the high resistance layer having a larger resistivity than the seed crystal, and the seed crystal lattice matching or pseudo lattice matching the compound semiconductor is provided. | 09-22-2011 |
20110227130 | STRUCTURES AND METHODS OF FORMING SIGE AND SIGEC BURIED LAYER FOR SOI/SIGE TECHNOLOGY - Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions. | 09-22-2011 |
20110266594 | METHOD FOR OBTAINING A LAYER OF ALN HAVING SUBSTANTIALLY VERTICAL SIDES - A method is disclosed, for producing a layer of AlN having substantially vertical sides relative to the surface of a substrate, comprising:
| 11-03-2011 |
20110272736 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region. | 11-10-2011 |
20110272737 | TRANSISTOR AND TRANSISTOR CONTROL SYSTEM - A transistor includes a transistor body, and a stress application section applying stress to the transistor body. The transistor body includes a formation substrate, and a first semiconductor layer and a second semiconductor layer which are sequentially stacked on the formation substrate. The second semiconductor layer having a wider bandgap than the first semiconductor layer. The stress application section applies stress to the transistor body so that tensile stress applied to the second semiconductor layer increases in accordance with an increase in a temperature. | 11-10-2011 |
20110316043 | Thin Group IV Semiconductor Structures - Thin group IV semiconductor structures are provided comprising a thin Si substrate and a second region formed directly on the Si substrate, where the second region comprises either (i) a Ge1 | 12-29-2011 |
20120061727 | GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. | 03-15-2012 |
20120068224 | METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER - A method of producing a semiconductor wafer suited to form types of devices such as HBT and FET on a single semiconductor wafer is provided. The method, by repeating steps including introducing, into a reaction chamber for forming a semiconductor by crystal growth, a first-impurity gas containing an element or a compound containing a first impurity atom as a constituent, thereby producing semiconductor wafers, includes, after introducing the first-impurity gas: taking out a produced semiconductor wafer; disposing a first semiconductor in the reaction chamber; introducing, into the reaction chamber, a second-impurity gas containing an element or a compound containing, as a constituent, a second impurity atom exhibiting a conduction type opposite to the conduction type of the first impurity atom within the first semiconductor; heating the first semiconductor in an atmosphere of the second-impurity gas; and forming a second semiconductor on the heated first semiconductor by crystal growth. | 03-22-2012 |
20120119258 | VERTICAL OUTGASSING CHANNELS - InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H | 05-17-2012 |
20120175675 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed. | 07-12-2012 |
20120248500 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device in which contact resistance between an ohmic electrode and an ohmic recess portion is reduced and a method of manufacturing the nitride semiconductor device are provided. The nitride semiconductor device includes: a first nitride semiconductor layer formed on a substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than a bandgap of the first nitride semiconductor layer; an ohmic recess portion formed in at least the second nitride semiconductor layer; and an ohmic electrode provided in contact with the ohmic recess portion. The ohmic recess portion includes a corrugated structure in at least a part of a plane in contact with the ohmic electrode. | 10-04-2012 |
20120280273 | METHODS AND SUBSTRATES FOR LASER ANNEALING - Methods and substrates for laser annealing are disclosed. The substrate includes a target region to be annealed and a plurality of reflective interfaces. The reflective interfaces cause energy received by the substrate to resonate within the target region. The method includes emitting energy toward the substrate with a laser, receiving the energy with the substrate, and reflecting the received energy with a plurality of reflective interfaces embedded in the substrate to generate a resonance within the target region. | 11-08-2012 |
20120280274 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is provided, comprising: a Si substrate; a porous structure layer formed on the Si substrate, in which the porous structure layer has a flat surface and comprises a Si | 11-08-2012 |
20120280275 | SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER - Provided is a semiconductor wafer including: a base wafer whose surface is made of a silicon crystal: a Si | 11-08-2012 |
20120299057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling. | 11-29-2012 |
20120305986 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a wafer; a plurality of convex structures formed on the wafer, in which every two adjacent convex structures are separated by a cavity in a predetermined pattern and arranged in an array, and the cavity between every two adjacent convex structures is less than 50 nm in width; and a first semiconductor film formed on the plurality of convex structures, in which a part of the first semiconductor film is spaced apart from the wafer. | 12-06-2012 |
20120326209 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - To provide a semiconductor device including a functional laminate having flatness and crystallinity improved by effectively passing on the crystallinity and flatness improved in a buffer to the functional laminate, and to provide a method of producing the semiconductor device; in the semiconductor device including the buffer and the functional laminate having a plurality of nitride semiconductor layers, the functional laminate includes a first n-type or i-type Al | 12-27-2012 |
20130001641 | Defect Mitigation Structures For Semiconductor Devices - A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer. The substrate intermediate layer and the device intermediate layer comprise a distribution in their compositions along a thickness coordinate. | 01-03-2013 |
20130001642 | METHOD INCLUDING PRODUCING A MONOCRYSTALLINE LAYER - A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion. | 01-03-2013 |
20130020611 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A STRUCTURE IN A TARGET SUBSTRATE FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming a structure in a target substrate for manufacturing a semiconductor device is provided. The method comprises the step of providing a masking layer on the target substrate and providing a stair-like profile in the masking layer such that the height of a step of the stair-like profile is smaller than the thickness of the masking layer. Further, the method comprises the step of performing anisotropic etching of the masking layer and the target substrate simultaneously such that a structure having a stair-like profile is formed in the target substrate. The semiconductor device comprises a target substrate including a first region made of a first type of semiconductor material and a second region made of a second type of semiconductor material. | 01-24-2013 |
20130032856 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a semiconductor apparatus includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; and a third semiconductor layer of the first conductivity type, wherein: the second semiconductor layer is formed between the first and third semiconductor layers, and the first and second semiconductor layers are in contact with each other; and a first energy level at a bottom edge of a conduction band of the first semiconductor layer is lower than a second energy level at a top edge of a valence band of the second semiconductor layer, and the second energy level at the top edge of the valence band of the second semiconductor layer is substantially the same as a third energy level at a bottom edge of a conduction band of the third semiconductor layer. | 02-07-2013 |
20130032857 | Silicon-Germanium Hydrides and Methods for Making and Using Same - The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds. | 02-07-2013 |
20130056793 | PROVIDING GROUP V AND GROUP VI OVER PRESSURE FOR THERMAL TREATMENT OF COMPOUND SEMICONDUCTOR THIN FILMS - Embodiments of the invention provide methods for forming high quality, low resistivity Group III-V or Group II-VI compounds. In one embodiment, the method includes growing a compound semiconductor layer having a n-type or p-type dopant over a substrate, the compound semiconductor layer comprising at least a first component and a second component, and the second component has a vapor pressure relatively higher than the first component, forming a supplemental layer consisted essentially of the second component at or near an upper surface of the compound semiconductor layer, and anneal the substrate. A capping layer may be formed on the supplemental layer to help prevent loss of crystallinity of the second component at elevated temperatures. An overpressure of the second component gas may be provided onto an exposed surface of the substrate during annealing to enhance the surface morphology of the compound semiconductor layer. | 03-07-2013 |
20130069110 | LOW RESISTIVITY CONTACT - Embodiments of a low resistivity contact to a semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a semiconductor layer, a semiconductor contact layer having a low bandgap on a surface of the semiconductor layer, and an electrode on a surface of the semiconductor contact layer opposite the semiconductor layer. The bandgap of the semiconductor contact layer is in a range of and including 0 to 0.2 electron-volts (eV), more preferably in a range of and including 0 to 0.1 eV, even more preferably in a range of and including 0 to 0.05 eV. Preferably, the semiconductor layer is p-type. In one particular embodiment, the semiconductor contact layer and the electrode form an ohmic contact to the p-type semiconductor layer and, as a result of the low bandgap of the semiconductor contact layer, the ohmic contact has a resistivity that is less than 1×10 | 03-21-2013 |
20130082303 | HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base substrate. Because of this difference in thicknesses, each sacrificial material layer etches at different rates, with thicker sacrificial material layers etching faster than thinner sacrificial material layers. An etch is performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially. | 04-04-2013 |
20130105858 | PROCESS FOR PRODUCING Si(1-v-w-x)CwAlxNv BASE MATERIAL, PROCESS FOR PRODUCING EPITAXIAL WAFER, Si(1-v-w-x)CwAlxNv BASE MATERIAL, AND EPITAXIAL WAFER | 05-02-2013 |
20130134480 | Formation of Devices by Epitaxial Layer Overgrowth - Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer. | 05-30-2013 |
20130153960 | Anti-Fuses on Semiconductor Fins - A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse. | 06-20-2013 |
20130153961 | IN-SITU PRE-CLEAN PRIOR TO EPITAXY - Methods for low temperature cleaning of a semiconductor surface prior to in-situ deposition have high throughput and consume very little of the thermal budget. GeH | 06-20-2013 |
20130193480 | Epitaxy Technique for Reducing Threading Dislocations in Stressed Semiconductor Compounds - A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers. | 08-01-2013 |
20130200429 | EPITAXY LEVEL PACKAGING - A method of growth and transfer of epitaxial structures from semiconductor crystalline substrate(s) to an assembly substrate. Using this method, the assembly substrate encloses one or more semiconductor materials and defines a wafer size that is equal to or larger than the semiconductor crystalline substrate for further wafer processing. The process also provides a unique platform for heterogeneous integration of diverse material systems and device technologies onto one single substrate. | 08-08-2013 |
20130200430 | ELECTRONIC DEVICE WITH MIRCOFILM ANTENNA AND RELATED METHODS - An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and the electrically conductive feed line, a second substrate on the insulating layer, and an antenna on the second substrate and having nanofilm layers stacked on the second substrate. The antenna is coupled to the feed line through an aperture. | 08-08-2013 |
20130200431 | Selective Area Growth of Germanium and Silicon-Germanium in Silicon Waveguides for On-chip Optical Interconnect Applications - A robust fabrication process for selective area growth of semiconductors in growth windows is provided. Sidewall growth is eliminated by the presence of a spacer layer which covers the sidewalls. Undesirable exposure of the top corners of the growth windows is prevented by undercutting the growth window prior to deposition of the dielectric spacer layer. The effectiveness of this process has been demonstrated by selective-area growth of Ge and Ge/SiGe quantum wells on a silicon substrate. Integration of active optoelectronic devices with waveguide layers via end-coupling through the dielectric spacer layer can be reliably accomplished in this manner. | 08-08-2013 |
20130200432 | SEMICONDUCTOR COMPONENT, SUBSTRATE AND METHOD FOR PRODUCING A SEMICONDUCTOR LAYER SEQUENCE - A semiconductor component includes a semiconductor body based on a nitride compound semiconductor material, and a substrate on which the semiconductor body is arranged, wherein impurities are formed in the substrate in a targeted manner. | 08-08-2013 |
20130270606 | Semiconductor Device with Integrated Breakdown Protection - A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path. | 10-17-2013 |
20140001513 | LAYER SYSTEM OF A SILICON-BASED SUPPORT AND A HETEROSTRUCTURE APPLIED DIRECTLY ONTO THE SUPPORT | 01-02-2014 |
20140084338 | SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain. | 03-27-2014 |
20140084339 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes as compound semiconductor layers: a first layer; a second layer larger in band gap than the first layer, formed above the first layer; a third layer having a p-type conductivity type, formed above the second layer; a gate electrode formed above the second layer via the third layer; a fourth layer larger in band gap than the second layer, formed to be in contact with the third layer above the second layer; and a fifth layer smaller in band gap than the fourth layer, formed to be in contact with the third layer above the fourth layer. | 03-27-2014 |
20140110753 | Methods of Making JFET Devices with Pin Gate Stacks - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET. | 04-24-2014 |
20140131768 | BRIDGE STRUCTURE - A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block. | 05-15-2014 |
20140159111 | SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film. | 06-12-2014 |
20140175509 | Lattice Mismatched Hetero-Epitaxial Film - An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein. | 06-26-2014 |
20140209974 | Double Stepped Semiconductor Substrate - A method for forming a double step surface on a semiconductor substrate includes, with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a rough surface on a region of a semiconductor substrate. The method further includes, with an annealing process used in the MOCVD process, forming double stepped surface on the region of the semiconductor substrate. | 07-31-2014 |
20140217467 | METHODS OF FORMING SUBSTRATES COMPRISED OF DIFFERENT SEMICONDUCTOR MATERIALS AND THE RESULTING DEVICE - Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer. | 08-07-2014 |
20140231870 | SEMICONDUCTOR STRUCTURE HAVING SILICON DEVICES, COLUMN III-NITRIDE DEVICES, AND COLUMN III-NON-NITRIDE OR COLUMN II-VI DEVICES - A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate. | 08-21-2014 |
20140264436 | SOLUTION PROCESSED NEUTRON DETECTOR - A low-cost neutron detector is formed on a substrate includes a sensor formed by an active material layer sandwiched between two electrodes, and a neutron capture layer formed in close proximity to (i.e., over and/or under) the sensor. The sensor active material layer includes a bulk heterojunction or bilayer structure that is formed by depositing particulate solutions incorporating at least one type of high atomic number nanoparticle using low-temperature (i.e., below 400° C.) solution processing techniques. The sensor electrode material and neutron capture material are similarly disposed in associated solutions (e.g., conductive inks) that are also deposited using low-temperature solution processing techniques, whereby the fabrication process can be carried out on low-cost flexible substrate material (e.g., PET) using high efficiency roll-to-roll production techniques. The neutron capture material is optionally patterned as an array of pillars, and the active layer materials are backfilled between the pillars. | 09-18-2014 |
20140306268 | METHOD FOR OBTAINING A HETEROGENEOUS SUBSTRATE FOR THE PRODUCTION OF SEMICONDUCTORS, AND CORRESPONDING SUBSTRATE - A method for obtaining a heterogeneous substrate intended for use in the production of a semiconductor comprises the following steps: (a) obtaining a first substrate ( | 10-16-2014 |
20150137178 | METAL-SEMICONDUCTOR-METAL (MSM) HETEROJUNCTION DIODE - In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer. | 05-21-2015 |
20160035826 | SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD - A method for manufacturing a semiconductor device may include forming a semiconductor portion, forming a doped portion, and forming a dielectric member. A side of the dielectric member abuts each of the semiconductor portion and the doped portion. A first half of the doped portion is positioned between the semiconductor portion and a second half of the doped portion. A dopant concentration of the second half of the doped portion is greater than a dopant concentration of the first half of the doped portion. | 02-04-2016 |
20160035837 | FREQUENCY MULTIPLIER BASED ON A LOW DIMENSIONAL SEMICONDUCTOR STRUCTURE - A frequency multiplier based on a low dimensional semiconductor structure, including an insulating substrate layer, a semiconductor conducting layer arranged on the surface of the insulating substrate layer, an insulating protective layer arranged on the surface of the semiconductor conducting layer, an insulating carving groove penetrating the semiconductor conducting layer, an inlet electrode arranged on the side surface of the semiconductor conducting layer, and an outlet electrode arranged on the side surface corresponding to the access electrode is provided. The semiconductor conducting layer comprises two two-dimensional, quasi-one-dimensional, or one-dimensional current carrying channels near to and parallel to each other. The frequency multiplier has advantages that the structure is simple, the process is easy to implement, no extra filter circuit needs to be added, dependence on material characteristics is little, and the selection range of materials is wide. | 02-04-2016 |
20160056244 | NANOSTRUCTURES AND NANOFEATURES WITH Si (111) PLANES ON Si (100) WAFERS FOR III-N EPITAXY - A fin over an insulating layer on a substrate having a first crystal orientation is modified to form a surface aligned along a second crystal orientation. A device layer is deposited over the surface of the fin aligned along the second crystal orientation. | 02-25-2016 |
20160133709 | MONOLITHIC INTEGRATED SEMICONDUCTOR STRUCTURE - A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition B | 05-12-2016 |
20160380147 | EPITAXIAL STRUCTURE AND METHOD FOR MAKING THE SAME - An epitaxial structure and a method for making the same are provided. The epitaxial structure includes a substrate, an epitaxial layer and a carbon nanotube layer. The epitaxial layer is located on the substrate. The carbon nanotube layer is located in the epitaxial layer. The method includes following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. An epitaxial layer is epitaxially grown from the epitaxial growth surface to enclose the carbon nanotube layer therein. | 12-29-2016 |
20220140108 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; an intermediate layer disposed on the second nitride semiconductor layer; and a conductive structure disposed on the intermediate layer, wherein a first even interface is formed between the intermediate layer and the second nitride semiconductor layer. | 05-05-2022 |
20220140126 | GROUP III-V SEMICONDUCTOR STRUCTURES HAVING CRYSTALLINE REGROWTH LAYERS AND METHODS FOR FORMING SUCH STRUCTURES - A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer. | 05-05-2022 |