| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257200000 | Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI)) | 51 |
| 20080251814 | HETERO-BONDED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH AN UNPINNING DIELECTRIC LAYER - A hetero-bonded SOI substrate comprises a stack of a semiconductor handle substrate, an isolation insulator layer, a depinning dielectric layer, and a top non-silicon semiconductor layer. The depinning layer abuts both the top non-silicon semiconductor layer and the isolation insulator layer and relaxes Fermi level pinning in the top non-silicon semiconductor layer. The top non-silicon semiconductor layer may be a III-V compound semiconductor layer such as GaAs and the depinning dielectric layer may be a (Gd | 10-16-2008 |
| 20080296625 | Gallium nitride-on-silicon multilayered interface - A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the range of about 300 to 800° C., and the first layer of a second film is formed in compression overlying the first layer of the first film. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, a first GaN layer is grown overlying the first layer of second film. Then, the above-mentioned processes are repeated: forming a second layer of first film; heating the substrate to a temperature in the range of about 300 to 800° C.; forming a second layer of second film in compression; and, growing a second GaN layer using the LNEO process. | 12-04-2008 |
| 20080296626 | NITRIDE SUBSTRATES, THIN FILMS, HETEROSTRUCTURES AND DEVICES FOR ENHANCED PERFORMANCE, AND METHODS OF MAKING THE SAME - The present invention provides nitride semiconductors having a moderate density of basal plane stacking faults and a reduced density of threading dislocations, various products based on, incorporating or comprising the nitride semiconductors, including without limitation substrates, template films, templates, heterostructures with or without integrated substrates, and devices, and methods for fabrication of templates and substrates comprising the nitride semiconductors. | 12-04-2008 |
| 20080296627 | Nitride semiconductor device and method of manufacturing the same - In the nitride semiconductor device using the silicon substrate, the metal electrode formed on the silicon substrate has both ohmic contact property and adhesion, so that the nitride semiconductor device having excellent electric properties and reliability is obtained. The nitride semiconductor device includes a silicon substrate ( | 12-04-2008 |
| 20080308845 | Heterogeneous Group IV Semiconductor Substrates - Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized. | 12-18-2008 |
| 20090001424 | III-nitride power device - A III-nitride power device that includes a Schottky electrode surrounding one of the power electrodes of the device. | 01-01-2009 |
| 20090014756 | Method of producing large area SiC substrates - A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides an alternative to expensive SiC wafers for growing semiconductor crystals. | 01-15-2009 |
| 20090189192 | DEPOSITION OF GROUP III-NITRIDES ON Ge - The present invention provides a method for depositing or growing a group III-nitride layer, e.g. GaN layer ( | 07-30-2009 |
| 20090302352 | P-N Junction for Use as an RF Mixer from GHZ to THZ Frequencies - This disclosure describes a semiconductor device that can be used as a mixer at RF frequencies extending from a few tens of GHz into the THz frequency range. The device is composed of narrow bandgap semiconductors grown by solid source molecular beam epitaxy. The device can comprise a GaSb substrate, a AlSb layer on the GaSb substrate, a In | 12-10-2009 |
| 20090302353 | STRUCTURES CONTAINING ELECTRODEPOSITED GERMANIUM AND METHODS FOR THEIR FABRICATION - Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits. | 12-10-2009 |
| 20100032718 | III-Nitride Based Semiconductor Structure with Multiple Conductive Tunneling Layer - A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer. | 02-11-2010 |
| 20100163931 | GROUP III-V NITRIDE LAYER AND METHOD FOR PRODUCING THE SAME - There is disclosed a hexagonal Group III-V nitride layer exhibiting high quality crystallinity capable of improving the properties of a semiconductor device such as a light emitting element. This nitride layer is a Group III-V nitride layer belonging to hexagonal crystal formed by growth on a substrate having a different lattice constant, which has a growth-plane orientation of {1-100} and in which a full width at half maximum b | 07-01-2010 |
| 20100187572 | SUSPENDED MONO-CRYSTALLINE STRUCTURE AND METHOD OF FABRICATION FROM A HETEROEPITAXIAL LAYER - Methods of fabricating a suspended mono-crystalline structure use annealing to induce surface migration and cause a surface transformation to produce the suspended mono-crystalline structure above a cavity from a heteroepitaxial layer provided on a crystalline substrate. The methods include forming a three dimensional (3-D) structure in the heteroepitaxial layer where the 3-D structure includes high aspect ratio elements. The 3-D structure is annealed at a temperature below a melting point of the heteroepitaxial layer. The suspended mono-crystalline structure may be a portion of a semiconductor-on-nothing (SON) substrate. | 07-29-2010 |
| 20100193842 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device | 08-05-2010 |
| 20100308376 | SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times. | 12-09-2010 |
| 20110001167 | REDUCED DEFECT SEMICONDUCTOR-ON-INSULATOR HETERO-STRUCTURES - A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor-on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on-insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed. | 01-06-2011 |
| 20110073913 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES ON A GROUP IV SUBSTRATE WITH CONTROLLED INTERFACE PROPERTIES AND DIFFUSION TAILS - Electronic and opto-electronic devices having epitaxially-deposited III/V compounds on vicinal group IV substrates and method for making same. The devices include an AlAs nucleating layer on a Ge substrate. The group IV substrate contains a p-n junction whose change of characteristics during epitaxial growth of As-containing layers is minimized by the AlAs nucleating layer. The AlAs nucleating layer provides improved morphology of the devices and a means to control the position of a p-n junction near the surface of the group IV substrate through diffusion of As and/or P and near the bottom of the III/V structure through minimized diffusion of the group IV element. | 03-31-2011 |
| 20110084310 | METHOD FOR OBTAINING A STRUCTURED MATERIAL WITH THROUGH OPENINGS, IN PARTICULAR NITRIDES OF TYPE III SEMICONDUCTORS STRUCTURED ACCORDING TO PHOTONIC CRYSTAL PATTERNS - A method of manufacture of a optical, photonic or optoelectronic component, including a so-called photonic slab or membrane that is traversed, in at least one internal region and according to a predetermined pattern, by a plurality of through openings having a micrometric or sub-micrometric transverse dimension, the method having the following steps: structuring of the surface of a substrate by an etching that produces holes in the substrate according to the pattern; depositing at least one layer of the photonic material forming the slab or membrane, by anisotropic epitaxial growth on the structured surface of the substrate around the opening of the holes. | 04-14-2011 |
| 20110140176 | Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 06-16-2011 |
| 20110233616 | GERMANIUM BASED METAL-INSULATOR TRANSITION THIN FILM, METAL-INSULATOR TRANSITION DEVICE INCLUDING THE METAL-INSULATOR TRANSITION THIN FILM, AND METHOD OF FABRICATING THE METAL-INSULATOR TRANSITION DEVICE - Provided are a germanium (Ge) based metal-insulator transition (MIT) thin film which is formed of a Ge single-element material instead of a compound material of two or more elements and by which material growth may be easily performed and a problem of a second phase characteristic in accordance with a structural defect and an included impurity may be solved, an MIT device including the MIT thin film, and a method of fabricating the MIT device. The MIT device includes a substrate; a germanium (Ge) based MIT thin film which is formed of a Ge single-element material on the substrate and in which a discontinuous MIT occurs at a predetermined transition voltage; and at least two thin film electrodes contacting the Ge based MIT thin film, wherein the discontinuous MIT occurs in the Ge based MIT thin film due to a voltage or a current which is applied through the thin film electrodes. | 09-29-2011 |
| 20110316051 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, AND METHOD OF PRODUCING ELECTRONIC DEVICE - The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed. | 12-29-2011 |
| 20120032234 | Antiphase Domain Boundary-Free III-V Compound Semiconductor Material on Semiconductor Substrate and Method for Manufacturing Thereof - Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface. The method further comprises at least partially filling the recessed region with a III-V compound semiconductor material overlaying the surface. | 02-09-2012 |
| 20120168823 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device and a method for forming the same. The method comprises: providing a first semiconductor layer and forming a first STI in the first semiconductor layer; determining a selected region in the first semiconductor layer, and making a portion of the first semiconductor layer in the selected region recessed; and in the selected region, epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer. According to the present invention, a structure with a second semiconductor layer selectively epitaxially grown and embedded in the first semiconductor layer can be formed by a simple process, and defects generated during the epitaxial growth process can be further reduced. | 07-05-2012 |
| 20120211803 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD WITH IMPROVED EPITAXIAL QUALITY OF III-V COMPOUND ON SILICON SURFACES - Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing. | 08-23-2012 |
| 20120217548 | THIN-FILM HETEROSTRUCTURE THERMOELECTRICS IN A GROUP IIA AND IV-VI MATERIALS SYSTEM - Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure. | 08-30-2012 |
| 20120261721 | SEMICONDUCTOR STRUCTURES HAVING NUCLEATION LAYER TO PREVENT INTERFACIAL CHARGE FOR COLUMN III-V MATERIALS ON COLUMN IV OR COLUMN IV-IV MATERIALS - A semiconductor structure having: a column IV material or column IV-IV material; a nucleation layer of AlN layer or a column III nitride having more than 60% aluminum content on a surface of the column IV material or column IV-IV material and a layer of column III-V material over the nucleation layer, where the nucleation layer and the layer of column III-V material over the nucleation layer have different crystallographic structures. In one embodiment, the column III-V nucleation layer is a nitride and the column III-V material of the over the nucleation layer is a non-nitride such as, for example, an arsenide (e.g., GaAs), a phosphide (e.g., InP), or an antimonide (e.g. InSb), or alloys thereof. | 10-18-2012 |
| 20120267688 | SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER - To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed. | 10-25-2012 |
| 20120273840 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed. | 11-01-2012 |
| 20120305992 | HYBRID MONOLITHIC INTEGRATION - The present invention describes a hybrid integrated circuit comprising both CMOS and III-V devices, monolithically integrated in a single chip. It allows the almost complete elimination of the contamination issues related to the integration of different technologies, maintaining at the same time a good planarization of the structure. It further simplifies the fabrication process, allowing the growth of high quality III-V materials on (100) silicon substrates lowering the manufacturing cost. Moreover, differently from many prior art attempts, it does not require silicon on insulator technologies and/or other expensive process steps. This invention enables the consolidation on the same integrated circuit of a hybrid switching power converter that takes advantage of the established circuit topologies of CMOS circuitries and of the higher mobility and voltage withstanding of III-V HEMT devices. | 12-06-2012 |
| 20120319171 | SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND A METHOD OF PRODUCING A SEMICONDUCTOR WAFER - A semiconductor wafer includes a base wafer, a first crystal layer, a second crystal layer and a third crystal layer. The first crystal layer has a first surface having a same orientation as the base wafer, and a second surface having a different orientation from the first surface, the second crystal layer has a third surface having the same orientation as the first surface, and a fourth surface having the same orientation as the second surface, the third crystal layer is in contact with a part of the third surface and the fourth surface. A thickness ratio of the second crystal layer in a region adjoining the first surface to a region adjoining the second surface is larger than a thickness ratio of the third crystal layer in a region adjoining the third surface to a region adjoining the fourth surface. | 12-20-2012 |
| 20120326212 | HIGH k GATE STACK ON III-V COMPOUND SEMICONDUCTORS - A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AO | 12-27-2012 |
| 20130015502 | STRUCTURE AND METHOD FOR FORMING A LIGHT DETECTING DIODE AND A LIGHT EMITTING DIODE ON A SILICON-ON-INSULATOR WAFER BACKSIDEAANM Fox; Benjamin A.AACI RochesterAAST MNAACO USAAGP Fox; Benjamin A. Rochester MN USAANM Gibbs; Nathaniel J.AACI Iowa CityAAST IAAACO USAAGP Gibbs; Nathaniel J. Iowa City IA USAANM Maki; Andrew B.AACI RochesterAAST MNAACO USAAGP Maki; Andrew B. Rochester MN USAANM Onsongo; David M.AACI AustinAAST TXAACO USAAGP Onsongo; David M. Austin TX USAANM Timpane; Trevor J.AACI RochesterAAST MNAACO USAAGP Timpane; Trevor J. Rochester MN US - A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes. | 01-17-2013 |
| 20130015503 | MONOLITHIC INTEGRATED SEMICONDUCTOR STRUCTURE - A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition B | 01-17-2013 |
| 20130119437 | SEMICONDUCTOR DEVICE - A semiconductor device having small leakage current and high breakdown voltage during reverse blocking, small on-state resistance and large output current at forward conduction, short reverse recovery time at shutoff, and high peak surge current value is provided. An n-type layer is made of a group-III nitride, and a p-type layer is made of a group-IV semiconductor material having a smaller band gap than the group-III nitride. The energy level at the top of the valence band of the n-type layer is lower than the energy level at the top of the valence band of the p-type layer, so that a P-N junction semiconductor device satisfying the above requirements is obtained. Further, a combined structure of P-N junction and Schottky junction by additionally providing an anode electrode to be in Schottky contact with the n-type layer also achieves the effect of decreasing voltage at the rising edge of current resulting from the Schottky junction. | 05-16-2013 |
| 20130126946 | III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate - A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask. | 05-23-2013 |
| 20130161699 | SEMICONDUCTOR STRUCTURES HAVING NUCLEATION LAYER TO PREVENT INTERFACIAL CHARGE FOR COLUMN III-V MATERIALS ON COLUMN IV OR COLUMN IV-IV MATERIALS - A semiconductor structure having: a column IV material or column IV-IV material; a nucleation layer of AlN layer or a column HI nitride having more than 60% aluminum content on a surface of the column IV material or column INT-IV material and a layer of column III-V material over the nucleation layer, where the nucleation layer and the layer of column III-V material over the nucleation layer have different crystallographic structures. In one embodiment, the columnffl V nucleation layer is a nitride and the column III-V material of the over the nucleation layer is a non-nitride such as, for example, an arsenide (e.g., GaAs), a phosphide (e.g, InP) or an antimonide (e.g. InSb), or alloys thereof. | 06-27-2013 |
| 20130214331 | METHOD FOR TREATING A SUBSTRATE AND A SUBSTRATE - A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET. | 08-22-2013 |
| 20130256759 | Fin Structure for a FinFET Device - A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin. | 10-03-2013 |
| 20130256760 | METHOD FOR FORMING GROUP III/V CONFORMAL LAYERS ON SILICON SUBSTRATES - A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions. | 10-03-2013 |
| 20130270608 | HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS - Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed. | 10-17-2013 |
| 20130320404 | GALLIUM NITRIDE TO SILICON DIRECT WAFER BONDING - A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs. | 12-05-2013 |
| 20130334574 | Monolithic Integrated Composite Group III-V and Group IV Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 12-19-2013 |
| 20140035005 | Monolithic Integrated Group III-V and Group IV Device - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT). | 02-06-2014 |
| 20140183601 | METHOD FOR TRANSFERRING A LAYER OF A SEMICONDUCTOR AND SUBSTRATE COMPRISING A CONFINEMENT STRUCTURE - A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that is distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into the donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer. | 07-03-2014 |
| 20140361345 | NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR WAFER - A nitride semiconductor wafer includes a silicon substrate, a first layer, a second layer, a third layer, a fourth layer, a fifth layer, and a sixth layer. The first layer is provided on the silicon substrate. The second layer is provided on the first layer. The third layer is provided on the second layer. The fourth layer is provided on the third layer. The fifth layer is provided on the fourth layer. The sixth layer is provided on the fifth layer. A composition ratio x4 of the fourth layer decreases in a first direction from the third layer toward the fifth layer. A maximum value of the composition ratio x4 is not more than a composition ratio of the third layer. A minimum value of the composition ratio x4 is not less than a composition ratio of the fifth layer. | 12-11-2014 |
| 20150048422 | A METHOD FOR FORMING A CRYSTALLINE COMPOUND III-V MATERIAL ON A SINGLE ELEMENT SUBSTRATE - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. | 02-19-2015 |
| 20150048423 | SEMICONDUCTOR DEVICE HAVING A III-V CRYSTALLINE COMPOUND MATERIAL SELECTIVELY GROWN ON THE BOTTOM OF A SPACE FORMED IN A SINGLE ELEMENT SUBSTRATE. - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. | 02-19-2015 |
| 20150054037 | SEMICONDUCTOR GALLIUM ARSENIDE COMPATIBLE EPITAXIAL FERROELECTRIC DEVICES FOR MICROWAVE TUNABLE APPLICATION - The presently claimed invention provides a barium strontium titanate/strontium titanate/gallium arsenide (BST/STO/GaAs) heterostructure comprising a gallium arsenide (GaAs) substrate, at least one strontium titanate (STO) layer, and at least one barium strontium titanate (BST) layer. The BST/STO/GaAs heterostructure of the present invention has a good temperature stability, high dielectric constant and low dielectric loss, which enable to fabricate tunable ferroelectric devices. A method for fabricating the BST/STO/GaAs heterostructure is also disclosed in the present invention, which comprises formation of at least one STO layer on the GaAs substrate by a first laser molecular beam epitaxial system, and formation of at least one BST layer on the STO layer by a second laser molecular beam epitaxial system. | 02-26-2015 |
| 20150333129 | Double Stepped Semiconductor Substrate - A method for forming a double step surface on a semiconductor substrate includes, with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a rough surface on a region of a semiconductor substrate. The method further includes, with an annealing process used in the MOCVD process, forming double stepped surface on the region of the semiconductor substrate. | 11-19-2015 |
| 20160141374 | ASPECT RATIO TRAPPING AND LATTICE ENGINEERING FOR III/V SEMICONDUCTORS - A method of forming a semiconductor structure. The method may include; forming a hardmask on a strained semiconductor, the strained semiconductor is on a substrate; relaxing edges of the strained semiconductor by forming first trenches through the hardmask and through the strained semiconductor; forming barrier layers in the first trenches; forming a second trench between adjacent barrier layers; and growing a second semiconductor layer on the strained semiconductor having relaxed edges. | 05-19-2016 |
| 20160172415 | IMAGE SENSOR AND METHOD FOR MANUFACTURING SAME | 06-16-2016 |
