| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257191000 | Having graded composition | 26 |
| 20080308843 | FIELD EFFECT TRANSISTOR HAVING A COMPOSITIONALLY GRADED LAYER - A GaN heterojunction FET has an Al | 12-18-2008 |
| 20100200894 | HETERO JUNCTION BIPOLAR TRANSISTOR - An energy level Ec in a vicinity of an interface between a graded layer | 08-12-2010 |
| 20110018031 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material. | 01-27-2011 |
| 20110079821 | Integrated Devices on a Common Compound Semiconductor III-V Wafer - A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs. | 04-07-2011 |
| 20120007144 | Compound Semiconductor Device and Method of Producing the Same - A semiconductor device comprises an Si substrate 10 and a compound layer | 01-12-2012 |
| 20120018779 | METHOD FOR PRODUCING MICROMECHANICAL PATTERNS HAVING A RELIEF-LIKE SIDEWALL OUTLINE SHAPE OR AN ADJUSTABLE ANGLE OF INCLINATION - A method for producing micromechanical patterns having a relief-like sidewall outline shape or an angle of inclination that is able to be set, the micromechanical patterns being etched out of a SiGe mixed semiconductor layer that is present on or deposited on a silicon semiconductor substrate, by dry chemical etching of the SiGe mixed semiconductor layer; the sidewall outline shape of the micromechanical pattern being developed by varying the germanium proportion in the SiGe mixed semiconductor layer that is to be etched; a greater germanium proportion being present in regions that are to be etched more strongly; the variation in the germanium proportion in the SiGe mixed semiconductor layer being set by a method selected from the group including depositing a SiGe mixed semiconductor layer having varying germanium content, introducing germanium into a silicon semiconductor layer or a SiGe mixed semiconductor layer, introducing silicon into a germanium layer or an SiGe mixed semiconductor layer and/or by thermal oxidation of a SiGe mixed semiconductor layer. | 01-26-2012 |
| 20120037957 | SEMICONDUCTOR DEVICES GROWN ON INDIUM-CONTAINING SUBSTRATES UTILIZING INDIUM DEPLETION MECHANISMS - We have observed anomalous behavior of II-VI semiconductor devices grown on certain semiconductor substrates, and have determined that the anomalous behavior is likely the result of indium atoms from the substrate migrating into the II-V layers during growth. The indium can thus become an unintended dopant in one or more of the II-VI layers grown on the substrate, particularly layers that are close to the growth substrate, and can detrimentally impact device performance. We describe a variety of semiconductor constructions and techniques effective to deplete the migrating indium within a short distance in the growth layers, or to substantially prevent indium from migrating out of the substrate, or to otherwise substantially isolate functional II-VI layers from the migrating indium, so as to maintain good device performance. | 02-16-2012 |
| 20120235208 | Semiconductor Mismatch Reduction - A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches. | 09-20-2012 |
| 20120280278 | Normally-Off High Electron Mobility Transistors - A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage. | 11-08-2012 |
| 20130015498 | Composite Semiconductor Device with Integrated Diode - There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a transition body formed over a diode, the transition body including more than one semiconductor layer. The composite semiconductor device also includes a transistor formed over the transition body. The diode may be connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two. | 01-17-2013 |
| 20130015499 | Composite Semiconductor Device with a SOI Substrate Having an Integrated Diode - There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a semiconductor on insulator (SOI) substrate including a diode and an insulator layer. The composite semiconductor device also includes a transition body formed over the diode, and a transistor formed over the transition body. The diode is connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two. | 01-17-2013 |
| 20130056795 | FinFET Design Controlling Channel Thickness - System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate. | 03-07-2013 |
| 20130140604 | SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed. | 06-06-2013 |
| 20130181256 | SEMICONDUCTOR DEVICES - In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction. | 07-18-2013 |
| 20130221406 | Ohmic Contact to Semiconductor - A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged. | 08-29-2013 |
| 20130256752 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an operation layer that is provided on a substrate and is made of a GaAs-based semiconductor; a first AlGaAs layer provided on the operation layer; a gate electrode provided on the first AlGaAs layer; an second AlGaAs layer having n-type conductivity and provided on the first AlGaAs layer of both sides of the gate electrode, an Al composition ratio of the second AlGaAs layer being larger than that of the first AlGaAs layer and being equal to or more than 0.3 and equal to or less than 0.5; an n-type GaAs layer selectively provided on the second AlGaAs layer; and a source electrode and a drain electrode that contain Au and are provided on the n-type GaAs layer. | 10-03-2013 |
| 20130313608 | SEMICONDUCTOR DEVICE - A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array. | 11-28-2013 |
| 20130334570 | INTEGRATED STRUCTURE OF COMPOUND SEMICONDUCTOR DEVICES - An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET. | 12-19-2013 |
| 20140070275 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and third and fourth semiconductor layers of the first conductivity type formed between the first and second semiconductor layer. The first, the third, the fourth, and the second semiconductor layers are coupled in this order. A band gap of the third semiconductor layer is narrower than that of the first semiconductor layer, and a band gap of the fourth semiconductor layer is narrower than that of the third semiconductor layer. | 03-13-2014 |
| 20140077263 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, an insulating film, an ohmic electrode, and a Schottky electrode. A surface region of the third nitride semiconductor layer between the ohmic electrode and the Schottky electrode contains an element heterogeneous with the constituent element of the third nitride semiconductor layer at a higher concentration than a region of the third nitride semiconductor layer of the second nitride semiconductor layer side. | 03-20-2014 |
| 20150380559 | Germanium-Containing FinFET and Methods for Forming the Same - A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin. A second recessing is performed to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing. The inter-diffusion region is then etched. | 12-31-2015 |
| 20160027877 | Source/Drain Structures and Methods of Forming Same - The present disclosure provides a semiconductor device including a gate stack disposed over a substrate, a source/drain (S/D) feature at least partially embedded within the substrate adjacent the gate stack. The S/D feature includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer. The second semiconductor material layer is different to the first semiconductor material layer. The S/D also includes a third semiconductor material layer disposed over the second semiconductor material layer, which includes a tin (Sn) material. | 01-28-2016 |
| 20160163856 | VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION - Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length. | 06-09-2016 |
| 20160172446 | MOSFET STRUCTURE AND MANUFACTURING METHOD THEREOF | 06-16-2016 |
| 20160172477 | METHODS TO ACHIEVE HIGH MOBILITY IN CLADDED III-V CHANNEL MATERIALS | 06-16-2016 |
| 20160190254 | Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. | 06-30-2016 |
