| Entries |
| Document | Title | Date |
|---|
| 20080203434 | Semiconductor Device with a Bipolar Transistor and Method of Manufacturing Such a Device - The invention relates to a semiconductor device ( | 08-28-2008 |
| 20080210977 | Semiconductor device having a support substrate partially having metal part extending across its thickness - A semiconductor device includes a support substrate and a semiconductor layer formed on the underlying substrate. The support substrate has its metal part formed by plating and extending across its entire thickness, whilst it has the other region made of semiconductor part. In particular, the region of the support substrate lying immediately below an active region is the metal part formed by plating. The region of the support substrate lying immediately below the region other than the active region is an inactive region made of semiconductor. The semiconductor device thus suppresses warping of a substrate otherwise caused by stress in the metal part formed by plating, and heat evolved due to the current in operation of the semiconductor device may be dissipated over the shortest path through the metal part having a higher thermal conductivity. | 09-04-2008 |
| 20080224174 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. | 09-18-2008 |
| 20080224175 | SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES - Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further includes a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body. | 09-18-2008 |
| 20080230807 | Semiconductor Device - A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device | 09-25-2008 |
| 20080230808 | HETEROJUNCTION BIPOLAR TRANSISTOR - A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side. | 09-25-2008 |
| 20080237642 | Method to Reduce Boron Penetration in a SiGe Bipolar Device - The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer. | 10-02-2008 |
| 20080265282 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 10-30-2008 |
| 20080265283 | Hetero-junction bipolar transistor - A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided. | 10-30-2008 |
| 20080296623 | BIPOLAR TRANSISTOR AND METHOD FOR MAKING SAME - A heterojunction bipolar transistor: The transistor may a collector layer, a base layer and an emitter layer. The transistor may include a dielectric material being disposed over the base layer. The base layer may be a SiGe base layer. | 12-04-2008 |
| 20080296624 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer. | 12-04-2008 |
| 20090039393 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed. Further, a second growing operation for selectively growing the second polycrystalline semiconductor layer and the third polycrystalline semiconductor layer on the exposed portion of the p-type polycrystalline semiconductor film exposed in the lower surface of the visor section without contacting the silicon nitride film, while growing the second semiconductor layer and the third semiconductor layer, so that the third semiconductor layer is in contact with the third polycrystalline semiconductor layer. | 02-12-2009 |
| 20090065811 | Semiconductor Device with OHMIC Contact and Method of Making the Same - A semiconductor device with ohmic contact is provided with a method of making the same. In one embodiment, a method is provided for fabricating a semiconductor device. The method comprises providing a semiconductor structure with a N-type doped semiconductor contact layer, forming a platinum contact portion over the N-type doped semiconductor contact layer, forming an adhesive contact portion over the platinum contact portion, forming a barrier contact portion over the adhesive contact portion, and forming a gold contact portion over the barrier contact portion. The method further comprises annealing the semiconductor structure to alloy the platinum contact portion with the N-type doped semiconductor contact layer to form a platinum/semiconductor alloyed diffusion contact barrier substantially disposed within the N-type doped semiconductor contact layer. | 03-12-2009 |
| 20090085066 | Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure - According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector in the high speed transistor region of the substrate. The method further includes forming a first high energy implant region in the high voltage transistor region of the substrate, where the first high energy implant region extends to a depth greater than a depth of a peak dopant concentration of the buried subcollector, thereby increasing a collector-to-emitter breakdown voltage of the high voltage transistor. The collector-to-emitter breakdown voltage of the high voltage transistor can be greater than approximately 5.0 volts. The high speed bipolar transistor can have a cutoff frequency of greater approximately 200.0 GHz. | 04-02-2009 |
| 20090108300 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 04-30-2009 |
| 20090127585 | Integration of an NPN device with phosphorus emitter and controlled emitter-base junction depth in a BiCMOS process - According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant. | 05-21-2009 |
| 20090140297 | SELF-ALIGNMENT SCHEME FOR A HETEROJUNCTION BIPOLAR TRANSISTOR - Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer. | 06-04-2009 |
| 20090173970 | METHOD OF FABRICATING HETERO-JUNCTION BIPOLAR TRANSISTOR (HBT) AND STRUCTURE THEREOF - A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>. | 07-09-2009 |
| 20090194792 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip. | 08-06-2009 |
| 20090200577 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE - The invention relates to a semiconductor device with a substrate ( | 08-13-2009 |
| 20090206370 | METHOD AND APPARATUS FOR FABRICATING A HETEROJUNCTION BIPOLAR TRANSISTOR - In one embodiment, the invention is a method and apparatus for fabricating a heterojunction bipolar transistor. One embodiment of a heterojunction bipolar transistor includes a collector layer, a base region formed over the collector layer, a self-aligned emitter formed on top of the base region and collector layer, a poly-germanium extrinsic base surrounding the emitter, and a metal germanide layer formed over the extrinsic base. | 08-20-2009 |
| 20090250724 | BIPOLAR TRANSISTOR AND METHOD OF MAKING SUCH A TRANSISTOR - A bipolar transistor is formed on a heavily doped silicon substrate ( | 10-08-2009 |
| 20090261385 | BIPOLAR TRANSISTOR WITH ENHANCED BASE TRANSPORT - A bipolar transistor includes a base layer design and a method for fabricating such a bipolar transistor that employ a built-in accelerating field focused on a base region adjacent to a collector, where minority carrier transport is otherwise retarded. The accelerating field of the base layer includes on average, a relatively low p-doping level in a first region proximate to the collector and a relatively high p-doping level in a second region proximate to an emitter. Alternatively, the accelerating field can be derived from band gap grading, wherein the grade of band gap in the first region is greater than the grade of band gap in the second region, and the average band gap of the first region is lower than that of the second region. | 10-22-2009 |
| 20090302351 | BIPOLAR TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - A bipolar transistor ( | 12-10-2009 |
| 20090321788 | DIELECTRIC LEDGE FOR HIGH FREQUENCY DEVICES - High frequency performance of (e.g., silicon) bipolar devices ( | 12-31-2009 |
| 20100001319 | Method for Making a Heterojunction Bipolar Transistor - The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat. | 01-07-2010 |
| 20100059793 | InP BASED HETEROJUNCTION BIPOLAR TRANSISTORS WITH EMITTER-UP AND EMITTER-DOWN PROFILES ON A COMMON WAFER - A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT. | 03-11-2010 |
| 20100072517 | Bipolar/dual FET structure including enhacement and depletion mode fets with isolated channels - According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET. | 03-25-2010 |
| 20100072518 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME - Methods of fabricating semiconductor devices using electrode-less wet-etching techniques to reduce defect densities on etched group III-nitride semiconductor surfaces are described herein. The methods generally involve contacting an etched surface of a component of a semiconductor device with a solution comprising a metal hydroxide and an oxidizing agent effective to reduce a roughness of the etched surface, wherein the etched surface is formed from a composition comprising a nitride of a group III element. Improved semiconductor devices are also disclosed. | 03-25-2010 |
| 20100109052 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer. | 05-06-2010 |
| 20100133586 | HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME - Provided are a heterojunction bipolar transistor and a method of forming the same. The method includes forming an emitter electrode on an emitter capping pattern, a base electrode on a base pattern, and a collector electrode on a subcollector pattern, the subcollector pattern, the base pattern, an emitter pattern, and the emitter capping pattern being provided to a substrate; patterning a protection insulation layer and a first dummy pattern covering the emitter electrode, the base electrode, and the collector electrode, to expose the emitter electrode, the base electrode, and the collector electrode; forming a second dummy pattern to electrically separate the emitter electrode, the base electrode, and the collector electrode; forming, on the substrate provided with the second dummy pattern, an emitter electrode interconnection connected to the emitter electrode, a base electrode interconnection connected to the base electrode, and a collector electrode interconnection connected to the collector electrode; and removing the first and second dummy patterns. | 06-03-2010 |
| 20100171151 | HETEROJUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - An HBT according to this invention includes: a sub-collector layer; a collector layer formed on the sub-collector layer and the base layer including a first collector layer, a second collector layer, a third collector layer, and a fourth collector layer. The first collector layer is formed on the sub-collector layer, and is made of semiconductor different from semiconductor of which the second to the fourth collector layers are made. The fourth collector layer is formed on the first collector layer, and has an impurity concentration lower than an impurity concentration of the second collector layer. The second collector layer is formed on the fourth collector layer, and has an impurity concentration lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer. The third collector layer is formed between the second collector layer and the base layer. | 07-08-2010 |
| 20100187571 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of the present invention is to provide a semiconductor resistive element having excellent linearity. A semiconductor device according to the present invention includes a HBT which is formed on a GaAs substrate and includes a group III-V compound semiconductor, and a semiconductor resistive element made of at least one layer included in a semiconductor epitaxial layer included in the HBT, and the semiconductor resistive element includes helium impurities. | 07-29-2010 |
| 20100237388 | HIGH ON-STATE BREAKDOWN HETEROJUNCTION BIPOLAR TRANSISTOR - A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage V | 09-23-2010 |
| 20100244099 | Double heterojunction bipolar transistor having graded base region - A semiconductor device comprises: a heterojunction, comprises a first region comprising a first III-V semiconductor; a second region adjacent to the first region and comprising a second III-V semiconductor material, wherein the second III-V semiconductor material comprises a material of graded concentration over a width of the second region; and a third region adjacent to the second region and comprising a third III-V semiconductor material, wherein the graded concentration is selection to provide substantially no conduction band discontinuity at a junction of the second region and the third region, or to provide a type I semiconductor junction at the junction of the second region and the third region. | 09-30-2010 |
| 20100283084 | BIPOLAR TRANSISTOR AND METHOD FOR FABRICATING THE SAME - The bipolar transistor includes a heterojunction intrinsic base layer epitaxially grown on a collector layer. The intrinsic base layer is disposed on the collector layer surrounded by an isolation layer, and an N-type impurity layer is formed in a surface portion of the collector layer. The impurity concentration of the N-type impurity layer is higher than the impurity concentration of the collector layer under the N-type impurity layer. Between the N-type impurity layer and the intrinsic base layer, an epitaxially grown layer is formed, where the epitaxially grown layer is lower in impurity concentration than the N-type impurity layer and the intrinsic base layer. | 11-11-2010 |
| 20100314664 | SILICIDED BASE STRUCTURE FOR HIGH FREQUENCY TRANSISTORS - High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. Emitter, base and collector regions are formed in or on a semiconductor substrate. The emitter contact has a portion that overhangs a portion of the extrinsic base contact, thereby forming a cave-like cavity between the overhanging portion of the emitter contact and the underlying regions of the extrinsic base contact. When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact closer to the base itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher f | 12-16-2010 |
| 20100314665 | HETERO-JUNCTION BIPOLAR TRANSISTOR - A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided. | 12-16-2010 |
| 20110012175 | SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be shaped as an island having a size that docs not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal dejects when the Ge layer is annealed at a certain temperature. | 01-20-2011 |
| 20110121364 | HETEROJUNCTION BIPOLAR TRANSISTOR - According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited and etched to define a base window over the buried collector drift region and overlapping the STI structures. The etching process is continued to selectively etch the buried collector drift region between the STI structures to form a base well. SiGeC may be selectively deposited to form epitaxial silicon-germanium in the base well in contact with the buried collector drift region and poly silicon-germanium on the side walls of the base well and base window. Spacers are then formed as well as an emitter. | 05-26-2011 |
| 20110121365 | HYBRID INTEGRATED CIRCUIT DEVICE, AND METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE - A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals. | 05-26-2011 |
| 20110133250 | MONOLITHIC MICROWAVE INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME - Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method include: forming an HBT on a substrate; forming a wiring of the HBT and a bottom electrode of a capacitor on the substrate, with a first metal, the bottom electrode being spaced apart from the HBT; forming a first insulation layer on the substrate to cover the HBT and the bottom electrode; and forming a top electrode of the capacitor on the first insulation layer and forming a resistance pattern on the substrate, with a second metal, the resistance pattern being spaced apart from the capacitor, wherein an edge of the top electrode is spaced apart from an edge of the bottom electrode. | 06-09-2011 |
| 20110140175 | MONOLITHIC MICROWAVE INTEGRATED CIRCUIT DEVICE AND METHOD OF FORMING THE SAME - Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method includes: forming an sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a Heterojunction Bipolar Transistor (HBT) region and a PIN diode region of a substrate; forming an emitter pattern and an emitter cap pattern in the HBT region and exposing the base layer by patterning the emitter layer and the emitter cap layer; and forming an intrinsic region by doping a portion of the collector layer of the PIN diode region with a first type impurity, the PIN diode region being spaced apart from the HBT region. | 06-16-2011 |
| 20110147799 | HIGH ON-STATE BREAKDOWN HETEROJUNCTION BIPOLAR TRANSISTOR - A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage V | 06-23-2011 |
| 20110198671 | GRINGO HETEROJUNCTION BIPOLAR TRANSISTOR WITH A METAL EXTRINSIC BASE REGION - The invention relates to a semiconductor device ( | 08-18-2011 |
| 20110241075 | BIPOLAR TRANSISTOR - A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [ | 10-06-2011 |
| 20110241076 | P-type Field-Effect Transistor and Method of Production - An n-layer is arranged above a substrate, which can be GaAs, and a p-layer ( | 10-06-2011 |
| 20110309412 | SUPERJUNCTION COLLECTORS FOR TRANSISTORS & SEMICONDUCTOR DEVICES - Superjunction collectors for transistors are discussed in this application. According to one embodiment, a bipolar transistor having a superjunction collector structure can comprise a collector electrode, a base electrode, an emitter electrode, a collector-base space charge region, and a superjunction collector. The collector-base space charge region can be disposed in electrical communication between the collector electrode and the base electrode. The superjunction collector region can be disposed in the collector-base space charge region. The superjunction collector region can comprise a plurality of alternating horizontally disposed P-type and N-type layers. The layers can be horizontally disposed layers that are layered on top of each other. The P-type and N-type layers can be doped with different types of doping levels. Other aspects, embodiments, and features are also discussed and claimed. | 12-22-2011 |
| 20110316050 | SEMICONDUCTOR DEVICE HAVING A HETEROJUNCTION BIOPOLAR TRANSISTOR AND A FIELD EFFECT TRANSISTOR - A semiconductor device with a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) formed over the same substrate; providing improved HBT characteristics and a lowered HBT collector resistance and also satisfactory etching of the FET gate recess, along with low ON-resistance in the FET. The sub-collector layer of a heterojunction bipolar transistor (HBT) is a laminated structure of multiple semiconductor layers, and moreover with a collector electrode formed on a section projecting out from one collector layer. In two of the FET, at least one semiconductor layer on the semiconductor substrate side of the semiconductor layers forming the sub-collector layer of the HBT also serves as at least a portion of a capacitor layer. The total film thickness of the HBT sub-collector layer is 500 nm or more; and the total film thickness of the FET capacitor layer is between 50 nm and 300 nm. | 12-29-2011 |
| 20120032233 | SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - A Silicon-Germanium heterojunction bipolar transistor (SiGe HBT) formed on a silicon substrate, wherein, an active region is isolated by field oxide regions, a collector region is formed in the active region and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions. Each of the pseudo buried layers is a lateral distance away from the active region and contacts with a part of the collector region. Deep-hole contacts are formed in the field oxide regions located on top of the pseudo buried layers to pick up the collector region. The present invention can adjust the breakdown voltage of devices through adjusting the lateral distance. A method for manufacturing the SiGe HBT is also disclosed. | 02-09-2012 |
| 20120056247 | PSEUDO BURIED LAYER AND MANUFACTURING METHOD OF THE SAME, DEEP HOLE CONTACT AND BIPOLAR TRANSISTOR - The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices. | 03-08-2012 |
| 20120061730 | SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, A METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND METHOD OF PRODUCING ELECTRONIC DEVICE - There is provided a semiconductor wafer including a base wafer that has an impurity region in which an impurity atom has been introduced into silicon, a plurality of seed bodies provided in contact with the impurity region, and a plurality of compound semiconductors each provided in contact with the corresponding seed bodies and lattice-matched or pseudo-lattice-matched to the corresponding seed bodies. The semiconductor wafer can further include an inhibitor provided on the base wafer and in which a plurality of apertures exposing at least a part of the impurity region are provided. | 03-15-2012 |
| 20120068228 | HETEROJUNCTION BIOPLAR TRANSISTOR STRUCTURE WITH GaPSbAs BASE - A heterojunction bipolar transistor (HBT) structure with GaPSbAs base is disclosed. The HBT structure generally includes a substrate, a subcollector layer, a collector layer, a base layer, an emitter layer, an emitter cap layer, and a contact layer laminated from bottom to top sequentially, and optionally may further comprise a buffer layer between the substrate and the subcollector layer. The subcollector layer includes heavily-doped GaAs; the collector layer includes GaAs, InGaP, or AlGaAs; the base layer includes GaPAsSb compound; the emitter layer includes InGaP or AlGaAs; the emitter cap layer includes GaAs; the contact layer includes InGaAs; and the substrate includes semi-insulating GaAs. Since the base having GaPSbAs compound has lower band gap energy, the turn-on voltage of the transistors can be reduced. Furthermore, the GaPSbAs can form a type II band alignment with InGaP and AlGaAs emitters, the potential spike of the conduction band at the emitter-base interface is eliminated and thus further reduces the turn-on voltage of the transistors and reduces power consumption. As a result of the type II band alignment, the collector layer can be InGaP, or AlGaAs and other wide band gap materials, which increases the breakdown voltage and reduces the offset voltage and hence improves the power performance of the transistors. | 03-22-2012 |
| 20120074465 | SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts. | 03-29-2012 |
| 20120091509 | SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region. | 04-19-2012 |
| 20120098039 | SIGE HETEROJUNCTION BIPOLAR TRANSISTOR HAVING LOW COLLECTOR/BASE CAPACITANCE AND MANUFACTURING METHOD OF THE SAME - A SiGe HBT having low collector-base capacitance is disclosed, which includes: a silicon substrate, including isolation trenches, a collector region situated between the isolation trenches, and lateral trenches; a SiGe base layer formed on the silicon substrate; and an emitter region formed on the SiGe base layer. Each lateral trench is situated in the collector region on one side of an isolation trench, and is connected to the isolation trench. Moreover, a manufacturing method of a SiGe HBT having low collector-base capacitance is disclosed, which includes: performing ion implantation to predetermined regions in a silicon substrate before trench isolations are formed; forming lateral trenches by etching ion implantation regions after the trench isolations are formed; then forming a SiGe HBT device by an ordinary semiconductor process. The present invention can reduce the collector-base capacitance and therefore improve high-frequency characteristics of the device. | 04-26-2012 |
| 20120112244 | VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening. | 05-10-2012 |
| 20120119262 | SiGe Heterojunction Bipolar Transistor and Method of Forming a SiGe Heterojunction Bipolar Transistor - A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region. | 05-17-2012 |
| 20120126292 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE - Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base. | 05-24-2012 |
| 20120132960 | REGROWN HETEROJUNCTION BIPOLAR TRANSISTORS FOR MULTI-FUNCTION INTEGRATED DEVICES AND METHOD FOR FABRICATING THE SAME - The present invention may provide an integrated device, which may include a substrate having first and second regions, the first region spaced apart from the second region, a first heterojunction bipolar transistor (HBT) device formed on the first region of the substrate, the first HBT device having a first collector layer formed above the first region of the substrate, the first collector layer having a first collector thickness and a first collector doping level, and a second HBT device formed on the second region of the substrate, the second HBT device having a second collector layer formed above the second region of the substrate, the second collector layer having a second collector thickness and a second collector doping level, the second collector thickness substantially greater than the first collector thickness, the second collector doping level lower than the first collector doping level. | 05-31-2012 |
| 20120132961 | HETEROJUNCTION BIPOLAR TRANSISTOR MANUFACTURING METHOD AND INTEGRATED CIRCUIT COMPRISING A HETEROJUNCTION BIPOLAR TRANSISTOR - Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed. | 05-31-2012 |
| 20120139009 | SOI SiGe-Base Lateral Bipolar Junction Transistor - A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area. | 06-07-2012 |
| 20120146098 | DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY - A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core. | 06-14-2012 |
| 20120181579 | VERTICAL PARASITIC PNP DEVICE IN A SILICON-GERMANIUM HBT PROCESS AND MANUFACTURING METHOD OF THE SAME - A vertical parasitic PNP device in a SiGe HBT process is disclosed which comprises a collector region, a base region, an emitter region, P-type pseudo buried layers and N-type polysilicons. The pseudo buried layers are formed at bottom of shallow trench field oxide regions around the collector region and contact with the collector region; deep hole contacts are formed on top of the pseudo buried layers to pick up collector electrodes. The N-type polysilicons are formed on top of the base region and are used to pick up base electrodes. The emitter region comprises a P-type SiGe epitaxial layer and a P-type polysilicon both of which are formed on top of the base region. A manufacturing method of a vertical parasitic PNP device in a SiGe HBT process is also disclosed. | 07-19-2012 |
| 20120199881 | BIPOLAR TRANSISTOR AND METHOD WITH RECESSED BASE ELECTRODE - High frequency performance of (e.g., silicon) bipolar devices ( | 08-09-2012 |
| 20120313146 | TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE - Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance R | 12-13-2012 |
| 20120319170 | ELECTRONIC DEVICE AND METHOD FOR PRODUCING ELECTRONIC DEVICE - Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element. | 12-20-2012 |
| 20130001647 | INTEGRATION OF VERTICAL BJT OR HBT INTO SOI TECHNOLOGY - In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer. The bipolar transistor structure includes: an opening formed in the top silicon layer; an opening in the buried oxide layer beneath the opening in the top silicon layer, the opening in the buried oxide layer including a region that undercuts the opening in the top silicon layer at a side of the opening in the top silicon layer; conductive material having a first conductivity type formed in the opening in the buried oxide layer such that the conductive material includes a region that undercuts the top silicon layer at the side of the opening in the top silicon layer; isolation dielectric material formed in the top silicon layer over the region of conductive material that undercuts the top silicon layer to define a bipolar transistor collector region having the first conductivity type, the collector region being in contact with the region of conductive material; a bipolar transistor base region formed in contact with an upper surface of the collector region, the base region having a second conductivity type that is opposite the first conductivity type; and an emitter region formed in contact with the base region, the emitter region having the first conductivity type. | 01-03-2013 |
| 20130062668 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE - Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base. | 03-14-2013 |
| 20130092981 | SIGE HBT HAVING A POSITION CONTROLLED EMITTER-BASE JUNCTION - A SiGe HBT having a position controlled emitter-base junction is disclosed. The SiGe HBT includes: a collector region formed of an N-doped active region; a base region formed on the collector region and including a base epitaxial layer, the base epitaxial layer including a SiGe layer and a capping layer formed thereon, the SiGe layer being formed of a SiGe epitaxial layer doped with a P-type impurity, the capping layer being doped with an N-type impurity; and an emitter region formed on the base region, the emitter region being formed of polysilicon. By optimizing the distribution of impurities doped in the base region, a controllable position of the emitter-base junction and adjustability of the reverse withstanding voltage thereof can be achieved, and thereby increasing the stability of the process and improving the uniformity within wafer. | 04-18-2013 |
| 20130099287 | GALLIUM ARSENIDE HETEROJUNCTION SEMICONDUCTOR STRUCTURE - Embodiments of semiconductor structure are disclosed along with methods of forming the semiconductor structure. In one embodiment, the semiconductor structure includes a semiconductor substrate, a collector layer formed over the semiconductor substrate, a base layer formed over the semiconductor substrate, and an emitter layer formed over the semiconductor substrate. The semiconductor substrate is formed from Gallium Arsenide (GaAs), while the base layer is formed from a Gallium Indium Nitride Arsenide Antimonide (GaInNAsSb) compound. The base layer formed from the GaInNAsSb compound has a low bandgap, but a lattice that substantially matches a lattice constant of the underlying semiconductor substrate formed from GaAs. In this manner, semiconductor devices with lower base resistances, turn-on voltages, and/or offset voltages can be formed using the semiconductor structure. | 04-25-2013 |
| 20130099288 | SiGe HBT and Manufacturing Method Thereof - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which a shallow trench is formed of a first shallow trench and a second shallow trench vertically joined together in the active region, the second shallow trench being located directly under the first shallow trench and having a width less than that of the first shallow trench; a pseudo buried layer is formed surrounding the bottom and side walls of the second shallow trench and is in contact with the collector region to serve as a connection layer of a collector; a deep hole contact is formed in the shallow trench and is in contact with the pseudo buried layer to pick up the collector. A SiGe HBT manufacturing method is also disclosed. The present invention is capable of improving the cut-off frequency of a SiGe HBT. | 04-25-2013 |
| 20130113020 | SIGE HBT AND METHOD OF MANUFACTURING THE SAME - A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed. | 05-09-2013 |
| 20130113021 | SIGE HBT HAVING DEEP PSEUDO BURIED LAYER AND MANUFACTURING METHOD THEREOF - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed. | 05-09-2013 |
| 20130113022 | SIGE HBT AND MANUFACTURING METHOD THEREOF - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, which includes: two isolation structures each being formed in a trench; a set of three or more pseudo buried layers formed under each trench with every adjacent two pseudo buried layers of the set being vertically contacted with each other; and a collector region. In this design, the lowermost pseudo buried layers of the two sets are laterally in contact with each other, and the collector region is surrounded by the two isolation structures and the two sets of pseudo buried layers. As the breakdown voltage of a SiGe HBT according to the present invention is determined by the distance between an uppermost pseudo buried layer and the edge of an active region, SiGe HBTs having different breakdown voltages can be achieved. A manufacturing method of the SiGe HBT is also disclosed. | 05-09-2013 |
| 20130119434 | BIPOLAR TRANSISTOR WITH A COLLECTOR HAVING A PROTECTED OUTER EDGE PORTION FOR REDUCED BASED-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance C | 05-16-2013 |
| 20130119435 | DIELECTRIC DUMMIFICATION FOR ENHANCED PLANARIZATION WITH SPIN-ON DIELECTRICS - An integrated device includes a lower layer pattern on a semiconductor substrate. The lower layer pattern includes a first region including first electrical devices and a second region including second electrical devices and electrically nonconductive dummy devices. A first device density of the first electrical devices in the first region is substantially greater than a second device density of the second electrical devices in the second region. A partially-planarizing dielectric layer is disposed on the lower layer pattern so as to cover the first electrical devices, the second electrical devices, and the electrically nonconductive dummy devices. The average height of the partially-planarizing dielectric layer in the first region is approximately the same as the average height in the second region. Through-holes are formed in the first region, and an electrically conductive material is disposed in the through-holes. | 05-16-2013 |
| 20130119436 | INTERFACE CONTROL IN A BIPOLAR JUNCTION TRANSISTOR - Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer. | 05-16-2013 |
| 20130126944 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH EPITAXIAL EMITTER STACK TO IMPROVE VERTICAL SCALING - A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p | 05-23-2013 |
| 20130126945 | ULTRA HIGH VOLTAGE SIGE HBT AND MANUFACTURING METHOD THEREOF - An ultra high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which, a collector region is formed between two isolation structures; a pseudo buried layer is formed under each isolation structure and each side of the collector region is connected with a corresponding pseudo buried layer; a SiGe field plate is formed on each of the isolation structures; each pseudo buried layer is picked up by a first contact hole electrode and each SiGe field plate is picked up by a second contact hole electrode; and each first contact hole electrode is connected to its adjacent second contact hole electrode and the two contact hole electrodes jointly serve as an emitter. A manufacturing method of the ultra high voltage SiGe HBT is also disclosed. | 05-23-2013 |
| 20130134483 | BIPOLAR TRANSISTOR WITH A RAISED COLLECTOR PEDASTAL FOR REDUCED CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased. | 05-30-2013 |
| 20130140607 | DEVICES AND METHODS RELATED TO A GALLIUM ARSENIDE SCHOTTKY DIODE HAVING LOW TURN-ON VOLTAGE - Disclosed are structures and methods related to metallization of a doped gallium arsenide (GaAs) layer. In some embodiments, such metallization can include a tantalum nitride (TaN) layer formed on the doped GaAs layer, and a metal layer formed on the TaN layer. Such a combination can yield a Schottky diode having a low turn-on voltage, with the metal layer acting as an anode and an electrical contact connected to the doped GaAs layer acting as a cathode. Such a Schottky diode can be utilized in applications such as radio-frequency (RF) power detection, reference-voltage generation using a clamp diode, and photoelectric conversion. In some embodiments, the low turn-on Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes. | 06-06-2013 |
| 20130146947 | SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY - A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot. | 06-13-2013 |
| 20130175581 | ZENER DIODE IN A SIGE BICMOS PROCESS AND METHOD OF FABRICATING THE SAME - A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed. | 07-11-2013 |
| 20130187198 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer. | 07-25-2013 |
| 20130234209 | SWITCHING DEVICE FOR HETEROJUNCTION INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME - A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 μA at 20V DC. | 09-12-2013 |
| 20130248935 | SIGE HETEROJUNCTION BIPOLAR TRANSISTOR WITH A SHALLOW OUT-DIFFUSED P+ EMITTER REGION - A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region. | 09-26-2013 |
| 20130256756 | INTEGRATED CIRCUIT HAVING A STAGGERED HETEROJUNCTION BIPOLAR TRANSISTOR ARRAY - An integrated circuit is provided. The integrated circuit may include, but is not limited to, a plurality of heterojunction bipolar transistors, wherein each heterojunction bipolar transistor is staggered with respect to any adjacent heterojunction bipolar transistor. The plurality of heterojunction bipolar transistors may be arranged in a column, wherein each heterojunction bipolar transistor is staggered in the column with respect to any adjacent heterojunction bipolar transistor in the column in a first direction and a second direction, wherein the second direction is substantially orthogonal to the first direction. | 10-03-2013 |
| 20130256757 | SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT - A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively. | 10-03-2013 |
| 20130256758 | INTEGRATED CIRCUIT STRUCTURE HAVING AIR-GAP TRENCH ISOLATION AND RELATED DESIGN STRUCTURE - A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate. | 10-03-2013 |
| 20130285120 | BIPOLAR TRANSISTOR HAVING COLLECTOR WITH GRADING - This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a high doping concentration at a junction with the base and at least one grading in which doping concentration increases away from the base. In some embodiments, the high doping concentration can be at least about 3×10 | 10-31-2013 |
| 20130285121 | BIPOLAR TRANSISTOR HAVING COLLECTOR WITH DOPING SPIKE - This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers. | 10-31-2013 |
| 20130299879 | SIGE HBT DEVICE AND MANUFACTURING METHOD OF THE SAME - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies. | 11-14-2013 |
| 20130313614 | METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME - The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance R | 11-28-2013 |
| 20130320403 | Epitaxial Base Layers For Heterojunction Bipolar Transistors - An exemplary embodiment of the present invention provides a heterojunction bipolar transistor comprising an emitter, a collector, and a base. The base can be disposed substantially between the emitter and collector. The base can comprise a plurality of alternating type-I and type-II layers arranged to form a short period super lattice. The type-I layers can have a band-gap that is narrower than the band-gap of the type-II layers. At least one of the type-I layers and the type-II layers can consist essentially of a quaternary material. | 12-05-2013 |
| 20130328108 | ULTRA-HIGH VOLTAGE SIGE HBT DEVICE AND MANUFACTURING METHOD OF THE SAME - An ultra-high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), which includes: a P-type substrate; an N-type matching layer, a P-type matching layer and an N− collector region stacked on the P-type substrate from bottom up; two field oxide regions separately formed in the N− collector region; N+ pseudo buried layers, each under a corresponding one of the field oxide regions and in contact with each of the N-type matching layer, the P-type matching layer and the N− collector region; an N+ collector region between the two field oxide regions and through the N− collector region and the P-type matching layer and extending into the N-type matching layer; and deep hole electrodes, each in a corresponding one of the field oxide regions and in contact with a corresponding one of the N+ pseudo buried layers. A method of fabricating an ultra-high voltage SiGe HBT is also disclosed. | 12-12-2013 |
| 20130341681 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED CURRENT GAIN AND A FABRICATION METHOD THEREOF - A heterojunction bipolar transistor (HBT) with improved current gain and the fabrication method thereof, in which the HBT comprises a substrate, a p-type buffer layer, a sub-collector layer, a collector layer, a base layer, an emitter layer, an emitter cap layer, and an emitter contact layer. Multiple etching processes are used for etching a base electrode contact region and terminated at the base layer. A collector electrode contact region is then formed in the base electrode contact region by an etching process terminated at the sub-collector layer. A base electrode is disposed on the base layer in the base electrode contact region. A collector electrode is disposed on the sub-collector layer in the collector electrode contact region. An emitter electrode is disposed on the emitter layer. | 12-26-2013 |
| 20140061727 | INTEGRATED CIRCUIT STRUCTURE HAVING AIR-GAP TRENCH ISOLATION AND RELATED DESIGN STRUCTURE - A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate. | 03-06-2014 |
| 20140077268 | Distributed Heating Transistor Devices Providing Reduced Self-Heating - According to various embodiments, a distributed heating transistor includes: a plurality of active regions where transistor action occurs including a heat source; and at least one inactive region where transistor action does not occur and no heat source is present, wherein adjacent active regions are separated by the at least one inactive region. The distributed heating transistor may be configured as field effect transistors (FETs), and bipolar junction transistors (BJTs). Methods for forming the distributed heating transistors are also provided. | 03-20-2014 |
| 20140097472 | BIPOLAR FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS OF FORMING THE SAME - Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET. | 04-10-2014 |
| 20140110761 | Monolithic HBT with Wide-Tuning Range Varactor - A semiconductor device having a tunable capacitance is disclosed, comprising a substrate, a semiconductor base layer comprising a first semiconductor material having a first band-gap, and a plurality of successive semiconductor layers positioned between the substrate and the semiconductor base layer. The plurality of successive semiconductor layers includes a tuning layer comprising a second semiconductor material having a second band-gap larger than the first band-gap. Furthermore, the tuning layer has a non-uniform doping profile with doping concentration that varies in accordance with distance from a surface of the tuning layer proximal to the semiconductor base layer. The tunable capacitance of the semiconductor device varies in accordance with an applied voltage between the base layer and one of the successive semiconductor layers. | 04-24-2014 |
| 20140117412 | Heterojunction Transistor and Manufacturing Method Therefor - A heterojunction transistor including a semiconductor body is provided. The semiconductor body includes: a base region of a semiconductor material having a first band-gap, the base region being of a first conductivity type; a collector region of a semiconductor material having a second band-gap which is larger than the first band-gap by at least about 1 eV, the collector region being of a second conductivity type and forming a first heterojunction with the base region; and an emitter region of a semiconductor material having a third band-gap which is larger than the first band-gap by at least about 1 eV, the emitter region being of the second conductivity type and forming a second heterojunction with the base region. Further, a method for producing a heterojunction transistor is provided. | 05-01-2014 |
| 20140124838 | HIGH SPEED SIGE HBT AND MANUFACTURING METHOD THEREOF - A high-speed SiGe HBT is disclosed, which includes: a substrate; STIs formed in the substrate; a collector region formed beneath the substrate surface and located between the STIs; an epitaxial dielectric layer including two portions, one being located on the collector region, the other being located on one of the STIs; a base region formed both in a region between and on surfaces of the two portions of the epitaxial dielectric layer; an emitter dielectric layer including two portions, both portions being formed on the base region; an emitter region formed both in a region between and on surfaces of the two portions of the emitter dielectric layer; a contact hole formed on a surface of each of the base region, the emitter region and the collector region. A method of manufacturing high-speed SiGe HBT is also disclosed. | 05-08-2014 |
| 20140131772 | SEMICONDUCTOR DEVICES WITH RECESSED BASE ELECTRODE - High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher f | 05-15-2014 |
| 20140131773 | SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY - A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, filling the respective slot. | 05-15-2014 |
| 20140151750 | HETEROJUNCTION BIPOLAR TRANSISTOR - Structures and methods of making a heterojunction bipolar transistor (HBT) device that include: an n-type collector region disposed within a crystalline silicon layer; a p-type intrinsic base comprising a boron-doped silicon germanium crystal that is disposed on a top surface of an underlying crystalline Si layer, which is bounded by shallow trench isolators (STIs), and that forms angled facets on interfaces of the underlying crystalline Si layer with the shallow trench isolators (STIs); a Ge-rich, crystalline silicon germanium layer that is disposed on the angled facets and not on a top surface of the p-type intrinsic base; and an n-type crystalline emitter disposed on a top surface and not on the angled lateral facets of the p-type intrinsic base. | 06-05-2014 |
| 20140167115 | HETEROJUNCTION BIPOLAR TRANSISTOR, POWER AMPLIFIER INCLUDING THE SAME, AND METHOD FOR FABRICATING HETEROJUNCTION BIPOLAR TRANSISTOR - A heterojunction bipolar transistor includes a ballast resistor layer of which resistance increases with an increase in temperature. The ballast resistor layer includes a first ballast resistor sub-layer having a positive temperature coefficient of resistivity in a first temperature range and a second temperature range and a second ballast resistor sub-layer having a negative temperature coefficient of resistivity in the first temperature range and a positive temperature coefficient of resistivity in the second temperature range. | 06-19-2014 |
| 20140167116 | HETEROJUNCTION BIPOLAR TRANSISTOR - The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches,=; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess. | 06-19-2014 |
| 20140175520 | METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME - The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance R | 06-26-2014 |
| 20140264457 | Heterojunction Bipolar Transistor having a Germanium Raised Extrinsic Base - Disclosed is a heterojunction bipolar transistor (“HBT”) including an intrinsic base in a SiGe layer. The HBT has a raised germanium extrinsic base over the SiGe layer. A base contact is situated over and contacting the raised germanium extrinsic base. An emitter is situated over the intrinsic base, and a collector is situated under the intrinsic base. The raised germanium extrinsic base has a reduced parasitic base-collector capacitance. The raised germanium extrinsic base is situated between a first dielectric layer and a second dielectric layer. Spacers are situated adjacent the second dielectric layer. The first dielectric layer can be a nitride based dielectric, the second dielectric layer can be an oxide based dielectric, and the spacers can be a nitride based dielectric. | 09-18-2014 |
| 20140264458 | Heterojunction Bipolar Transistor having a Germanium Extrinsic Base Utilizing a Sacrificial Emitter Post - Disclosed is a method for fabricating a heterojunction bipolar transistor (“HBT”), and the resulting structure. The method includes forming a germanium layer over a SiGe layer, the SiGe layer including an intrinsic base. Thereafter, an emitter sacrificial post and a raised germanium extrinsic base are formed by etching away portions of the germanium layer. Then, a conformal dielectric layer is deposited over the raised germanium extrinsic base. The process continues by removing the emitter sacrificial post and forming an emitter over the intrinsic base within an emitter opening defined by the previous removal of the emitter sacrificial post. The resulting structure has a raised germanium extrinsic base with a reduced parasitic base-collector capacitance. | 09-18-2014 |
| 20140312390 | Layout Structure of Heterojunction Bipolar Transistors - A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved. | 10-23-2014 |
| 20140332854 | Stress release structures for metal electrodes of semiconductor devices - This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and stresses can be induced in the devices during the fabrication and operation. The present invention provides metal electrode with stress release structures to reduce the strain and stresses in these devices. | 11-13-2014 |
| 20140353725 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE BY FORMING MONOCRYSTALLINE SEMICONDUCTOR LAYERS ON A DIELECTRIC LAYER OVER ISOLATION REGIONS - Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g., a bipolar device) is formed incorporating the resulting monocrystalline second and third semiconductor layers. | 12-04-2014 |
| 20140353726 | LATERAL BIPOLAR TRANSISTORS HAVING PARTIALLY-DEPLETED INTRINSIC BASE - A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode. | 12-04-2014 |
| 20140367745 | T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR - A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region. | 12-18-2014 |
| 20140374802 | BIPOLAR TRANSISTOR WITH MASKLESS SELF-ALIGNED EMITTER - Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes. | 12-25-2014 |
| 20150014747 | METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY - A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening. | 01-15-2015 |
| 20150035011 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer. | 02-05-2015 |
| 20150035012 | Methods and Apparatus for Bipolar Junction Transistors and Resistors - Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer. | 02-05-2015 |
| 20150041862 | METHOD OF MANUFACTURING IC COMPRISING A BIPOLAR TRANSISTOR AND IC - Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate ( | 02-12-2015 |
| 20150060950 | TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region. | 03-05-2015 |
| 20150091063 | SEMICONDUCTOR ELEMENT - A semiconductor element includes a collector contact layer of a high concentration N-type semiconductor layer. An N-type collector layer, a base layer, being a high concentration P-type semiconductor layer with a top surface, laminated on the collector layer, and an N-type emitter layer laminated on a part of the top surface, are laminated on the collector contact layer. A base-collector layer junction is located on a bonded surface, between the base layer and the collector layer. An inactive portion is located outside an outside end of a base electrode on the top surface, in a plan view. The inactive portion is formed by implanting ions of one of helium and argon into the first and second semiconductor layers. The inactive portion extends from the top surface to a position below the base-collector layer junction. | 04-02-2015 |
| 20150102389 | HETEROJUNCTION BIPOLAR TRANSISTOR GEOMETRY FOR IMPROVED POWER AMPLIFIER PERFORMANCE - A heterojunction bipolar transistor includes a base mesa, an emitter assembly formed over the base mesa, and a base contact. The emitter assembly includes multiple circular sectors. Each circular sector is spaced apart from one another such that a sector gap is formed between radial sides of adjacent circular sectors. The base contact, which is formed over the base mesa, has a central portion and multiple radial members. Each radial member extends outward from the central portion of the base contact along a corresponding sector gap. As such, each of the circular sectors of the emitter assembly is separated by a radial member of the base contact. The number of circular sectors may vary from one embodiment to another. For example, the emitter assembly may have three, four, six, or more circular sectors. | 04-16-2015 |
| 20150108548 | BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS - According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer. | 04-23-2015 |
| 20150108549 | FORMATION OF A HIGH ASPECT RATIO TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT RATIO TRENCH ISOLATION REGION - Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance C | 04-23-2015 |
| 20150137185 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH AN AIRGAP BETWEEN THE EXTRINSIC BASE AND COLLECTOR - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface. | 05-21-2015 |
| 20150137186 | FORMATION OF AN ASYMMETRIC TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING AN ASYMMETRIC TRENCH ISOLATION REGION - Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance C | 05-21-2015 |
| 20150145005 | TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT - Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region) of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed. | 05-28-2015 |
| 20150380531 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED CURRENT GAIN - A heterojunction bipolar transistor (HBT) with improved current gain, in which the HBT comprises a substrate, a modulation-doped buffer structure, an n-type sub-collector layer, an n-type collector layer, a p-type base layer, an n-type emitter layer, an emitter cap layer, and an emitter contact layer, a collector electrode, a base electrode and an emitter electrode, wherein the modulation-doped buffer structure includes at least one doped layer having a thickness of at least 10 Å and less than 3000 Å and doped a dopant element with doping concentration at least 3×10 | 12-31-2015 |
| 20160020307 | Heterojunction Bipolar Transistor - A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa. | 01-21-2016 |
| 20160087073 | BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer. | 03-24-2016 |
| 20160133732 | SEMICONDUCTOR DEVICE - In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×10 | 05-12-2016 |
| 20160141220 | HETERO-BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME - A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa. The metal layer, which is in contact with the primary mesa, may be made of at least one of tungsten (W), molybdenum (Mo), and tantalum (Ta) with a thickness of the 10 to 60 nm. | 05-19-2016 |
| 20160190293 | A Transistor and Method of Making - A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (f | 06-30-2016 |
| 20160379944 | POWER AMPLIFIER MODULES WITH POWER AMPLIFIER AND TRANSMISSION LINE AND RELATED SYSTEMS, DEVICES, AND METHODS - One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and an RF transmission line electrically coupled to an output of the power amplifier. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. The RF transmission line includes a nickel layer with a thickness that is less than 0.5 um, a conductive layer under the nickel layer, a palladium layer over the nickel layer, and a gold layer over the palladium layer. Other embodiments of the module are provided along with related methods and components thereof. | 12-29-2016 |
| 20160379975 | LATERAL BIPOLAR SENSOR WITH SENSING SIGNAL AMPLIFICATION - An integrated sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second bipolar junction transistors (BJTs). The first BJT has a base that is electrically coupled with the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second BJTs and the sensing structure are monolithically formed a common substrate. | 12-29-2016 |
| 20170236925 | SEMICONDUCTOR DEVICE WITH MULTIPLE HBTS HAVING DIFFERENT EMITTER BALLAST RESISTANCES | 08-17-2017 |
| 20190148531 | HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME | 05-16-2019 |
