Patent application number | Description | Published |
20080307276 | Memory Controller with Loopback Test Interface - In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect. | 12-11-2008 |
20080307286 | Combined Single Error Correction/Device Kill Detection Code - In one embodiment, an apparatus comprises a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission comprising M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one. | 12-11-2008 |
20110035560 | Memory Controller with Loopback Test Interface - In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect. | 02-10-2011 |
20110296110 | Critical Word Forwarding with Adaptive Prediction - In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays. | 12-01-2011 |
20120017135 | Combined Single Error Correction/Device Kill Detection Code - In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one. | 01-19-2012 |
20120069034 | QoS-aware scheduling - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 03-22-2012 |
20120072677 | Multi-Ported Memory Controller with Ports Associated with Traffic Classes - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 03-22-2012 |
20120072678 | Dynamic QoS upgrading - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 03-22-2012 |
20120072679 | Reordering in the Memory Controller - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 03-22-2012 |
20120072787 | Memory Controller with Loopback Test Interface - In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect. | 03-22-2012 |
20120126868 | Mechanism for an Efficient DLL Training Protocol During a Frequency Change - An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit. | 05-24-2012 |
20120137078 | Multiple Critical Word Bypassing in a Memory Controller - In one embodiment, a memory controller may be configured to transmit two or more critical words (or beats) corresponding to two or more different read requests prior to returning the remaining beats of the read requests. Such an embodiment may reduce latency to the sources of the memory requests, which may be stalled awaiting the critical words. The remaining words may fill a cache block or other buffer, but may not be required by the sources as quickly as the critical words in order to support higher performance. In some embodiments, once a remaining beat of a block is transmitted, all of the remaining beats may be transmitted contiguously. In other embodiments, additional critical words may be forwarded between remaining beats of a block. | 05-31-2012 |
20120159230 | Mechanism for Updating Memory Controller Timing Parameters During a Frequency Change - A mechanism for updating memory controller timing parameters during a frequency change includes a memory controller that controls memory transactions to a memory unit. The integrated circuit may also include a power manager unit that is coupled to the memory controller and may be configured to provide an indication that a memory clock frequency is changing to a new frequency. The integrated circuit also includes a storage that includes a number of entries. Each entry may store a predetermined set of timing values that corresponds to a respective memory clock frequency. In response to receiving the indication, the memory controller may access a given entry of the storage that corresponds to the new frequency, and may generate new timing values that correspond to the new frequency based upon the predetermined set of timing values stored within the given entry. | 06-21-2012 |
20130046938 | QoS-Aware Scheduling - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 02-21-2013 |
20130054901 | PROPORTIONAL MEMORY OPERATION THROTTLING - A memory controller receives memory operations via an interface which may include multiple ports. Each port is coupled to real-time or non-real-time requestors, and the received memory operations are classified as real-time or non-real-time and stored in queues prior to accessing memory. Within the memory controller, pending memory operations from the queues are scheduled for servicing. Logic throttles the scheduling of non-real-time memory operations in response to detecting a number of outstanding memory operations has exceeded a threshold. The throttling is proportional to the number of outstanding memory operations. | 02-28-2013 |
20130054902 | ACCELERATING BLOCKING MEMORY OPERATIONS - A memory controller, system, and method for accelerating blocking memory operations. A memory controller reorders memory operations so as to maximize efficient use of the memory device bus. When data for a newer memory operation is retrieved from memory and ready to be returned to a source device, the newer memory operation can be held up waiting for an older memory operation to be completed. In response, the memory controller forwards a push request for the older memory operation to a memory channel unit. The memory channel unit then sets a push bit of the older memory operation, which expedites the scheduling of the older memory operation. | 02-28-2013 |
20130064025 | DYNAMIC DATA STROBE DETECTION - Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal. | 03-14-2013 |
20140006743 | QoS-Aware Scheduling | 01-02-2014 |
20140052937 | Dynamic QoS Upgrading - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 02-20-2014 |
20140085320 | EFFICIENT PROCESSING OF ACCESS REQUESTS FOR A SHARED RESOURCE - A system and method for efficiently processing access requests for a shared resource. A computing system includes a shared memory accessed by multiple requestors. Control logic determines two requestors seek to access a same data block within the shared memory. In response to the determination, a first requestor of the two requestors sends a read request to the shared memory on behalf of the two requestors. The second requestor of the two requestors is prevented from sending a read request. In response to detecting data is returned as a response to the read request generated by the first requestor, both the first requestor and the second requestor retrieve the data. In response to detecting a given requestor of the two requestors generates an indication that it is unable to continue retrieving the same response data, the two requestors return to generating separate, respective read requests. | 03-27-2014 |
20140232731 | DISPLAY POWER MANAGEMENT - Techniques are disclosed relating to power management within an integrated circuit. In one embodiment, a display buffer receives image data through a data transfer interconnect. A data transfer interconnect is powered down based on the received image data being greater than a threshold amount of data. The display buffer transmits at least a portion of the image data to one or more outputs, and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer includes a plurality of line buffers, each configured to store a respective image source line. In such an embodiment, a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. | 08-21-2014 |
20140237195 | N-DIMENSIONAL COLLAPSIBLE FIFO - A system and method for efficient dynamic utilization of shared resources. A computing system includes a shared data structure accessed by multiple requestors. Both indications of access requests and indices pointing to entries within the data structure are stored in storage buffers. Each storage buffer maintains at a selected end an oldest stored indication of an access request from a respective requestor. Each storage buffer stores information for the respective requestor in an in-order contiguous manner beginning at the selected end. The indices stored in a given storage buffer are updated responsive to allocating new data or deallocating stored data in the shared data structure. Entries in a storage buffer are deallocated in any order and remaining entries are collapsed toward the selected end to eliminate gaps left by the deallocated entry. | 08-21-2014 |
20150062134 | PARAMETER FIFO FOR CONFIGURING VIDEO RELATED SETTINGS - A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve a top frame packet from the parameter buffer and determine if the frame packet is an internal type, i.e., intended for internal registers in a respective processing unit or if it is an external type, i.e., intended for an external register elsewhere in the graphics system. Based on the type of frame packet, the control circuit may update one or more register values accordingly. | 03-05-2015 |
20150070365 | ARBITRATION METHOD FOR MULTI-REQUEST DISPLAY PIPELINE - Embodiments of an apparatus and method are disclosed that may allow for arbitrating multiple read requests to fetch pixel data from a memory. The apparatus may include a first and a second processing pipeline, and a control unit. Each of the processing pipelines may be configured to generate a plurality of read requests to fetch a respective one of a plurality of portions of stored pixel data. The control unit may be configured to determine a priority for each read request dependent upon display coordinates of one or more pixels corresponding to each of the plurality of portions of stored pixel data, and determine an order for the plurality of read requests dependent upon the determined priority for each read request. | 03-12-2015 |
20150095630 | GLOBAL CONFIGURATION BROADCAST - Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect. | 04-02-2015 |
20150302544 | COORDINATE BASED QOS ESCALATION - Systems and methods for determining priorities of pixel fetch requests of separate requestors in a display control unit. The distance between the oldest pixel in an output buffer and the output equivalent coordinate of the oldest outstanding source pixel read request for each requestor in the display control unit is calculated. Then, a priority is assigned to each requestor based on this calculated distance. If a given requestor lags behind the other requestors based on a comparison of the distance between the oldest pixel and the output equivalent coordinate of the oldest outstanding source pixel read, then source pixel fetch requests for this given requestor are given a higher priority than source pixel fetch requests for the other requestors. | 10-22-2015 |
Patent application number | Description | Published |
20080319030 | SYDNONIMINES - SPECIFIC DOPAMINE REUPTAKE INHIBITORS AND THEIR USE IN TREATING DOPAMINE RELATED DISORDERS - Derivatives of Sydnonimine and its analogues, which bind selectively to dopamine transporter (DAT) proteins are useful for treating and delaying the progression of disorders and illnesses that are alleviated by inhibiting dopamine reuptake. | 12-25-2008 |
20090215839 | SYDNONIMINES-SPECIFIC DOPAMINE REUPTAKE INHIBITORS AND THEIR USE IN TREATING DOPAMINE RELATED DISORDERS - Derivatives of Sydnonimine and its analogues, which bind selectively to dopamine transporter (DAT) proteins are useful for treating and delaying the progression of disorders and illnesses that are alleviated by inhibiting dopamine reuptake. | 08-27-2009 |
20110020466 | FERTILIZED EGG ISOLATE AND USE THEREOF - Fertilized egg isolate, methods for preparing the fertilized egg isolate and uses thereof for treating mental health disorders and disease or conditions mediated by or associated with one or more glutamate receptors or by the neurokinin 2 (NK2) receptor. | 01-27-2011 |
20110288137 | SYDNONIMINES-SPECIFIC DOPAMINE REUPTAKE INHIBITORS AD THEIR USE IN TREATING DOPAMINE RELATED DISORDERS - Derivatives of Sydnonimine and its analogues, which bind selectively to dopamine transporter (DAT) proteins are useful for treating and delaying the progression of disorders and illnesses that are alleviated by inhibiting dopamine reuptake. | 11-24-2011 |
20120190743 | COMPOUNDS FOR TREATING DISORDERS OR DISEASES ASSOCIATED WITH NEUROKININ 2 RECEPTOR ACTIVITY - Compounds, pharmaceutical compositions and methods of treating a disorder or disease associated with neurokinin 2 (NK | 07-26-2012 |
20120264698 | METHOD OF USING DOPAMINE REUPTAKE INHIBITORS AND THEIR ANALOGS FOR TREATING AUTOIMMUNE CONDITIONS AND DELAYING OR PREVENTING AUTOIMMUNE RELATED PATHOLOGIC PROGRESSIONS - Dopamine reuptake inhibitors, and their analogs, are disclosed for treating and delaying the progression of autoimmune diseases. | 10-18-2012 |
20130131127 | METHOD OF USING DOPAMINE REUPTAKE INHIBITORS AND THEIR ANALOGS FOR TREATING DIABETES SYMPTOMS AND DELAYING OR PREVENTING DIABETES-ASSOCIATED PATHOLOGIC CONDITIONS - Method of using dopamine reuptake inhibitors, e.g., sydnonimine derivatives, for the management of diabetic symptoms and associated complications or conditions, such as hyperglycemia and diabetic neuropathy. | 05-23-2013 |
20130281495 | SYDNONIMINES-SPECIFIC DOPAMINE REUPTAKE INHIBITORS AND THEIR USE IN TREATING DOPAMINE RELATED DISORDERS - Derivatives of Sydnonimine and its analogues, which bind selectively to dopamine transporter (DAT) proteins are useful for treating and delaying the progression of disorders and illnesses that are alleviated by inhibiting dopamine reuptake. | 10-24-2013 |
20140206625 | METHOD OF USING DOPAMINE REUPTAKE INHIBITORS AND THEIR ANALOGS FOR TREATING AUTOIMMUNE CONDITIONS AND DELAYING OR PREVENTING AUTOIMMUNE RELATED PATHOLOGIC PROGRESSIONS - Dopamine reuptake inhibitors, and their analogs, are disclosed for treating and delaying the progression of autoimmune diseases. | 07-24-2014 |
20150366846 | METHOD OF USING DOPAMINE REUPTAKE INHIBITORS AND THEIR ANALOGS FOR TREATING DIABETES SYMPTOMS AND DELAYING OR PREVENTING DIABETES-ASSOCIATED PATHOLOGIC CONDITIONS - Method of using dopamine reuptake inhibitors, e.g., sydnonimine derivatives, for the management of diabetic symptoms and associated complications or conditions, such as hyperglycemia and diabetic neuropathy. | 12-24-2015 |
20160095839 | METHOD OF USING DOPAMINE REUPTAKE INHIBITORS AND THEIR ANALOGS FOR TREATING AUTOIMMUNE CONDITIONS AND DELAYING OR PREVENTING AUTOIMMUNE RELATED PATHOLOGIC PROGRESSIONS - Dopamine reuptake inhibitors, and their analogs, are disclosed for treating and delaying the progression of autoimmune diseases. | 04-07-2016 |
Patent application number | Description | Published |
20090006709 | PCI EXPRESS INTERFACE - The present invention discloses a PCI Express interface compatible with USB interface comprising a power supply terminal and a ground terminal, in which four data terminals include two data transmitting terminals and two data receiving terminals, characterized in that the power supply terminal and the ground terminal of said interface coincide with the corresponding terminals of USB interface specification, two of said four data terminals are guaranteed to have their positions and widths overlaid with the position of terminal D+ in USB interface specification and not with the position of terminal D− in USB interface specification, and the other two data terminals are guaranteed to have their positions and widths overlaid with the position of terminal D− in USB interface specification and not with the position of terminal D+ in USB interface specification. The PCI Express interface compatible with USB interface can provide a data transmission rate up to 3 Gb/S according to PCI Express interface specification and support to the conventional USB peripheral devices without any modification on them. It further has the advantages of small-sized outline and convenience in use. | 01-01-2009 |
20090012277 | Process for Preparation of Timosaponin B II - A method for preparation of Timosaponin BII, which uses Chinese traditional medicine Rhizoma Anemarrhenae or fresh rhizoma or fibrous root of | 01-08-2009 |
20090107912 | Composite Material and Method for Removing Harmful Algal Blooms and Turning Them into Submerged Macrophytes - The present invention proposes a composite material which can rapidly and effectively remove algae and transform them into submerged macrophytes. The composite material is a mixture of two functional materials: one can grow into submerged macrophytes, and the other is clays or modified local soil particles which can flocculate algae, inhibit phosphorus release from sediments and act as the carrier of the above-mentioned seeds, earthnuts, buds, and roots of submerged macrophytes. In addition, the present invention proposes a physical-chemical-ecological combined method for improving water quality and enhancing the ecological restoration of eutrophic lakes using the above-mentioned material. By spraying the composite material to the lake surface, the new method can remove algae and turbidity through flocculation and complete the planting process simultaneously so that HABs and eutrophication are effectively controlled. | 04-30-2009 |
20110161802 | Methods, processes and systems for centralized rich media content creation, custimization, and distributed presentation - The present invention is related to methods, processes, and systems that enable web users to quickly create, customize, and publish rich media contents via Internet. Web addresses and attributes with regard to the published rich media contents are also generated. The published rich media contents, web addresses and attributes are stored locally in a centralized place, but they can be called by any geographically distributed third-party websites or remote web users, and then be presented on the third-party websites or the terminal devices of the remote web users. Furthermore, the present invention also enables web users to quickly create and customize personal online stores at a centralized place, and then list the published rich media contents in their personal online stores. These listed rich media contents can also be referenced and called by any geographically distributed third-party websites or remote web users, and then be presented on the third-party websites or the terminal devices of the remote web users. | 06-30-2011 |
20120019193 | CHARGING AND POWER SUPPLYING METHOD FOR TERMAL, AND TERMINAL - Embodiments of the present invention relate to a charging method for a terminal, a power supplying method for a terminal, and a terminal. The terminal comprises at least a master device supply. The method comprises: detecting a power level of a battery of a second terminal when the second terminal is in connection with the terminal, and when the power level of the battery of the second terminal is less than a predetermined first charge threshold, controlling the master device supply to be connected with the battery of the second terminal, such that the master device supply charges the battery of the second terminal. According to the embodiments of the present invention, it is possible to ensure that the battery of the second terminal can carry as much power as possible. in case that the power of the battery of the terminal is low, the battery of the second terminal can supply power to the terminal and the second terminal to maintain the operation of them. As a result, the usage, stability, and convenience of the terminal can be improved. | 01-26-2012 |
20120226665 | METHOD FOR PRESENTING FILES UPON SWITCHING BETWEEN SYSTEM STATES AND PORTABLE TERMINAL - Methods for presenting files upon switching between system states and portable terminals are provided. The portable terminal comprising a first system platform and a second system platform, a state in which the presentation of the file is controlled by the first system platform being a first state, and a state in which the presentation of the file is controlled by the second system platform being a second state. The method comprising: detecting, by the first system platform in the first state, that a status of the file satisfies a preset condition; backuping, by the first system platform, the file for the second system platform; and switching to the second state, and continuing, by the second system platform, the presentation of the file based on the backup file. With the portable terminal of hybrid system architecture according to embodiments of the present invention, if the system state is switched while a file is being played, the switched-to system can continue presenting the file based on the backup file, according to the presentation progress before the system switching. In this way, it is possible to achieve a seamless presentation of the file before and after the switching, and thus improve user's experience. | 09-06-2012 |
20120260084 | METHOD FOR SWITCHING SYSTEM STATE AND PORTABLE TERMINAL - A method for switching system state and a portable terminal. The method is applied to a portable terminal comprising a first system and a second system. The second system has a second control module provided therein. The method comprises: obtaining, by the second system, state information of the first system through the second control module when at least one of the first system and the second system is in an inactive state; receiving, by the second control module, a system state switching event; switching, by the second control module, the second system to a state corresponding to the state information of the first system based on the state information of the first system. According to the embodiments of the present invention, when the system state is to be switched, it is not necessary that both systems are in the active state. Rather, the state information can be transmitted between the systems in the inactive state by using a control module provided in one or both of the systems, and the power consumption of the portable terminal can be reduced. | 10-11-2012 |
20130094511 | PACKET DIVERSION METHOD AND DEEP PACKET INSPECTION DEVICE - A packet diversion method and a DPI device are disclosed in the present invention. The method includes: receiving a packet, where the packet contains a user identifier; according to the user identifier and preset first correspondence between the user identifier and a service type, searching for the service type corresponding to the user identifier in the packet; adding an inner virtual local area network Vlan header to the packet according to the service type, preset second correspondence between a service type and a slave device identifier, and preset third correspondence between a slave device identifier and each bit in a diversion identifier field; and diverting the packet to a corresponding slave device according to the diversion identifier in the diversion identifier field. The inner Vlan header carrying the diversion identifier field is added to the packet, to indicate diversion of the packet in a same cluster. | 04-18-2013 |
20130135304 | GENERATING THREE-DIMENSIONAL VIRTUAL SCENE - A method and system for generating a three-dimensional (3D) virtual scene are disclosed. The method includes: identifying a two-dimensional (2D) object in a 2D picture and the position of the 2D object in the 2D picture; obtaining the three-dimensional model of the 3D object corresponding to the 2D object; calculating the corresponding position of the 3D object corresponding to the 2D object in the horizontal plane of the 3D scene according to the position of the 2D object in the picture; and simulating the falling of the model of the 3D object onto the 3D scene from a predetermined height above the 3D scene, wherein the position of the landing point the model of the 3D object in the horizontal plane is the corresponding position of the 3D object in the horizontal plane of the 3D scene. | 05-30-2013 |
20130222722 | Display Method, Information Processing Method, Electronic Device, And Display System - A display method is applied in a first electronic device and a second electronic device, wherein, the first electronic device includes a first display unit having a plurality of edges, and the second electronic device includes a second display unit also having a plurality of edges. The method includes the first electronic device and the second electronic device are tiled and placed in alignment, with a first edge as a first tiling shaft; a predetermined display content is displayed on the first display unit and the second display unit after tiling; when the first electronic device and/or the second electronic device is/are changed in position and re-tiled, a second edge is re-determined as a second tiling shaft; and according to the second tiling shaft, a third display content is displayed on the first display unit, and a fourth display content is displayed on the second display unit. | 08-29-2013 |
20140013844 | Terminal Device - A terminal device is described that includes a housing configured to accommodate various components of the terminal device; a first sensing unit configured to collect first status information of the terminal device; a second sensing unit configured to collect second status information of the terminal device; and a processing unit configured to determine a manner that a user holds the terminal device based on the first status information and the second status information. | 01-16-2014 |
20140059459 | PROCESSING METHOD AND PROCESSING DEVICE FOR DISPLAYING ICON AND ELECTRONIC DEVICE - A processing method and a processing device for displaying an icon and an electronic device are provided. The electronic device has a plurality of variable operation forms. Specifically, a current operation form of the electronic device is detected and determined. A first application applicable to the electronic device in the currently determined operation form is selected according to the determined operation form. Then, a display policy for the icon which corresponds to the selected and determined application and is displayed on the display screen of the electronic device is correspondingly adjusted. Therefore, it is ensured that the user can rapidly, conveniently and accurately select the available application in the case of the operation form of the electronic device, thus improving the user experience when the user uses the electronic device. | 02-27-2014 |
20150044424 | BOTTOM ELECTRODE AND MANUFACTURING METHOD THEREOF - A bottom electrode and a method of manufacturing the same are disclosed. The present invention relates to the field of dry etching, and has solved problems of separately fabrication of the ceramic points and ceramic layer of the conventional bottom electrode, low adhesion strength between the ceramic points and ceramic layer, incidental dropping off the ceramic layer. The bottom electrode includes: a metal substrate and an insulating layer disposed on the metal substrate, wherein the metal substrate comprises: a base substrate and a plurality of protrusion parts disposed on the base substrate, the insulating layer is disposed on surface of the base substrate and the protrusion parts on surface of the base substrate. Insulating protrusion points are formed at the protrusion parts. | 02-12-2015 |
20150067635 | IMPACT ANALYSIS OF CHANGE REQUESTS OF INFORMATION TECHNOLOGY SYSTEMS - A method for impact analysis of change requests of a computing system is provided. The method includes, identifying artifacts and tasks that are impacted by a change request on a target project based on a change request repository, an artifact dependency network and a task-artifact mapping repository. The method further includes, determining an impact analysis priority for each of the identified tasks based on associations among the change request and the identified artifacts and tasks, and a project status tracking repository. The method further includes analyzing an impact of the change request on each of the identified tasks according to the determined impact analysis priority. The method further includes obtaining requirements, requirement dependencies and requirement constraints of the project scope to identifying artifacts and tasks that are impacted by a change request on the target project of the project scope. | 03-05-2015 |
20150089361 | METHOD AND APPARATUS FOR MANAGING ELECTRONIC DEVICE - A method and an apparatus for managing an electronic device are provided. The method comprises: determining a state of the electronic device; monitoring whether an instruction for invoking a notification component in the electronic device has been generated when the state of the electronic device satisfies a predetermined condition; and intercepting the instruction for invoking the notification component to prevent a notification event associated with the instruction from being executed. | 03-26-2015 |
20150095875 | COMPUTER-ASSISTED RELEASE PLANNING - A compute-implemented method and apparatus for assisting release planning, including steps of: obtaining remaining requirements that are expected to be included in a current release plan; obtaining the release plan, which comprises a set of planned requirements that are already included in the release plan and a set of release constraints; determining that there is a conflict between the release constraints and the planned requirements; rendering, in response to this determination, a proposal to create a modified release plan that is a function of the remaining requirements and of the current release plan; and forecasting, as a function of the remaining requirements and of the modified release plan, whether the addition of another requirement to the release plan would create a conflict with the release constraints. | 04-02-2015 |
20150103963 | SEQUENCE SYNCHRONIZATION APPARATUS AND METHOD AND RECEIVER - Embodiments of the present disclosure provide a sequence synchronization apparatus and method and a receiver. The sequence synchronization apparatus includes: a signal receiving unit configured to receive a clock synchronized signal including a training symbol, the training symbol being in-phase modulated or being modulated with a fixed phase difference based on all or part of subcarriers; and a symbol detecting unit configured to detect the training symbol, so as to achieve sequence synchronization of the signal. With the embodiments of the present disclosure, not only sequence synchronization may be achieved by using minimum complexity as possible, but also the sequence synchronization apparatus is made simple, fast and accurate. | 04-16-2015 |
20150121381 | CHANGE-REQUEST ANALYSIS - A method and associated systems for analyzing a change request of a project that involves an IT system, where IT system contains IT artifacts that have predefined relationships. One or more processors obtain a change request; use information contained in the change request to select an applicable decomposition agent; use information in the selected decomposition agent to decompose the change request into a set of component sub-change requests; correlate at least one of the sub-change requests with one of the IT artifacts; and display the sub-change requests. In alternate implementations, selecting the applicable decomposition agent may require additional user input. | 04-30-2015 |
20150248778 | GENERATING A TREE MAP - A method for generating a tree map for tree map visualization includes obtaining node information of a plurality of nodes to be processed, the plurality of nodes to be processed being sub-nodes sharing a same parent node and the node information comprising at least sizes of the nodes; determining from the plurality of nodes a plurality of candidate nodes whose sizes are less than a threshold size; determining at least one super node including the plurality of candidate nodes based on the node information of the determined plurality of candidate nodes, a screen size, and the threshold size, such that when displaying in a zooming-in mode the super node on the screen, all candidate nodes in the super node are displayed at display sizes not less than the threshold size; and determining data required for displaying the tree map based on the determined super node. | 09-03-2015 |
20150287226 | GENERATING A TREE MAP - A method for generating a tree map for tree map visualization includes obtaining node information of a plurality of nodes to be processed, the plurality of nodes to be processed being sub-nodes sharing a same parent node and the node information comprising at least sizes of the nodes; determining from the plurality of nodes a plurality of candidate nodes whose sizes are less than a threshold size; determining at least one super node including the plurality of candidate nodes based on the node information of the determined plurality of candidate nodes, a screen size, and the threshold size, such that when displaying in a zooming-in mode the super node on the screen, all candidate nodes in the super node are displayed at display sizes not less than the threshold size; and determining data required for displaying the tree map based on the determined super node. | 10-08-2015 |
20150310216 | Computer Health Index Display Apparatus and Method - The disclosure discloses an apparatus for displaying a computer health index comprising: a health index calculator configured to calculate one or more health sub-indices, and calculate a computer health index based on the one or more health sub-indices, wherein each health sub-index is associated with one of one or more computer states, and reflects the health degree of the associated computer state; and a simple index display configured to receive the computer health index from the health index calculator, and displaying a small icon reflecting a value of said computer health index. | 10-29-2015 |
20160050237 | METHOD AND DEVICE FOR ACQUIRING MULTIMEDIA DATA STREAM - A method for acquiring a multimedia data stream includes establishing, by a terminal, a socket connection with a target camera device when a preset trigger event is triggered in the terminal and sending a transfer command to the target camera device through the socket connection when an event of starting preview is detected. The transfer command instructs the target camera to transfer the multimedia data stream. The method further includes receiving the multimedia data stream transferred by the target camera device and displaying the multimedia data stream in a specified preview interface. | 02-18-2016 |
20160061927 | Identification method and identification system for an object's passing route direction - An identification method comprising: when an object is in a whole process from entering to separating from a region inducted by the low-frequency electromagnetic field, receiving the low-frequency signal of the low-frequency electromagnetic field in real time; extracting the attribute code and signal intensity corresponding to the low-frequency signal received and conducting associate storage; and after the object separates from the region inducted by the low-frequency electromagnetic field, determining the route direction along which the object passes through the vector beacons according to the attribute code and signal intensity stored. | 03-03-2016 |
Patent application number | Description | Published |
20120097944 | TEST STRUCTURES FOR THROUGH SILICON VIAS (TSVs) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded. | 04-26-2012 |
20120242346 | Power Compensation in 3DIC Testing - A device, such as a 3DIC stacked device includes a first device under test (DUT) connected to a first force pad by a first through substrate via (TSV) stack and connected to a first sense pad by a second TSV stack. The device further includes a second DUT stacked above the first DUT and connected to a second force pad and a second force pad by a second third TSV and connected to a second sense pad by a fourth TSV. Functional blocks on either the first or second blocks can be accessed for testing by way of the TSVs. In some applications the TSVs are vertically aligned to form TSV stacks. | 09-27-2012 |
20120246514 | Adaptive Test Sequence for Testing Integrated Circuits - A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence. | 09-27-2012 |
20120256649 | Dynamic Testing Based on Thermal and Stress Conditions - A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results. | 10-11-2012 |
20120286814 | 3D IC Testing Apparatus - A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once. | 11-15-2012 |
20130078745 | Production Flow and Reusable Testing Method - An embodiment is a method. The method comprises providing a substrate comprising a die area. The die area comprises sections of pad patterns, and first sections of the sections each comprise a first uniform pad pattern. The method further comprises probing a first one of the first sections with a first probe card; stepping the first probe card to a second one of the first sections; and probing the second one of the first sections with the first probe card. | 03-28-2013 |
20130099809 | METHODS AND SYSTEMS FOR PROBING SEMICONDUCTOR WAFERS - A wafer probing method includes calibrating a wafer probing system, checking continuity between probe pins of the wafer probing system and respective conductors of a wafer under test, and identifying at least an interconnect structure in the wafer under test to determine whether a fault exists. | 04-25-2013 |
20130099812 | Probe Cards for Probing Integrated Circuits - A device includes a probe card, which further includes a chip. The chip includes a semiconductor substrate, a test engine disposed in the chip, wherein the test engine comprises a device formed on the semiconductor substrate, wherein the device is selected from the group consisting essentially of a passive device, an active device, and combinations thereof. A plurality of probe contacts is formed on a surface of the chip and electrically connected to the test engine. | 04-25-2013 |
20130147049 | Circuit Probing Structures and Methods for Probing the Same - A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component. | 06-13-2013 |
20130196458 | METHOD OF TESTING THROUGH SILICON VIAS (TSVS) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded. | 08-01-2013 |
20140176165 | Apparatus for Three Dimensional Integrated Circuit Testing - A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit. | 06-26-2014 |
20140361804 | METHOD AND APPARATUS OF WAFER TESTING - A system for testing a wafer includes a probe card and a wafer. The probe card includes at least one first probe site and at least one second probe site. The wafer includes a plurality of dies. The at least one first probe site is arranged for a first test, and the at least one second probe site is arranged for a second test. Each of the plurality of dies corresponds to first probe pads and second probe pads. Each of the at least one first probe site is arranged to touch the first probe pads of each of the plurality of dies. Each of the at least one second probe site is arranged to touch the second probe pads of each of the plurality of dies. | 12-11-2014 |
20150130498 | SYSTEMS FOR PROBING SEMICONDUCTOR WAFERS - A wafer probing system includes a plurality of contacting pins connected to a test head. The system further includes a probe card electrically connectable with the test head, where the probe card includes a circuit board having a plurality of contact pads on opposite sides of the circuit board. | 05-14-2015 |
Patent application number | Description | Published |
20130286465 | TFT ARRAY SUBSTRATE, E-PAPER DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A TFT array substrate, an electronic paper display panel and method for manufacturing the same are disclosed. The electronic paper display panel includes: a first transparent substrate, and an array of storage capacitors located on an inner side of the first transparent substrate. Each of the storage capacitors includes a common electrode located on the first transparent substrate, a transparent capacitor medium layer located on the common electrode, and a pixel electrode ( | 10-31-2013 |
20130314636 | TFT ARRAY SUBSTRATE AND FORMING METHOD THEREOF, AND DISPLAY PANEL - A TFT array substrate is disclosed. The TFT array substrate includes an array of TFT switches including scan lines, data lines intersecting the scan lines, and TFT switches. Each of the TFT switches includes a gate electrode electrically connected to a scan line, a source electrode electrically connected to a data line, and a drain electrode. The TFT array substrate also includes an array of pixel electrodes, each of the pixel electrodes is electrically connected to the drain electrode of a corresponding TFT switch. At least one first pixel electrode is disposed in the array of the pixel electrodes, and each first pixel electrode has an overlapping portion overlapped by at least one of the scan lines and the data lines. In addition, in the overlapping portion, a shielding electrode layer is located between the first pixel electrode and at least one of the scan line and the data line overlapping the first pixel electrode. | 11-28-2013 |
20140078420 | IN-CELL TOUCH PANEL AND COLOR FILTER SUBSTRATE THEREOF - A color filter device for in-cell touch panel is disclosed. The device includes a substrate, a black matrix with a plurality of openings that is formed on the substrate, and a plurality of sensing electrodes and a plurality of driving electrodes both formed on the black matrix. The sensing electrodes are independent of the driving electrodes, the black matrix is disconnected between the sensing electrodes and the driving electrodes, and the disconnected portion of the black matrix is blocked by an opaque material. | 03-20-2014 |
20140176884 | LIQUID CRYSTAL PANEL - A liquid crystal panel includes a TFT (Thin Film Transistor) substrate, a CF (Color Filter) substrate and liquid crystal layer arranged between the TFT substrate and the CF substrate. The liquid crystal panel includes a display area and a non-display area, the non-display area surrounds the display area, a sealing material coating area is arranged in the non-display area, and a sealing material is arranged in the sealing material coating area to seal the liquid crystal layer between the TFT substrate and the CF substrate. A first black matrix is arranged inside the CF substrate in the non-display area, devices including a metal layer are arranged inside the TFT substrate in the non-display area, and voids are arranged in the first black matrix of the CF substrate corresponding to at least a part of the devices including the metal layer. | 06-26-2014 |
20140184938 | EMBEDDED TOUCH DISPLAY PANEL AND TOUCH DISPLAY DEVICE - A touch display panel comprises a color film substrate, which comprises a conducting layer arranged on a transparent substrate. The conducting layer comprises a plurality of first and second wires, and a color resistance insulating layer lying flat on the conducting layer, where the color resistance insulating layer includes first color resistances with via holes and second color resistances without via holes. The color film substrate also includes a plurality of bridges formed on the color resistance insulating layer, where at least one second color resistance has an extension portion extending in a direction substantially perpendicular to the second color resistances, where the extension portion isolates the conducting layer from the bridges between adjacent second color resistances. | 07-03-2014 |
20140184945 | TOUCH PANEL AND TOUCH DISPLAY DEVICE - The present invention provides a touch panel and a touch display device, the touch panel includes: a transparent substrate; a conductive layer disposed on the transparent substrate, where the conductive layer includes a plurality of first conductive patterns and a plurality of second conductive patterns intersecting with the plurality of first conductive patterns, and each of the second conductive patterns is separated into multiple segments by the plurality of first conductive patterns; a color resistance insulating layer disposed on the conductive layer, where the color resistance insulating layer includes a plurality of through-holes; and a metal bridging layer disposed on the color resistance insulating layer, where the multiple segments of the second conductive pattern are connected together by the metal bridging layer via the through-holes. With the technical solutions of the present invention, the color resistor is used as the insulating layer to replace the existing organic film layer, thus avoiding the undesirable risk brought about by the manufacturing process for coating the organic film, simplifying the manufacturing process and reducing the production costs. | 07-03-2014 |
20150015623 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel includes a substrate, multiple data line groups which are arranged on the substrate sequentially and adjacently, and multiple gate line groups which are arranged on the substrate sequentially and adjacently. The display panel further includes multiple pixel electrode array units which are arranged in an array on the substrate. The pixel electrodes in the pixel electrode array unit are electrically connected with the data lines and the gate lines via switch elements. Data driving signals received by any two adjacent pixel electrodes in a same column have opposite polarities. The pixel electrode array unit includes a first pixel electrode, a second pixel electrode, a third pixel electrode, and a fourth pixel electrode. Data driving signals received by any two adjacent pixel electrodes of a same type in the same row have opposite polarities. | 01-15-2015 |
20150036064 | EMBEDDED CAPACITIVE TOUCH DISPLAY PANEL AND EMBEDDED CAPACITIVE TOUCH DISPLAY DEVICE - An embedded capacitive touch display panel is disclosed. The display panel includes a first transparent substrate, and a grid-shaped metal conductive layer formed on the first transparent substrate. The grid-shaped metal conductive layer includes first metal electrodes extending in a first direction, and second metal electrodes extending in a direction intersecting the first direction. Each of the second metal electrodes is divided into multiple sections by openings, through which the first metal electrodes extend. In addition, the first and second metal electrodes are separated from each other by gaps. The display panel also includes a color filter layer, including a plurality of red, green, and blue color resist units, and a green color resist bar. The gaps include a first gap part, parallel to the green color resist bar, where the first gap part is not overlapped by the green color resist bar. | 02-05-2015 |
20150185932 | DISPLAY APPARATUS AND METHOD OF REPAIRING BROKEN LINE THEREOF - A display apparatus is disclosed. First and second conduction terminals are respectively arranged on inner sides of upper and lower substrates. The first and second conduction terminals are electrically connected, and first conduction terminals are respectively electrically connected with first signal traveling lines. In addition, second conduction terminals are respectively electrically connected with second signal traveling lines on the inner side of the lower substrate and pairs of alternative conduction terminals. First and second alternative conduction terminals are respectively arranged on the inner sides of the upper and lower substrates. Furthermore, the first and second alternative conduction terminals are respectively electrically connected through first repair lines, which are arranged on the inner side of the upper substrate. In addition, the first and second alternative conduction terminals are respectively electrically connected with the first repair lines and with alternative wires. | 07-02-2015 |
20150332058 | METHOD FOR ENCRYPTING A 3D MODEL FILE AND SYSTEM THEREOF - The invention discloses a method for encrypting a 3D model file and system thereof. The system of the invention comprises a data reading module used to read data of the 3D model file; a mesh shifting module for selecting at least one triangle mesh and shifting the coordinates of the vertexes of the selected triangle mesh by a vector; a gap filling module for filling a gap generated from shifting the vertexes of the selected triangle mesh by the vector to generate a revised 3D model file; and a model generating module for storing the revised 3D model file to generate an encrypted 3D model file. Compared to the prior art, the invention provides the users for previewing the 3D model file, and the invention only provides the authorized users for correctly printing the original 3D model. Therefore, the invention can achieve the purpose for encrypting the 3D model file. | 11-19-2015 |
Patent application number | Description | Published |
20140167799 | THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE - The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection. | 06-19-2014 |
20140253162 | INTEGRATED CIRCUIT TEST SYSTEM AND METHOD - A system for testing a device under test (DUT) includes a probe card and a test module. The probe card includes probe beds electrically coupled to a circuit board and a first plurality of electrical contacts coupled to the circuit board, which are for engaging respective ones of a plurality of electrical contacts of a test equipment module. Probes are coupled to respective probe beds and are disposed to engage electrical contacts of the DUT. The probe card includes a second plurality of electrical contacts coupled to the circuit board. The first and second pluralities of contacts are mutually exclusive. The test module includes a memory, a processor, and a plurality of electrical contacts electrically coupled to respective ones of the second plurality of electrical contacts of the probe card. The circuit board includes a first electrical path for electrically coupling the test equipment module to the test module. | 09-11-2014 |
20150087089 | 3D IC Testing Apparatus - A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup. | 03-26-2015 |
20150115986 | ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE - Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment. | 04-30-2015 |
20150115993 | STRUCTURE AND METHOD FOR TESTING STACKED CMOS STRUCTURE - A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus. | 04-30-2015 |
20150241508 | Test Circuit And Method - A circuit is disclosed that includes a signal-forcing path, a discharging path, a contact probe, a monitoring probe and a switch module. The signal-forcing path is connected to a signal source. The discharging path is connected to a discharging voltage terminal. The contact probe contacts a pad module of an under-test device. The monitoring probe generates a monitored voltage associated with the pad module. The switch module is operated in a discharging mode to connect the contact probe to the discharging path when the monitored voltage does not reach a threshold voltage such that the under-test device is discharged and is operated in an operation mode to connect the contact probe to the signal-forcing path when the monitored voltage reaches the threshold voltage such that a signal generated by the signal source is forced to the under-test device. | 08-27-2015 |
20150323589 | COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS THEREWITH - A composite integrated circuit (IC) includes a first circuit layer, a second circuit layer having a first chip and a second chip, and a first wireless power transfer (WPT) device in the first chip or the first circuit layer. The first WPT device generates a power supply voltage by extracting energy from an electromagnetic signal. A first tracking circuit in the second chip or the first circuit layer is powered by the power supply voltage from the first WPT device and stores or outputs tracking data in response to an instruction extracted from the electromagnetic signal. | 11-12-2015 |
20150380328 | Circuit Probing Structures and Methods for Probing the Same - A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component. | 12-31-2015 |
20160077147 | INTEGRATED FAN-OUT PILLAR PROBE SYSTEM - Disclosed herein is a method of probe testing dies, the method comprising loading a wafer having a first die and a second die into a prober and bringing probes of the prober into contact with first contact pads of the first die according to first probe parameters. A first probe contact test of first values of the contact between the probes and the first contact pads is performed, and a die test of the first die is performed after performing the probe contact test. Results of the die test and results of the probe contact test are saved and second probe parameters are automatically generated based on at least the results of the first probe contact test. | 03-17-2016 |
20160113099 | THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE - The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection. | 04-21-2016 |