| Entries |
| Document | Title | Date |
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| 20100283496 | TRANSMISSION-MODULATED PHOTOCONDUCTIVE DECAY MEASUREMENT SYSTEM - A system and method for measuring recombination lifetime of a photoconductor or semiconductor material in real time and without physically contacting the material involving positioning the sample material between a transmitter and a receiver so that electromagnetic signals, preferably radio frequency signals, traveling from the transmitter to the receiver pass through the sample material. The electromagnetic signals are modulated as they pass through the sample material depending on the carrier density and conductivity of the sample material. The modulated electromagnetic signals received by the receiver are then analyzed to determine the carrier recombination lifetime of the sample material. | 11-11-2010 |
| 20100283497 | SEMICONDUCTOR TESTING DEVICE, SEMICONDUCTOR DEVICE, AND TESTING METHOD - A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses ( | 11-11-2010 |
| 20100301892 | Electrostatic discharge withstand voltage evaluating device and electrostatic discharge withstand voltage evaluating method - In one embodiment of the present invention, an electrostatic discharge withstand voltage evaluating device includes: an application device, including a first connecting section and a second connecting section, for supplying pulse electric charge, the first connecting section being connectable to one or whole terminal(s) of one of input terminals and output terminals of a source driver, and supplying electric charge to the source driver, the second connecting section being connectable to one or whole terminal(s) of the other one of the input terminals and the output terminals, and enabling said one or whole terminal(s) of the other one of the input terminals and the output terminals to be grounded; and a common connecting section being connectable to the plurality of output terminals of the source driver, and causing the plurality of output terminals to be electrically connected to each other, wherein the output terminals of the source driver are connected, via the common connecting section, to one of the first connecting section and the second connecting section. Therefore, the electrostatic discharge withstand voltage evaluating device can more successfully recreate how a failure occurs in a semiconductor device and can evaluate an electrostatic discharge breakdown withstand of the semiconductor device. | 12-02-2010 |
| 20100308856 | Test apparatus and test method - Provided is a test apparatus for testing a device under test, including: a level comparing section that receives a signal under test output from the device under test and outputs a logical value, the logical value indicating a comparison result obtained by comparing a signal level of the signal under test with preset first threshold and second threshold; an acquiring section that acquires the logical value output from the level comparing section, according to a strobe signal supplied thereto; an expected value comparing circuit that determines whether the logical value acquired by the acquiring section corresponds to a preset expected value; and a threshold control section that sets an upper limit and a lower limit of a voltage of the eye mask to the level comparing section as the first threshold and the second threshold, when an eye mask test is performed for determining whether an eye opening of the signal under test is larger than a predefined eye mask. | 12-09-2010 |
| 20100315114 | Semiconductor device with test structure and semiconductor device test method - The invention relates to a semiconductor device comprising a test structure ( | 12-16-2010 |
| 20100315115 | METHOD OF CHARACTERIZING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of characterizing semiconductor device includes providing a silicon-on-insulator (SOI) substrate with at least a body-tied (BT) SOI device and a BT dummy device for measurement, respectively measuring tunneling currents (I | 12-16-2010 |
| 20100315116 | Testing method for a semiconductor integrated circuit device, semiconductor integrated circuit device and testing system - A method that divides semiconductor integrated circuit devices (corresponding to S | 12-16-2010 |
| 20110001508 | SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - In order to reduce the number of electrodes included in test patterns, the semiconductor integrated circuit includes, a plurality of first and second chains, a first common electrode connected to one end of each first chain, a second common electrode connected to one end of each second chain, and a plurality of selection electrodes. Each selection electrode is connected to the other end of any one of the plurality of first chains and to the other end of any one of the plurality of second chains. When a test target chain is selected from the plurality of first chains, a first reference voltage is applied to the first common electrode, a second reference voltage is applied to a target selection electrode that is connected to the test target chain, and a current flowing in the target selection electrode is measured to obtain a resistance value of the test target chain. | 01-06-2011 |
| 20110001509 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor integrated circuit device includes: terminals | 01-06-2011 |
| 20110018572 | SEMICONDUCTOR DEVICE TEST SYSTEM - A semiconductor device test system is disclosed. The semiconductor device test system extends driver- and comparator-functions acting as important functions of a test header to an external part (e.g., a HIFIX board) of the test header, such that it can double the productivity of a test without upgrading the test header. The semiconductor device test system includes a test header for testing a semiconductor device by a test controller, and a HIFIX board for establishing an electrical connection between the semiconductor device and the test header, and including a Device Under Test (DUT) test unit which processes a read signal generated from the semiconductor device by making one pair with a driver of the test header and transmits the processed read signal to the test header. | 01-27-2011 |
| 20110018573 | Semiconductor Device, A Method of Manufacturing A Semiconductor Device and A Testing Method of the Same - A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester. | 01-27-2011 |
| 20110018574 | RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES - Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections. | 01-27-2011 |
| 20110025364 | Test Mode Signal Generating Device - Various embodiments of a test mode signal generating device are disclosed. The device includes first and second test mode signal generating units. The first test mode signal generating unit is configured to receive test address signals to generate a first test mode signal when a first mode conversion signal is enabled. The first test mode signal generating unit is also configured to enable a second mode conversion signal when the test address signals correspond to a first predetermined combination. The second test mode signal generating unit is configured to receive the test address signals to generate a second test mode signal when the second mode conversion signal is enabled. The second test mode signal generating unit is also configured to enable the first mode conversion signal when the test address signals correspond to a second predetermined combination. | 02-03-2011 |
| 20110025365 | Circuit Arrangement and Method for Testing a Reset Circuit - A circuit arrangement ( | 02-03-2011 |
| 20110025366 | TEST DEVICE FOR TESTING TRANSISTOR CHARACTERISTICS IN SEMICONDUCTOR INTEGRATED CIRCUIT - A test device of a semiconductor integrated circuit includes: an oscillation unit including a plurality of oscillation circuits and configured to activate the respective oscillation circuits in response to a test mode signal and output a plurality of oscillation signals; a switching unit configured to extract only an activated signal among the plurality of oscillation signals; a frequency division unit configured to divide a signal outputted from the switching unit at a predetermined division ratio and generate a divided oscillation signal; and a data buffer unit configured to buffer the divided oscillation signal to output through a data pad. | 02-03-2011 |
| 20110043242 | ACQUISITION OF SILICON-ON-INSULATOR SWITCHING HISTORY EFFECTS STATISTICS - A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip. | 02-24-2011 |
| 20110050269 | Method for evaluating semiconductor device - A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved. | 03-03-2011 |
| 20110050270 | CIRCUIT, SYSTEM, AND METHOD FOR DEGRADATION DETECTION - The present invention aims to provide a circuit, system, and method for degradation detection that can accurately evaluate a degradation condition of a transistor without increasing the circuit size. The degradation detection circuit includes a MOS transistor disposed between a power supply (VDD) and a power supply (GND) which has a lower potential than the power supply (VDD), a resistance unit that is connected in series with the MOS transistor and includes slower degradation progress than degradation progress of the MOS transistor, and an output terminal for degradation degree measurement that outputs a voltage at a junction between the MOS transistor and the resistance unit for measuring the degradation degree of the MOS transistor. | 03-03-2011 |
| 20110050271 | TEST APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD USING THE SAME - A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated. | 03-03-2011 |
| 20110057681 | SEMICONDUCTOR TESTING CIRCUIT, SEMICONDUCTOR TESTING JIG, SEMICONDUCTOR TESTING APPARATUS, AND SEMICONDUCTOR TESTING METHOD - A signal processing section included in a semiconductor testing circuit supplies a test signal inputted from a tester via a signal line to a plurality of DUTs and generates a test result by synthesizing response signals transmitted from the plurality of DUTs on the basis of the test signal. A test result output section included in the semiconductor testing circuit makes a voltage level of the test result differ from a voltage level of the test signal inputted and outputs the test result to the tester via the signal line. | 03-10-2011 |
| 20110068818 | SEMICONDUCTOR APPARATUS AND METHOD OF DETECTING CHARACTERISTIC DEGRADATION OF SEMICONDUCTOR APPARATUS - A semiconductor apparatus (IPD) includes a set value storage unit that stores a set value determined based on an initial characteristic value of the IPD, and a detector that detects characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the set value stored in the set value storage unit. Further, a method of detecting characteristic degradation of a semiconductor apparatus (IPD) includes storing a set value determined based on an initial characteristic value of the IPD, and detecting characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the stored set value. | 03-24-2011 |
| 20110074459 | STRUCTURE AND METHOD FOR SEMICONDUCTOR TESTING - An embodiment of a test structure in accordance with the present invention comprises a pair of interdigitated comb portions of a metallization layer present in a recess of an inter-layer dielectric (ILD) formed over a polysilicon heater element. A third portion of the metallization layer comprises a serpentine metal line interposed between the comb portions. Application of force voltages, and detection of sense voltages, at various nodes of the metallization portions allows identification of the following: (1) electromigration of metal in the metallization portions; (2) extrusion of metal from one metallization portion to contact another; (3) breakdown voltage (V | 03-31-2011 |
| 20110080188 | Universal test fixture for high-power packaged transistors and diodes - A universal test fixture for testing and characterization of high-power flange-packaged RF and microwave transistors and diodes includes a precision-machined heat sink having a built-in center cavity with a finger catch on either side of the cavity which uses a plurality of matching modules that are installed in the center cavity and designed as transistor or diode carrier modules to provide mounting for the high-power packaged RF and microwave devices in a wide variety of flange type packages, an adjustable clamping structure connected to a movable arm, and a plurality of non-conductive high temperature pressure clamps. Each carrier module is made of a gold-plated rectangular aluminum block having a center cavity that is machined to the package outline. A non-conductive black-anodized high-temperature resistant pressure clamp machined to the package outline holds the packaged device in the carrier module. When clamped down using the clamping structure, the pressure clamp holds the package leads on a printed circuit board ensuring excellent electrical contact between package leads and circuit traces and surrounding ground planes, obviating soldering and desoldering the leads to the circuit board. The pressure clamp also produces pressure along the device package to hold the packaged device to the carrier module which houses the device and which itself is bolted to the heat sink resulting in excellent thermal contact under the device. | 04-07-2011 |
| 20110084722 | Semiconductor device and test method thereof - A semiconductor device includes a plurality of memory chips arranged in a layered manner, each including a substrate and a memory cell array, and a plurality of current paths provided while penetrating through the memory chips. Each of the memory chips includes a test circuit that reads test data from a corresponding one of the memory cell array and outputs a layer test result signal responding to the test data to a different current path for each of the memory chips. | 04-14-2011 |
| 20110109342 | CROSSTALK SUPPRESSION IN WIRELESS TESTING OF SEMICONDUCTOR DEVICES - An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die. | 05-12-2011 |
| 20110115517 | BUILT-OFF TEST DEVICE AND TEST SYSTEM INCLUDING THE SAME - A built-off test (BOT) device includes a signal processing block, an output selection block and a signal control block. The signal processing block duplicates a test signal to apply a plurality of duplicated test signals to each of a plurality of devices under test (DUTs) through each of corresponding channels, and the signal processing block provides a plurality of decision signals based upon a plurality of test result signals received from each of the DUTs. The output selection block merges the decision signals as a final decision signal or sequentially outputs the decision signals as the final decision signal, in response to an output mode selection signal. The signal control block provides the test signal to the signal processing block or provides the final decision signal externally, in response to a first switching control signal. | 05-19-2011 |
| 20110115518 | System and Method for Use in Functional Failure Analysis by Induced Stimulus - A scanning/imaging system wherein an external stimulus is used for exciting a device under test (DUT). A stimulus source is included for providing a stationary stimulus with a controllable spot size to a device under test (DUT), the controllable spot size covering a portion of the DUT for excitation by the stationary stimulus. A sensor is operable for capturing at least one of a functional response signal and an optical image signal emanating from the DUT portion. A linear positioning device is operable to facilitate scanning of remaining portions of the DUT until a predetermined area thereof has been traversed. A controller is operably coupled to the linear positioning device, stimulus source and the sensor for providing the overall control thereof. | 05-19-2011 |
| 20110128030 | MONITORING OF THE ACTIVITY OF AN ELECTRONIC CIRCUIT - A method and a device for monitoring a digital signal, wherein a first P-channel MOS transistor is placed in degradation conditions of negative bias temperature instability type during periods when the signal to be monitored is in a first state; a first quantity representative of the saturation current of the first transistor is measured when the signal to be monitored switches to a second state; and a detection signal is switched when this first quantity exceeds a threshold. | 06-02-2011 |
| 20110128031 | TEST SYSTEM AND SUBSTRATE UNIT FOR TESTING - A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon. | 06-02-2011 |
| 20110128032 | WAFER FOR TESTING, TEST SYSTEM, AND SEMICONDUCTOR WAFER - Provided is a test wafer that tests a plurality of semiconductor chips that are formed on a semiconductor wafer and that each include an operation circuit and an internal memory. The test wafer comprises a plurality of test circuits that correspond to the plurality of semiconductor chips, supply the operation circuits of the corresponding semiconductor chips with measurement signals, and measure electrical characteristics of signals output by the operation circuits in response to the measurement signals; and a plurality of write circuits that correspond to the plurality of semiconductor chips and each write, to the internal memory of the corresponding semiconductor chip, data corresponding to a measurement result of the corresponding test circuit. | 06-02-2011 |
| 20110140727 | SWITCHING DEVICE FAILURE DETECTION SYSTEM AND METHOD FOR MULTILEVEL CONVERTERS - A multilevel converter includes a plurality of phase legs each having at least two inner switching devices, at least two outer switching devices, at least two clamping diodes, a split DC link and a switching device failure detection circuit. The switching device failure detection circuit includes a logic module for each of the switching devices, a voltage calculation module and a failure detection algorithm. The logic module generates a blocking state logic signal by comparing a switching device voltage and a threshold reference voltage and the voltage calculation module determines an expected voltage blocking state for each of the switching devices based on the gate drive signals of the switching devices and an output current direction. The failure detection algorithm detects a failure condition in any of the switching devices based on the blocking state logic signals and the expected voltage blocking states of the switching devices. | 06-16-2011 |
| 20110140728 | METHOD AND APPARATUS FOR MONITORING VIA'S IN A SEMICONDUCTOR FAB - A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured. | 06-16-2011 |
| 20110140729 | INSPECTION DEVICE - An object of the invention is to provide an inspection device which has a function of preventing electric discharge so that an absorbed current is detected more efficiently. | 06-16-2011 |
| 20110148454 | SEMICONDUCTOR WAFER, SEMICONDUCTOR CIRCUIT, SUBSTRATE FOR TESTING AND TEST SYSTEM - A test system includes a test substrate that transmits/receives signals to/from a semiconductor wafer, and a control apparatus to control the test substrate. The semiconductor wafer includes an external terminal coupled to an external measurement circuit, a plurality of selecting wiring lines provided to receive/transmit signals to/from the corresponding the measuring points, and a selecting section that selects one of the selecting wiring lines and that allows signal transmission between the corresponding measuring point and the external terminal through the selected selecting wiring line. The test substrate includes a measurement circuit that is coupled to the external terminal of the semiconductor wafer and that measures an electrical characteristic of a signal transmitted through the selecting wiring line selected by the selecting section, and a control section that controls which one of the measurement wiring lines is to be selected by the selecting section in the semiconductor wafer. | 06-23-2011 |
| 20110148455 | METHOD FOR MEASURING CURRENT, METHOD FOR INSPECTING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND TEST ELEMENT GROUP - An object is to provide a current measurement method which enables a minute current to be measured. To achieve this, the value of a current flowing through an electrical element is not directly measured, but is calculated from a change in potential observed in a predetermined period. The detection of a minute current can be achieved by a measurement method including the steps of applying a predetermined potential to a first terminal of an electrical element comprising the first terminal and a second terminal; measuring an amount of change in potential of a node connected to the second terminal; and calculating, from the amount of change in potential, a value of a current flowing between the first terminal and the second terminal of the electrical element. | 06-23-2011 |
| 20110156742 | Chip Testing Circuit - A chip testing circuit is disclosed. The chip testing circuit uses a judging circuit to switch the connection of the data compressing circuit between data compressing base units which compresses 4 XIOs, so as to obtain testing data by one single interface circuit and to increase the testing throughput. | 06-30-2011 |
| 20110169520 | APPARATUS FOR MEASURING MINORITY CARRIER LIFETIME AND METHOD FOR USING THE SAME - An apparatus for measuring minority carrier lifetime is provided. The apparatus includes a resonant circuit having an inductor and a capacitor and configured to resonate at a measurement frequency. The apparatus also includes a ferromagnetic core having a first portion and a second portion. The first portion defines a gap and can be configured to direct therealong a magnetic field established by the inductor, such that lateral spreading of the magnetic field outside of the first portion is inhibited, and to direct the magnetic field generally uniformly across the gap. The second portion can be configured to direct the magnetic field therealong and, in conjunction with the first portion, into a closed loop. A radiation source can be configured to irradiate an area proximal to the gap defined by the first portion of the ferromagnetic core. | 07-14-2011 |
| 20110175638 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CORE TEST CIRCUIT - A semiconductor circuit inhibiting the increase in the number of elements required to enable core circuit testing and a core test circuit enabling consecutive-pattern testing of a core circuit without increasing the number of terminals are provided. The semiconductor circuit includes a core circuit, a combinational circuit, a scan path for the combinational circuit with the scan path including cascaded scan flip-flops connected to input and output terminals of the combinational circuit, and scan path sharing circuits including multiplexers for allowing output signals of the core circuit to be inputted to the scan flip-flops, and allows a core circuit not included in the combinational circuit to be tested using the scan path for the combinational circuit. The core test circuit is provided with output shift registers for storing and outputting test results of plural test patterns outputted from output terminals of the core circuit to be eventually scanned out from the output shift registers. | 07-21-2011 |
| 20110181315 | Adaptive Device Aging Monitoring and Compensation - Improved device aging monitoring and compensation schemes are presented herein. In particular, embodiments enable quantitative measurement of actual aging experienced by a device up to the instant of measurement, rather than rely on static a priori estimation of aging effects under worst case conditions. As such, embodiments provide adaptive device aging monitoring and compensation schemes. In addition, embodiments allow for aging monitoring and compensation to be performed at a desired granularity, whereby aging monitoring and compensation can be performed at a chip, module, or sub-module level. Further, embodiments inherently compensate for the effects of aging on passive components (e.g., parasitics of interconnect wires, capacitors, etc.) in addition to active device aging. | 07-28-2011 |
| 20110215825 | SYSTEM AND METHOD FOR TEMPERATURE CYCLING - A system and method for non-isothermal temperature cycling (also called Conduction Temperature Cycling) of a semiconductor device. The method includes inserting a semiconductor device into a testing chamber and thermally coupling the semiconductor device to a heating and cooling element via a vacuum holding component. The method further includes heating and cooling a die portion of the semiconductor device with the heating and cooling element and testing the semiconductor device for component failure caused by thermo-mechanical stress induced by the non-isothermal temperature cycling. In one embodiment, the heating and cooling comprises non-isothermal temperature cycling. | 09-08-2011 |
| 20110221466 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE - According to the following disclosure, disclosed is a semiconductor device including: an internal circuit configured to receive and output a signal current; a current mirror unit outputting a copied current corresponding to the signal current; and a test pad from which the copied current is taken out. | 09-15-2011 |
| 20110227599 | SEMICONDUCTOR DEVICE TEST METHOD AND SEMICONDUCTOR DEVICE - A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks. | 09-22-2011 |
| 20110227600 | METHOD OF TESTING SEMICONDUCTOR DEVICE - A method of testing a semiconductor device is provided. In order to provide the same conditions and application of electrical power as a test process in which characteristic functions of a semiconductor device are tested, the number of removal power pins is set. The final number of power pins that can be provided during a normal operation is determined by setting the number of removal power pins. The final number of power pins represents the minimum number of power pins that are requested to be connected for the normal operation of the semiconductor device, and is met by removing a timing margin during the operation of the semiconductor device. Afterwards, a delay test pattern that can be used during a scan mode is applied. When it is determined to be defective by the delay test pattern, a cycle of the delay test pattern is increased. The increased cycle of the delay test pattern may increase the number of switching operations in the delay test pattern or offset ground bouncing caused by excessive current requested per unit time, so that an overkill phenomenon in which a good semiconductor device is determined to be defective can be prevented. | 09-22-2011 |
| 20110248739 | BENDING TEST APPARATUS FOR FLEXIBLE DEVICES - Provided is a bending test apparatus of a flexible device. The bending test apparatus includes: first and second electrode parts disposed in a horizontal direction and loading a flexible device horizontally, wherein the first electrode part is movable in the horizontal direction and the second electrode part is fixed so that the first electrode part horizontally moves toward the second electrode part to apply mechanical stress of the horizontal direction to the flexible device. | 10-13-2011 |
| 20110248740 | STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O - The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths. | 10-13-2011 |
| 20110254579 | SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST SYSTEM - According to an embodiment, a semiconductor test method for performing electrical tests with a plurality of test items on each of the same type of semiconductor devices by semiconductor test equipment is disclosed. The method includes: dividing the plurality of test items into M (M is an integer greater than or equal to 2) test item groups, the M test item groups comprising a test item group that can be performed using a predetermined number of pins of the semiconductor test equipment and M−1 test item groups that can be performed using a certain number of pins of the semiconductor test equipment, the certain number being smaller than the predetermined number; making each pin connection for performing a test of corresponding test item group between the semiconductor test equipment and the M semiconductor devices; and performing tests of each test item group at the same time by the semiconductor test equipment, after making the pin connections. | 10-20-2011 |
| 20110260747 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME - A semiconductor device ( | 10-27-2011 |
| 20110267091 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes an internal operation signal generation circuit configured to generate an internal operation signal in response to a signal applied through a reset signal input pad during a test period. | 11-03-2011 |
| 20110267092 | APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST - A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed. | 11-03-2011 |
| 20110273200 | Fault Current Test Equipment of Direct Current Thyristor Valve - The present invention relates to a test equipment of direct current thyristor valve, and particularly relates to a fault current test equipment of direct current thyristor valve. This present invention equipment includes high voltage low current circuit and low voltage high current circuit, said test equipment includes fault current circuit, said fault current circuit includes resonant circuit, said high voltage low current circuit, low voltage high current circuit and fault current circuit are all connected with the thyristor sample Vt respectively. In his present invention, the thyristor sample is first heated through the high voltage circuit and low voltage high current circuit to reach the stable state. And then shut off the switch and carries out the test using the fault current which is produced by the fault current circuit. This prevents the power system from the short-circuit impact. Further more, the peak current and the current duration of the fault current circuit can be adjusted flexibly by changing the voltage of the adding energy circuit. | 11-10-2011 |
| 20110273201 | High Voltage Thyristor Valve Multi-Injection Test Method - This invention provides a high voltage thyristor valve multi-injection test method, it can meet one way valve and double valve operation test and over current test requirements. It has high equivalence and good flexibility. It includes FACTS double way thyristor valve and normal direct current thyristor valve operation tests and over current test. This method is novel, flexible, can carry out many different test and their mixture test and including the high voltage thyrsor valve different tests. | 11-10-2011 |
| 20110279142 | TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) TEST STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF PERFORMING TDDB TEST USING THE SAME - A time dependent dielectric breakdown (TDDB) test structure of a semiconductor device includes: a first test cell having a first test pattern in which a dielectric layer is formed between two electrodes; a second test cell spaced apart from the first test cell and having a second test pattern in which a dielectric layer is formed between two electrodes; and a barrier region configured to prevent electrical interference from occurring between the first test cell and the second test cell during a TDDB test. | 11-17-2011 |
| 20110285418 | SEMICONDUCTOR DEVICE - A first power-cutoff switch is disposed between a power line and an internal power line dedicated for a circuit block, and has a current supply capacity having the level at which ON-current can protect an external examination environment. A second power-cutoff switch is disposed between a power line and an internal power line, and has a current supply capacity having the level at which ON-current can supply consumed current of the circuit block. A detecting circuit detects that a voltage of the internal power line matches a reference voltage. The first power-cutoff switch is ON/OFF by an operation state of the circuit block. The second power-cutoff switch is ON by detecting the matching of the volumes with the detecting circuit and is OFF by the ON/OFF operation of the first power-cutoff switch. | 11-24-2011 |
| 20110291690 | Apparatus and Method for Testing Non-Contact Pads of a Semiconductor Device to be Tested - The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on to and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening. Whereby, the non-contact pads of the semiconductor device to be tested face but not in physically contact with the testing pads of the active chip, so as to test the proximity communication between the non-contact pads of the semiconductor device and the testing pads of the active chip. | 12-01-2011 |
| 20110291691 | CHIP AND CHIP TEST SYSTEM - According to an example embodiment, a chip includes a plurality of circuit blocks, a power switch unit configured to supply power to the plurality of circuit blocks, and a power switch controller configured to control the power switch unit in response to an external control signal. The external control signal selectively control supply of power to at least one circuit block of the plurality of circuit blocks. | 12-01-2011 |
| 20110291692 | METHOD AND APPARATUS FOR INSPECTING SEMICONDUCTOR USING ABSORBED CURRENT IMAGE - Provided is an apparatus for automatically detecting a failure position on a specified wiring line. The apparatus and a method for automatically detecting the failure position even on a long wiring line by applying a probe and an electron beam onto a sample and using an image of the current absorbed by the sample are provided. The apparatus obtains an absorbed current image, while laterally moving at right angle with the probe applied onto the sample, and based on the obtained absorbed current image, correction is performed by means of both an image shift and a stage. Countermeasures are taken, using a stage not having a sample rotating stage, against factors including a hardware factor of not moving at a correct angle, such as backlash, the wiring line is accurately and continuously displayed even when the apparatus moves to the ends of the long wiring line, and the failure position is detected, while the apparatus automatically reciprocates several times between the both ends of the wiring line. | 12-01-2011 |
| 20110291693 | TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES - Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal. | 12-01-2011 |
| 20110309855 | METHOD AND APPARATUS FOR BYPASSING SILICON BUGS - The present invention provides a method and apparatus for bypassing silicon bugs. One exemplary embodiment of the method includes using a logic element formed on a substrate to detect a predefined trigger condition indicating onset of a functional bug during operation of a semiconductor device formed on the substrate. The method also includes modifying operation of the semiconductor device to avoid onset of the functional bug by taking a predefined action associated with the predefined trigger condition. | 12-22-2011 |
| 20120001651 | FREQUENCY SPECIFIC CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS - Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. | 01-05-2012 |
| 20120019279 | METHOD AND PATTERN CARRIER FOR OPTIMIZING INSPECTION RECIPE OF DEFECT INSPECTION TOOL - A method for optimizing an inspection recipe of a defect inspection tool is described. A substrate having thereon intentional defects and locating patterns beside the intentional defects is provided. The defect inspection tool is used to detect the intentional defects with an inspection recipe and obtain the distribution of undetected or partially detected intentional defects. The locating patterns are utilized to locate the undetected or partially detected intentional defects and thereby determine the type(s) of the undetected or partially detected intentional defects. The inspection recipe is modified according to the type(s) of the undetected or partially detected intentional defects in a manner such that there is a minimal number of undetected or partially detected intentional defects under the inspection of the defect inspection tool. | 01-26-2012 |
| 20120025862 | Test Structure for ILD Void Testing and Conduct Resistance Measurement in a Semiconductor Device - In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored. | 02-02-2012 |
| 20120062266 | SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION - A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection. | 03-15-2012 |
| 20120062267 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INSPECTING THE SAME - A potential of a gate of the transistor of the memory cell is held at a predetermined potential VGM which is between a potential VGL used in normal holding and a threshold of the transistor Vth. When the potential is held for a predetermined period, the memory cell becomes in a similar state in which the memory cell is held at a potential VGL in 10 years. A memory cell, which does not hold data sufficiently at this time, can be judged not to hold data for 10 years in normal use. | 03-15-2012 |
| 20120062268 | METHOD AND DEVICE FOR MEASURING THE RELIABILITY OF AN INTEGRATED CIRCUIT - Electromigration may cause a fault to appear in an integrated circuit located on a semiconductor chip. To detect such a fault, at least one resistive test structure is provided separated from the integrated circuit and located on at least one metallization level of the integrated circuit. During operation of the integrated circuit, the resistive test structure is sensed. Detection of a voltage difference between two points of the resistive test structure is indicative of a fault. | 03-15-2012 |
| 20120074980 | SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES - An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters. | 03-29-2012 |
| 20120081141 | On-Chip Delay Measurement Through a Transistor Array - Methods and apparatus are provided for measuring a delay through one or more transistors in an array of transistors. The delay through one or more transistors in an array of transistors is measured by selecting one of the transistors in the array; and applying a clock signal to the selected transistor, wherein an output of the selected transistor is applied to a first input of a logic gate having at least two inputs and wherein a second clock signal based on the clock signal is applied to a second input of the logic gate, and wherein an output of the logic gate indicates a difference in arrival times of the signals at the two inputs. In one variation, a clock signal is applied to the selected transistor and a variable delay circuit; and an output of the selected transistor is applied to a data input of a latch having a clock input and a data input while an output of the variable delay circuit is applied to a clock input of the latch. The delay applied by the variable delay circuit to the clock signal is adjusted until a predefined transition is detected in an output of the latch. If the delay is measured through a plurality of transistors in the array, the delay variation among the plurality of transistors can be obtained. | 04-05-2012 |
| 20120092037 | METHOD AND DEVICE FOR TESTING A THIN FILM TRANSISTOR - A method and device for testing a thin film transistor (TFT) provided on an array substrate are provided in an embodiment. The method comprises determining periods and signal amplitudes in each period of the gate electrode test voltage signal and the source-drain-electrode test voltage signal corresponding to the TFT characteristics to be tested, wherein both the gate electrode test voltage signal and the source-drain-electrode test voltage signal are alternative current signals; according to the period and the signal amplitude in each period of the gate electrode test voltage signal and those of the source-drain-electrode test voltage signal, applying the gate electrode test voltage signal to a gate electrode of the TFT to be tested, and applying the source-drain-electrode test voltage signal across source and drain electrodes of the TFT; and obtaining the TFT output signals related to the TFT characteristics to be tested. | 04-19-2012 |
| 20120105093 | SEMICONDUCTOR APPARATUS AND METHOD OF TESTING AND MANUFACTURING THE SAME - A semiconductor apparatus includes: a semiconductor chip, wherein a conductive layer is formed at one side of the semiconductor chip and one or more of probe pads are formed at the other side thereof; a plurality of through-silicon vias (TSVs), wherein one side of each of the plurality of TSVs is coupled to the conductive layer and the other side of one or more of the plurality of TSVs is coupled to the probe pad; a plurality of latch units each configured to be assigned to the plurality of corresponding TSVs and store a test signal, wherein the test signal is inputted via the probe pad and is transferred via the plurality of corresponding TSVs to the plurality of assigned latch units, respectively; and a signal combination unit configured to combine a plurality of signals stored in the plurality of latch units to output the result as an error detection signal. | 05-03-2012 |
| 20120112782 | METHOD FOR PREDICTING TOLERABLE SPACING BETWEEN CONDUCTORS IN SEMICONDUCTOR PROCESS - A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Δd to d−Δd wherein d is the standard spacing and Δd| 05-10-2012 | |
| 20120126845 | CONNECTOR AND SEMICONDUCTOR TESTING DEVICE INCLUDING THE CONNECTOR - A connector includes a first terminal. The first terminal includes a movable portion, and the movable portion has, on its tip side, a contact portion located on a course C of a case assembly. Further, the first terminal includes a fixed portion restricted from moving and located on a base side of the movable portion. The movable portion is elastically deformable to incline toward a side surface of an insertion hole while using the fixed portion as a fixed point. Further, the movable portion includes a hit portion between the contact portion and the fixed portion. The hit portion is located apart from the side surface of the insertion hole, and the hit portion is provided capable of hitting, midway during inclining of the movable portion toward the side surface of the insertion hole, against the side surface of the insertion hole. | 05-24-2012 |
| 20120133386 | MAGNETIC FIELD SIMULATOR FOR TESTING SINGULATED OR MULTI-SITE STRIP SEMICONDUCTOR DEVICE AND METHOD THEREFOR - A system for testing a magnetic sensor has a plurality of coils, wherein the coils are positioned along perpendicular planes. A magnetic field is generated along each of the perpendicular planes when a current is sent to each of the plurality of coils. | 05-31-2012 |
| 20120133387 | RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES - Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections. | 05-31-2012 |
| 20120133388 | TRANSISTOR POWER SWITCH DEVICE AND METHOD OF MEASURING ITS CHARACTERISTICS - A transistor power switch device comprising an array of vertical transistor elements for carrying current between first and second faces of a semiconductor body. The device also comprises a semiconductor monitor element comprising first and second semiconductor monitor regions in the semiconductor body and a monitor conductive layer distinct from the current carrying conductive layer of the transistor array. The semiconductor monitor element presents semiconductor properties representative of the transistor array. Characteristics of the semiconductor monitor element are measured as representative of characteristics of the transistor array. Source metal ageing of a transistor power switch device is monitored by measuring and recording a parameter which is a function of a sheet resistance of the monitor conductive layer when the transistor power switch device is new and comparing it with its value after operation of the device. A measured current is applied between a first location on an elongate strip element of the monitor conductive layer and a first location on one of a pair of lateral extensions of the strip, and the corresponding voltage developed between a second location on the elongate strip element and the other of said pair of lateral extensions is measured. | 05-31-2012 |
| 20120146682 | YIELD ENHANCEMENT FOR STACKED CHIPS THROUGH ROTATIONALLY-CONNECTING-INTERPOSER - A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield. | 06-14-2012 |
| 20120153984 | METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE - A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing. | 06-21-2012 |
| 20120187974 | Dual Stage Voltage Ramp Stress Test for Gate Dielectrics - A testing system for testing the integrity of a gate dielectric includes a testing apparatus, the testing apparatus including a test probe configured to contact and provide a voltage across the gate dielectric and to measure a current passing through the gate dielectric. The testing system also includes a computing device coupled to the testing apparatus an causing the testing apparatus to apply a constant voltage as part of a first test to the gate dielectric through the test probe until a first predetermined current is measured passing through the gate dielectric and to apply an increasing voltage to the gate dielectric after the first predetermined current is measured. | 07-26-2012 |
| 20120187975 | SEMICONDUCTOR DEVICE EVALUATION APPARATUS AND SEMICONDUCTOR DEVICE EVALUATION METHOD - A semiconductor device evaluation apparatus includes a current measurement portion that measures a current value at multiple times included in a period from the beginning of application of a voltage to a semiconductor device to a steady state of the current value flowing through the semiconductor device; a period division portion that divides the period into a first period and a second period later than the first period and finds a curve approximately representing a temporal change in a current value measured at time included in the second period so that a difference between a current value measured at the time included in the first period and a current value found by extrapolating the curve at the same time becomes greater than a specified threshold value; and a current estimation portion that estimates a current value flowing through the semiconductor device at the start time. | 07-26-2012 |
| 20120187976 | METHOD FOR TESTING TRAP DENSITY OF GATE DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE HAVING NO SUBSTRATE CONTACT - A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges. After that, the following steps are repeated sequentially to form a loop by changing the bias settings: 1) carriers flow into the channel through the source and the drain to form an inversion layer, and a portion of carriers are confined by the traps in the gate dielectric layer; 2) carriers of the inversion layer flow back to the source and the drain respectively, whereas the carriers confined by the traps in the gate dielectric layer do not flow back to the channel; 3) carriers confined by the traps in the gate dielectric layer flow out through the drain terminal only; and the trap density of the gate dielectric layer are calculated according to the period of the loop, the size of the channel of the device, and DC currents at the source and the drain. The method is simple and effective and is easy to setup the instruments with a low cost. The method is applicable to be used in testing traps in the gate dielectric layer of the devices that have no substrate contact, especially the surrounding-gate device. | 07-26-2012 |
| 20120200312 | Element Substrate, Inspecting Method, and Manufacturing Method of Semiconductor Device - A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a semiconductor layer of the invention has a closed-loop circuit in which an antenna coil and a semiconductor element are connected in series, and a surface of an area over which the circuit is formed is covered with an insulating film. By using such a circuit, a contactless inspection can be carried out. Further, a ring oscillator can be substituted for the closed-loop circuit. | 08-09-2012 |
| 20120212250 | Semiconductor element testing system having air filter - A semiconductor element testing system having an air filter includes a testing apparatus, a first hollow frame, a fan assembly, a second hollow frame, and an air filter. The testing apparatus includes a housing having an opening. The first hollow frame is arranged on the housing and includes a flange, a bottom surface, and a side portion, wherein a plurality of hooks are fixedly arranged on the side portion. The fan assembly is fixed on the first hollow frame such that a forced airflow can be supplied toward inside of the housing. The second hollow frame includes an outer side portion fixedly arranged with a plurality of loop fasteners corresponding to the plural hooks. The air filter covers on the opening of the housing. Thereby, floating particles of the testing system can be reduced so as to lower the possibility of contamination for chips. | 08-23-2012 |
| 20120212251 | SIGNAL TRANSMISSION CIRCUIT DEVICE, SEMICONDUCTOR DEVICE, METHOD AND APPARATUS FOR INSPECTING SEMICONDUCTOR DEVICE, SIGNAL TRANSMISSION DEVICE, AND MOTOR DRIVE APPARATUS USING SIGNAL TRANSMISSION DEVICE - Disclosed is a signal transmission circuit device ( | 08-23-2012 |
| 20120235701 | Method for Accelerated Lifetesting of Large Area OLED Lighting Panels - A method for accelerated life testing of organic devices, and in particular large area organic emissive devices, is provided. The first method comprises obtaining one or more individual organic emissive devices, each having a first organic stack comprising one or more organic layers. The lifetime of each of the one or more individual organic emissive devices is measured at one or more temperatures at a non-heating current density. Based upon the measured lifetimes at the non-heating current density of the one or more devices, the device lifetime is determined for a selected luminance. An organic emissive panel is also obtained having a second organic stack that consists essentially of the one or more organic layers of the first organic stack. The junction temperature of the organic emissive panel is then determined at a heating current density. Based upon the junction temperature and the device lifetime of the one or more individual organic emissive devices at the selected luminance, the expected lifetime of the organic emissive panel is then determined at the heating current density. | 09-20-2012 |
| 20120235702 | SPLIT GATE STRUCTURE AND METHOD OF USING SAME - A method comprises providing first and second semiconductor devices. Each device comprises a transistor having a split gate electrode including first and second gate portions. Each device has a respective ratio between an area of its first gate portion and a sum of areas of its first and second gate portions. For each device, a stress voltage is applied to the first gate portion, but not to the second gate portion. For each device, the first and second gate portions are biased with a common voltage, and data are collected indicating a respective degradation for each device due to the stress voltage. The degradation has a component due to time dependent dielectric breakdown (TDDB) and a component due to bias temperature instability. From the collected data extrapolation determines the degradation component due to TDDB. | 09-20-2012 |
| 20120242365 | SYSTEM FOR DETECTING A FAILURE ASSOCIATED WITH AN INVERTER OR ASSOCIATED MACHINE - An inverter comprises a first pair of semiconductor devices with switched terminals that are coupled in series between a positive terminal and a negative terminal of a direct current bus. An analog interface adjusts a voltage levels at measurement nodes associated with control terminals of the semiconductor devices. An analog-to-digital converter has analog inputs for receiving the adjusted voltage levels of the measurement nodes and outputting corresponding digital count data for each measurement node. A data processor is adapted to detect the fault or absence of a fault in the inverter based on the conformity of the digital count to one or more reference ranges stored in a data storage device for corresponding switch states of the semiconductor devices. | 09-27-2012 |
| 20120268159 | METHOD OF DETECTING DEFECTS IN A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE USING THE SAME - A method of detecting a defect of a semiconductor device includes forming test patterns and unit cell patterns in a test region a cell array region of a substrate, respectively, obtaining reference data with respect to the test patterns by irradiating an electron beam into the test region, obtaining cell data by irradiating the electron beam into the cell array region, and detecting defects of the unit cell patterns by comparing the obtained cell data with the obtained reference data. | 10-25-2012 |
| 20120274348 | TEST CIRCUIT AND METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via receives an input voltage. The voltage driving unit is connected to the through via to receive the input voltage, changes a level of the input voltage in response to a test control signal, and generates a test voltage. The determination unit compares the input voltage with the test voltage to outputs a resultant signal. | 11-01-2012 |
| 20120293196 | TEST KEY STRUCTURE FOR MONITORING GATE CONDUCTOR TO DEEP TRENCH MISALIGNMENT AND TESTING METHOD THEREOF - The disclosure provides a test key structure for monitoring gate conductor to deep trench misalignment and a testing method thereof. The test key structure for monitoring gate conductor to deep trench misalignment includes: a deep trench capacitor structure comprising a plurality of parallel deep trench capacitor lines and a deep trench capacitor connect; a buried strap out-diffusion adjacent to a first side of the deep trench capacitor line; a first gate conductor structure comprising a plurality of parallel first gate conductor lines and a first gate conductor connect, wherein each first gate conductor line is disposed directly over the corresponding deep trench capacitor line; and a second gate conductor structure comprising a plurality of parallel second gate conductor lines and a second gate conductor connect, wherein the first gate conductor lines are electrically connected to each other via the second gate conductor connect, and wherein the first gate conductor lines and the second gate conductor lines are parallel to each other, and the first gate conductor lines and the second gate conductor lines are arranged alternately. | 11-22-2012 |
| 20120306526 | SHUTTLE PLATE HAVING POCKETS FOR ACCOMODATING MULTIPLE SEMICONDUCTOR PACKAGE SIZES - An input/output shuttle plate includes a metal plate having a plurality of pockets. The plurality of pockets have a bottom, a sidewall portion and a pocket depth. A first seating surface at a first pocket depth (d | 12-06-2012 |
| 20120319718 | SIGNAL TRANSMISSION APPARATUS AND SEMICONDUCTOR TEST APPARATUS USING THE SAME - The semiconductor test apparatus includes a pin electronics unit. The pin electronics unit includes a driver configured to generate a test signal to be applied to a semiconductor device and a comparator configured to receive a response signal output from the semiconductor device and to convert the response signal into a digital signal. A first line is connected between the driver and a connector to which the external cable is connected. A second line diverges from the connector side of the first line. A probing unit is connected between the first and second lines, and is configured to at least reduce distortion of a signal on the first line to be transmitted to the second line. A divergence point at which the second line diverges from the first line is located outside the pin electronics unit near the connector. | 12-20-2012 |
| 20120319719 | SEMICONDUCTOR DEVICE AND TEST METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device has a first driving circuit inputting first data; a first gate circuit for the first data to pass therethrough; a first holding circuit holding the first data from the first gate circuit; a logic circuit carrying out a logic operation on the first data from the first holding circuit and outputting second data; a second driving circuit for inputting the second data from the logic circuit; a second gate circuit for the second data from the second driving circuit to pass therethrough; a second holding circuit holding the second data from the second gate circuit; and a power supply circuit supplying a first power supply voltage to the first and second gate circuits, the first and second holding circuits and the logic circuit, and supplying a second power supply voltage higher than the first power supply to the first and second driving circuits. | 12-20-2012 |
| 20120326744 | ACTIVE-MATRIX SUBSTRATE, ACTIVE-MATRIX TESTING METHOD, DISPLAY PANEL, AND DISPLAY PANEL MANUFACTURING METHOD - An active-matrix substrate includes: a substrate; gate lines disposed on the substrate; source lines disposed on the substrate in a direction that crosses the gate lines; a first terminal provided for each of data line blocks obtained by grouping every m-lines (m being an integer greater than or equal to 2) of the source lines into a block; a first selection circuit provided for each of the data line blocks, for causing conduction between the first terminal and at least one source line selected from among the m source lines; a second terminal provided for every n-blocks (n being an integer greater than or equal to 2) of the data line blocks; and a second selection terminal provided for every n-blocks of the data line blocks, for causing conduction between the second terminal and at least one source line selected from among the m×n source lines. | 12-27-2012 |
| 20130009663 | CRACK DETECTION LINE DEVICE AND METHOD - A crack detection line device and a method are disclosed. An embodiment comprises a semiconductor device comprising a crack detection line within a chip, the crack detection line surrounding an inner area of the chip, wherein the crack detection line comprises a first terminal and a second terminal. The semiconductor device further comprises a test circuit connected to the first terminal and the second terminal, the test circuit configured to measure a signal over the crack detection line and an output terminal, the output terminal connected to the test circuit and configured to provide a measured signal. | 01-10-2013 |
| 20130015876 | APPARATUS AND METHOD FOR MEASURING DEGRADATION OF CMOS VLSI ELEMENTSAANM LAI; Fang-Shi JordanAACI Chia YiAACO TWAAGP LAI; Fang-Shi Jordan Chia Yi TWAANM LU; Chih-ChengAACI Tainan CityAACO TWAAGP LU; Chih-Cheng Tainan City TWAANM LIN; Yung-FuAACI Hsinchu CityAACO TWAAGP LIN; Yung-Fu Hsinchu City TWAANM HSUEH; Hsu-FengAACI Tainan CityAACO TWAAGP HSUEH; Hsu-Feng Tainan City TWAANM CHANG; Chin-HaoAACI Hsinchu CityAACO TWAAGP CHANG; Chin-Hao Hsinchu City TWAANM WENG; Cheng YenAACI Hsinchu CityAACO TWAAGP WENG; Cheng Yen Hsinchu City TWAANM MHALA; Manoj M.AACI HsinchuAACO TWAAGP MHALA; Manoj M. Hsinchu TW - The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages. | 01-17-2013 |
| 20130015877 | METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR DEVICEAANM Shao; Jhih JieAACI Toufen TownshipAACO TWAAGP Shao; Jhih Jie Toufen Township TWAANM Huang; Szu-ChiaAACI Hsinchu CityAACO TWAAGP Huang; Szu-Chia Hsinchu City TWAANM Chung; Tang-HsuanAACI Kaohsiung CityAACO TWAAGP Chung; Tang-Hsuan Kaohsiung City TWAANM Tseng; Huan ChiAACI Hsinchu CityAACO TWAAGP Tseng; Huan Chi Hsinchu City TW - The present disclosure provides a method for testing a semiconductor device. The method includes providing a testing unit and an electronic circuit coupled to the testing unit and applying a first electrical signal to the testing unit. The method includes sweeping a second electrical signal across a range of values, the second electrical signal supplying power to the electronic circuit, wherein the sweeping is performed while a value of the first electrical signal remains the same. The method includes measuring a third electrical signal during the sweeping, the measured third electrical signal having a range of values that each correspond to one of the values of the second electrical signal. The method includes adopting an optimum value of the second electrical signal that yields a minimum value of the third electrical signal. The method includes testing the testing unit while the second electrical signal is set to the optimum value. | 01-17-2013 |
| 20130027075 | METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR DEVICE - The present disclosure provides an apparatus testing a semiconductor device. The apparatus includes a plurality of testing pads. The apparatus includes a plurality of testing units. The apparatus includes a switching circuit coupled between the testing pads and the testing units. The switching circuit contains a plurality of switching devices. The apparatus includes a control circuit coupled to the switching circuit. The control circuit is operable to establish electrical coupling between a selected testing unit and one or more of the testing pads by selectively activating a subset of the switching devices. | 01-31-2013 |
| 20130033284 | DISGUISING TEST PADS IN A SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads. | 02-07-2013 |
| 20130049789 | DIE HAVING WIRE BOND ALIGNMENT SENSING STRUCTURES - A semiconductor die includes a substrate having a topside including active circuitry having an array of bond pads thereon separated by gaps including a minimum gap. At least a portion of the array of bond pads are connected to nodes in the active circuitry. At least one wire bond alignment sensing structure includes a first bond pad selected from the array of bond pads, and a guard element positioned along at least a portion of the first bond pad. The guard element is spaced apart by a distance shorter than the minimum gap from the first bond pad. | 02-28-2013 |
| 20130049790 | Electrical Characterization for a Semiconductor Device Pin - Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display. | 02-28-2013 |
| 20130057312 | SYSTEM AND METHOD FOR ELECTRICAL TESTING OF THROUGH SILICON VIAS (TSVs) - An embodiment of a testing system for carrying out electrical testing of at least one first through via extending, at least in part, through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the first through via and to electrical-connection elements carried by the first body for electrical connection towards the outside; the first electrical test circuit enables detection of at least one electrical parameter of the first through via through the electrical-connection elements. | 03-07-2013 |
| 20130057313 | PULSE VOLTAGE AGE ACCELERATION OF A LASER FOR DETERMINING RELIABILITY - A method of accelerating the aging of a laser to thereby determine the reliability of the laser. The method includes an act of providing a laser die for reliability testing, an act of applying a plurality of short signal pulses to the laser die so as to simulate the aging of the laser die, and an act of ascertaining the reliability of the laser die based on its response to the plurality of short signal pulses. | 03-07-2013 |
| 20130063175 | Semiconductor Device Components and Methods - Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end. | 03-14-2013 |
| 20130063176 | TEST CIRCUITS AND CURRENT PULSE GENERATOR FOR SIMULATING AN ELECTROSTATIC DISCHARGE - This invention is an electrostatic discharge (ESD) testing circuit that can deliver current pulses to a component under test (CUT) with controlled impedance. Generated current pulses simulating ESD events, such as those compliant to the European International Electrotechnical Commission IEC 61000-4-2 standard, can be delivered to the CUT with low distortion through a constant impedance electrical path, such as a combination of cables and controlled impedance conductors of printed wiring boards and wafer probes compatible with packaged IC devices, assemblies, and wafers, plus an impedance controlling series resistance. The current pulse can be delivered to the CUT with various forcing impedances. Measurements of the current passing through the CUT can be made. | 03-14-2013 |
| 20130082730 | Passive Probing of Various Locations in a Wireless Enabled Integrated Circuit (IC) - Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit. | 04-04-2013 |
| 20130082731 | SWITCHING MATRIX AND TESTING SYSTEM FOR SEMICONDUCTOR CHARACTERISTIC MEASUREMENT USING THE SAME - A switching matrix includes a plurality of input ports, a plurality of output ports, a plurality of switching devices configured to open and close, an electrical connection between the input ports and the output ports, and an electrical sensor configured to generate a signal by measuring a predetermined electrical property of the electrical connection, the open and close of switching devices is pre-determined by status read from the electrical sensor. | 04-04-2013 |
| 20130088253 | Methods for Testing Manufactured Products - The problem of high test cost of manufactured goods can be partially solved by lowering the percentage of the goods to be tested methodically while keeping the total defective portion of the goods expressed in DPPM below a preset target value. The method includes identifying a first test that is capable of screening out enough parts that would fail a second test so that the portion of the parts to be tested second test can be reduced. The number of parts screened out by the first test determines if the reduced testing scheme would violate the preset DPPM target value. | 04-11-2013 |
| 20130088254 | METHOD FOR TESTING INTEGRATED CIRCUITS WITH HYSTERESIS - A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC. | 04-11-2013 |
| 20130093454 | TESTING AND REPAIRING APPARATUS OF THROUGH SILICON VIA IN STACKED-CHIP - A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector. | 04-18-2013 |
| 20130120018 | Test Structure and Method of Testing Electrical Characteristics of Through Vias - A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV. | 05-16-2013 |
| 20130141134 | Systems and Methods for Sensing Signals Communicated with a Host Device or on an Interface of Plug-In Card when There is Lack of Access to Sensing Points - A circuit system for testing a chip is provided. The circuit system includes a first layer coupled with a plurality of ground communication mediums. Each ground communication medium facilitates communication of a ground signal. The circuit system includes a second layer coupled with a first integrated circuit chip. The second layer is coupled with a plurality of radio frequency (RF) communication mediums. The RF communication mediums facilitate communication of RF signals. The first integrated circuit chip communicates via one of the RF signals and the ground signal with a second integrated circuit chip. The first and second layers are used to probe the RF signals and the ground signal. | 06-06-2013 |
| 20130147509 | TEST PATTERN OF SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING TEST PATTERN AND METHOD OF TESTING SEMICONDUCTOR DEVICE BY USING TEST PATTERN - A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts. | 06-13-2013 |
| 20130162282 | SEMICONDUCTOR DEVICE HAVING POTENTIAL MONITORING TERMINAL TO MONITOR POTENTIAL OF POWER-SUPPLY LINE - Disclosed herein is a device that includes an internal circuit, a first terminal supplied with a first voltage, a first power-supply line coupled between the first terminal and the internal circuit, a potential monitoring terminal, and a first switch coupled between the internal power-supply line and the potential monitoring terminal. | 06-27-2013 |
| 20130169307 | CONTACT RESISTANCE TEST STRUCTURE AND METHOD SUITABLE FOR THREE-DIMENSIONAL INTEGRATED CIRCUITS - A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test structure are all predicated upon two parallel conductor lines (or multiples thereof) that are contacted by one perpendicular conductor line absent a via interposed there between. The test structure and related methods are applicable within the context of three-dimensional integrated circuits. | 07-04-2013 |
| 20130200919 | Method And Apparatus For Determining At Least One Operating Parameter Of A Thermoelectric System In A Vehicle - A method is provided for determining at least one operating parameter of a thermoelectric system in a vehicle, wherein the thermoelectric system comprises an energy conversion device having at least one photovoltaic element for converting thermal radiation, which is emitted by a heat source of the vehicle, into electrical energy. The method includes measuring an electrical power of the photovoltaic device, and determining an operating parameter of the thermoelectric system based on the measured electrical power of the photovoltaic device. | 08-08-2013 |
| 20130207685 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of semiconductor chips coupled to one another through vias, wherein a lowermost semiconductor chip of the plurality of semiconductor chips is configured to generate a first test pulse signal and transmit the first test pulse signal through the via, an uppermost semiconductor chip of the plurality of semiconductor chips is configured to generate a second test pulse signal while substantially maintaining a time difference with the first test pulse signal, and to transmit the second test pulse signal through the via, and the plurality of semiconductor chips are configured to generate test result signals for determining whether the vias are defective in response to the first test pulse signal and the second test pulse signal. | 08-15-2013 |
| 20130214810 | METHOD FOR TESTING DENSITY AND LOCATION OF GATE DIELECTRIC LAYER TRAP OF SEMICONDUCTOR DEVICE - Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices. | 08-22-2013 |
| 20130222006 | APPARATUS FOR MONITORING OPERATING PARAMETERS OF INTEGRATED CIRCUITS AND INTEGRATED CIRCUIT WITH OPERATING PARAMETER MONITORING - A device for monitoring operating parameters of integrated circuits. A signal is generated at least at one output of a comparison element by comparing switching states of input signals at the at least two inputs of the comparison element, which signal indicates that the at least one operating parameter has fallen below or has exceeded a predefined threshold. The two input signals are generated by at least two operating parameter-dependent devices, and the switching behavior thereof is subject to a time delay depending on the current value of the at least one operating parameter. A predefined time delay has a value such that when the predefined threshold of the operating parameter is exceeded, one of the input signals changes its switching state at the times predefined for the comparison element by the clock signal on the basis of the time delay. | 08-29-2013 |
| 20130249589 | INTERPOSER AND ELECTRICAL TESTING METHOD THEREOF - An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer. | 09-26-2013 |
| 20130249590 | TSV Testing Using Test Circuits and Grounding Means - This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure. | 09-26-2013 |
| 20130257472 | ELECTRICAL CHARACTERIZATION OF SEMICONDUCTOR MATERIALS - A method for characterizing the electronic properties of a semiconductor sample by exploiting transients in measured photoconductance, the transients being induced by illuminating the semiconductor sample with a small probing illumination that is superimposed over a larger background illumination. In one embodiment, a pulse-type probing illumination is utilized, with either the intensity of the probing illumination being gradually reduced or the intensity of the background illumination being gradually increased until the measured photoconductance rise and decay in the sample are substantially exponential. In another embodiment, a continuous probing illumination with a sinusoidally-modulated intensity is utilized, the modulated intensity of the probing illumination being gradually adjusted until the measured photoconductance is linearly dependent thereupon. | 10-03-2013 |
| 20130265078 | METHOD OF MEASURING A SILICON THIN FILM, METHOD OF DETECTING DEFECTS IN A SILICON THIN FILM, AND SILICON THIN FILM DEFECT DETECTION DEVICE - A method of measuring conductivity of a silicon thin film is provided. By the method, a capacitive sensor is positioned over a silicon thin film sample with an air-gap between the sensor and the sample, a size of the air-gap is measured using the capacitive sensor while an excitation light source module is turned off, an excitation light is illuminated on the silicon thin film sample by turning on the excitation light source module, where the excitation light is an ultraviolet light, a conductivity change of the silicon thin film sample is measured using the capacitive sensor, and a measurement error due to a deviation of the air-gap is eliminated by normalizing the conductivity change based on a measurement result of the size of the air-gap. | 10-10-2013 |
| 20130285694 | THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE - A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region. | 10-31-2013 |
| 20130293255 | METHOD FOR TESTING THROUGH-SILICON-VIA - A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range. | 11-07-2013 |
| 20130300450 | TEST DEVICE AND TEST SYSTEM OF SEMICONDUCTOR DEVICE AND TEST METHOD FOR TESTING SEMICONDUCTOR DEVICE - A test device of a semiconductor device for testing a semiconductor device including a plurality of interface pads includes a plurality of coupling units, each configured to be coupled to a corresponding one of the plurality of interface pads, a channel configured to be coupled to the plurality of coupling units, a voltage generating unit configured to generate a test voltage applied to the channel, and a current measuring unit configured to measure a current that flows on the channel in response to the test voltage. | 11-14-2013 |
| 20130314119 | TESTING STRUCTURE AND METHOD OF USING THE TESTING STRUCTURE - A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually. | 11-28-2013 |
| 20130321022 | METHODS AND APPARATUS FOR TESTING INACCESSIBLE INTERFACE CIRCUITS IN A SEMICONDUCTOR DEVICE - A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion. | 12-05-2013 |
| 20130328588 | TESTING CIRCUIT AND PRINTED CIRCUIT BOARD USING SAME - A testing circuit for testing proper connections between pins and corresponding circuits within an integrated circuit includes a pin selection module. The pin selection module includes a plurality of input pins, an output pin, and a control pin. The pin selection module selectively connects one of the input pins to the output pin based upon a control signal from the control pin. A voltage-dividing module includes an input end to receive a test voltage, an output end connected with the output pin of the pin selection module, and a voltage-dividing element connected between the input end and the output end. A determination module receives an output voltage from the output end, and determines whether the voltage of the output end falls into one of several predetermined voltage ranges, and outputs a result accordingly. | 12-12-2013 |
| 20140002126 | PIN REMOVAL MODE SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME | 01-02-2014 |
| 20140002127 | Method and Apparatus for Testing a Semiconductor Device | 01-02-2014 |
| 20140009185 | SEMICONDUCTOR DEVICE AND FAULT DIAGNOSIS SYSTEM - Provided is a semiconductor device capable of performing fault detection on a circuit executing an AD conversion operation during the AD conversion operation. The semiconductor device includes an analog to digital conversion unit that converts a second analog signal into a first digital signal, in which the second analog signal is obtained by adding a first analog signal and an offset signal with a signal band different from the first analog signal, a signal extraction unit that extracts from the first digital signal a second digital signal corresponding to the signal band of the offset signal, and a fault detection unit that detects a fault in the analog to digital conversion unit based on the second digital signal and a setting value that is set upon generating the offset signal. | 01-09-2014 |
| 20140043057 | SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF - A semiconductor apparatus includes a test voltage application unit, a first pad and a second pad. The test voltage application unit is configured to apply a test voltage to first and second TSVs in response to a test mode signal. The first pad is configured to output a first test signal outputted from the first TSV. And the second pad is configured to output a second test signal outputted from the second TSV. | 02-13-2014 |
| 20140043058 | SEMICONDUCTOR MODULE - A semiconductor module is provided in a power system of an apparatus. The semiconductor module includes a semiconductor switch, a voltage applying device configured to apply a first voltage that is equal to or higher than a rated voltage of the apparatus to the semiconductor switch in an off-state in a case where the apparatus is not in practical use, and a leak detecting circuit configured to detect a leak current from the semiconductor switch. The rated voltage of the apparatus is a rated voltage when the apparatus is in practical use. | 02-13-2014 |
| 20140049283 | METHOD AND APPARATUS FOR DETECTING SEMICONDUCTOR DEVICE PROPERTY - A method for detecting a semiconductor device property is provided. First, a semiconductor device is provided. Thereafter, a detecting current is applied and the semiconductor device is heated, and temperatures and voltages of the semiconductor device are measured, so as to establish a relationship between the temperatures and the voltages of the semiconductor device. Accordingly, a temperature sensitive parameter (TSP) is calculated. An apparatus for detecting a semiconductor device property is also provided. | 02-20-2014 |
| 20140049284 | TEST DEVICE, SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF - A test device for testing a semiconductor device including a TSV may comprise a ring oscillator including a plurality of inverters, a switch selectively connecting an output node of an inverter of the plurality of inverters and the TSV, and a controller controlling the switch. | 02-20-2014 |
| 20140062520 | DISPLAY DEVICE AND MOTHER SUBSTRATE - A display device is disclosed. The display device has a display area for displaying images and a non-display area neighboring the display area. The display device includes a test element group (TEG) including a plurality of test pads provided in the non-display area and having different shapes. | 03-06-2014 |
| 20140062521 | WIRING DEFECT INSPECTING METHOD, WIRING DEFECT INSPECTING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A wiring defect inspecting method in accordance with the present invention comprises: obtaining a resistance of a short-circuited path of a semiconductor substrate; applying a voltage, which is specified on the basis of the resistance obtained, to the semiconductor substrate having a defect portion so as to cause the defect portion to generate heat; and capturing, with use of an infrared camera, an image of the semiconductor substrate whose temperature has increased due to the heat generated from the defect portion. | 03-06-2014 |
| 20140091829 | SEMICONDUCTOR DEVICE, APPARATUS OF ESTIMATING LIFETIME, METHOD OF ESTIMATING LIFETIME - According to one embodiment, a semiconductor device includes a circuit board, a plurality of semiconductor chips stacked above the circuit board, first and second bumps, third and fourth bumps, and first and second detection units. The first and second bumps are provided in either a gap between the circuit board and the semiconductor chip or a gap between the two semiconductor chips. The third and fourth bumps are provided in any of gaps other than the gap in which the first and second bumps are provided. The first detection unit is electrically connected to the first bump to detect damage of the first bump and to generate a first signal indicating the damage of the first bump. The second detection unit is electrically connected to the third bump to detect damage of the third bump and to generate a second signal indicating the damage of the third bump. | 04-03-2014 |
| 20140091830 | TEST APPARATUS - A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values. | 04-03-2014 |
| 20140097863 | TEST METHOD AND TEST ARRANGEMENT - A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell. | 04-10-2014 |
| 20140097864 | Semiconductor Device Test Structures and Methods - Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer. | 04-10-2014 |
| 20140097865 | CIRCUIT BOARD HAVING BYPASS PAD - An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided. | 04-10-2014 |
| 20140111241 | OPTICAL TESTING OF A MULTI QUANTUM WELL SEMICONDUCTOR DEVICE - A pump light pulse is generating a strain pulse in a sample that includes quantum wells. A signal is measured using a probe light pulse. The probe light pulse is delayed in relation to the pump light pulse. The signal derives from a change in an optical property of the sample, which optical property responds to the generated strain pulse. One may deduce parameters of interest of the sample, including the quantum wells, from the characteristics of the signal. For discerning between various components of the stress in the quantum wells a lead pump pulse, preceding the pump light, pulse my also be used. A system for the application of such methods is also disclosed. | 04-24-2014 |
| 20140118020 | STRUCTURES AND METHODS FOR DETERMINING TDDB RELIABILITY AT REDUCED SPACINGS USING THE STRUCTURES - A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below the lithographic resolution limit of the fabrication technology. | 05-01-2014 |
| 20140125373 | SEMICONDUCTOR ELEMENT INSPECTION DEVICE AND INSPECTION METHOD - A semiconductor inspection device ( | 05-08-2014 |
| 20140132303 | APPARATUS AND METHOD FOR SENSING TRANSISTOR MISMATCH - An integrated circuit implements a transistor mismatch sensor comprising first and second inverter chains coupled to a register. The register comprises a plurality of flip-flops having clock inputs driven by an output of the first inverter chain and data inputs driven by an output of the second inverter chain. Data outputs of the flip-flops of the register are indicative of an amount of mismatch between transistors of different conductivity types in the first and second inverter chains. For example, the register may comprise a thermometer encoded register providing a digital output signal having a first value indicative of an approximate match in speed, drive strength or other characteristics between the transistors of the first and second conductivity types, with values above and below the first value being indicative of respective first and second different types of relative mismatch in speed, drive strength or other characteristics. | 05-15-2014 |
| 20140139257 | APPARATUS AND METHOD FOR EXTRACTING RESISTANCE AND COMPUTER-READABLE RECORDING MEDIUM - A resistance extracting apparatus, a resistance extracting method, and a computer-readable recording medium are provided. A resistance extracting apparatus includes an interface unit which receives parameter values of a semiconductor device, which are measured in a turn-on state and a turn-off state of the semiconductor device, a resistance value extracting unit which extracts resistance values which are independent from voltage applied to the semiconductor device using the parameter value measured in the turn-off state, and extracts resistance values which are dependent on the voltage using the parameter value measured in the turn-on state, and a control unit which controls the resistance value extracting unit to extract the independent resistance values and the dependent resistance values using the received parameter values. | 05-22-2014 |
| 20140145745 | TEST SYSTEM FOR TESTING A CMOS IMAGE SENSOR AND A DRIVING METHOD THEREOF - A test system including a test device configured to transmit an input signal and a control signal to at least one complementary metal-oxide semiconductor (CMOS) image sensor via a probe card, and an interface board configured to map the probe card and the test device. The interface board includes an output receiver configured to receive an image signal from the at least one CMOS image sensor and transform the image signal into image data. | 05-29-2014 |
| 20140145746 | TESTING DEVICE - A testing device has plural pin electronics substrates and a control substrate. The control substrate includes a first instruction code memory storing an instruction code, a first program counter incrementing a count in synchronization with a clock, a code analysis circuit analyzing the instruction code read from the first instruction code memory in accordance with a counter value, and a control data output control circuit outputting control data for controlling the pin electronics substrates in accordance with the instruction code. Each pin electronics substrate includes a first pin memory storing pin data, a second program counter incrementing a count in synchronization with the clock, and a pin data output control circuit adjusting, based on control data, the count value of the second program counter and outputting pin data read from the first pin memory, the pin data being dependent on the count value of the second program counter. | 05-29-2014 |
| 20140152336 | Semiconductor Device and Method for Evaluating Semiconductor Device - A semiconductor layer with a low density of trap states is provided. A transistor with stable electrical characteristics is provided. A transistor having high field-effect mobility is provided. A semiconductor device including the transistor is provided. A method for evaluating a semiconductor layer is provided. A method for evaluating a transistor is provided. A method for evaluating a semiconductor device is provided. Provided is, for example, a semiconductor layer with a low defect density which can be used for a channel formation region of a transistor, a transistor including a semiconductor layer with a low defect density in a channel formation region, or a semiconductor device including the transistor. | 06-05-2014 |
| 20140159764 | SYSTEMS AND METHODS FOR FRACTURE DETECTION IN AN INTEGRATED CIRCUIT - Systems, methods, and devices are provided to identify the occurrence, location, and/or severity of a fracture within an integrated circuit, even when the integrated circuit is not accessible to external inspection. One such method includes obtaining a measurement of a property of the integrated circuit through at least one contact of the integrated circuit. The measurement may include a resistance of a resistive pattern in the integrated circuit or a measurement of current-voltage behavior of a power supply of the integrated circuit. The measurement of the property may be compared to an expected baseline property. Based at least in part on this comparison, whether a fracture of the integrated circuit has occurred and a location of the fracture in the integrated circuit may be determined. | 06-12-2014 |
| 20140159765 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: an output timing test unit configured to edge-trigger a pad output data applied from an input/output pad at a first timing and output the edge-triggered pad output data as output timing test data, during an output timing test mode, and a test output unit configured to receive the output timing test data and output the received output timing test data to a probe pad. | 06-12-2014 |
| 20140159766 | HIGH-FREQUENCY MODULE AND METHOD FOR INSPECTING HIGH-FREQUENCY MODULE - A high-frequency module includes a high-frequency circuit chip, a wiring board having a wiring unit including connection pads which are flip-chip-connected to input and output terminals of the high-frequency circuit chip via bumps, a measurement circuit element that is disposed on a surface, opposed to the wiring board, of the high-frequency circuit chip and is connected between at least two terminals, connected to connection pads of the wiring unit, of the input and output terminals, or that is disposed on a surface, opposed to the high-frequency circuit chip, of the wiring board and is connected to the connection pads, and a detection conductor that is disposed on the high-frequency circuit chip or the wiring board at such a position as to be opposed to the measurement circuit element. | 06-12-2014 |
| 20140159767 | PROCESS SENSOR - A semiconductor process sensor to characterize a semiconductor process by which the semiconductor process sensor was formed. The semiconductor process sensor includes a constant reference voltage source to provide a constant reference voltage signal, a process sensing resistor, a constant current source, and an analog-to-digital converter. The process sensing resistor has a first terminal electrically coupled to the constant reference voltage source and a second terminal to provide a sensed voltage signal, the process sensing resistor having a resistance that is dependent on at least one variation in the semiconductor process used to form the semiconductor process sensor. The constant current source is electrically coupled to the second terminal of the process sensing resistor. The analog-to-digital converter is coupled to the second terminal of the process sensing resistor to provide at least one output signal characterizing the semiconductor process by which the semiconductor process sensor was formed. | 06-12-2014 |
| 20140176180 | APPARATUS FOR TESTING SWITCHING OF POWER SEMICONDUCTOR MODULE - Disclosed herein is an apparatus for testing switching of a power semiconductor module, including: a power semiconductor module including a plurality of power semiconductor devices corresponding to a plurality of phases to test a switching operation of a corresponding power semiconductor device; a power supply unit supplying power to the power semiconductor module; a relay switching unit including a plurality of relay switch devices that connects or disconnects between the power semiconductor module and the power supply unit according to a relay control signal; and a control unit controlling the relay switching unit to test on/off characteristics of at least one of the plurality of power semiconductor devices individually or simultaneously, By this configuration, the on/off operations of the plurality of power semiconductor devices are tested individually or simultaneously by the control of the plurality of relay switch devices, thereby improving the user convenience and reducing the test time. | 06-26-2014 |
| 20140176181 | PRE SPACE TRANSFORMER, SPACE TRANSFORMER MANUFACTURED USING THE PRE SPACE TRANSFORMER, AND SEMICONDUCTOR DEVICE INSPECTING APPARATUS INCLUDING THE SPACE TRANSFORMER - Disclosed herein is a pre space transformer including: a substrate having a first surface and a second surface, which is an opposite surface to the first surface; individual electrodes disposed on the first surface; and common electrodes disposed in the substrate, wherein the individual electrodes are repeatedly disposed while configuring a unit pattern. | 06-26-2014 |
| 20140191777 | MONITORING SYSTEM FOR DETECTING DEGRADATION OF INTEGRATED CIRCUIT - A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit. | 07-10-2014 |
| 20140197862 | METHODS FOR CHARACTERIZING SHALLOW SEMICONDUCTOR JUNCTIONS - The disclosed technology generally relates to methods of characterizing semiconductor materials, and more particularly to methods of characterizing shallow semiconductor junctions. In one aspect, the method of characterizing shallow semiconductor junctions comprises providing a substrate comprising a shallow junction formed at a first main surface, where the shallow junction is formed substantially parallel to the first main surface. The method additionally comprises providing a dielectric layer on the first main surface. The method additionally comprises iterating, at least twice, a combination of processes including providing a respective charge on a predetermined area of the dielectric layer via a charge applicator, and measuring a corresponding junction photovoltage for the predetermined area. The method further comprises deriving at least one of an average hole/electron mobility or a dose of active dopants in the substrate corresponding to the predetermined area, based on the respective charges and the corresponding junction photo voltages. | 07-17-2014 |
| 20140203836 | METHOD OF CHARACTERIZING THE SENSITIVITY OF AN ELECTRONIC COMPONENT SUBJECTED TO IRRADIATION CONDITIONS - A method of selecting a piece of electronic equipment subjected to irradiation conditions comprising at least one electronic component by characterizing a sensitivity parameter of the electronic component to the irradiation conditions listed in a predetermined specifications. The electronic component is irradiated with a source of ionizing radiation having the known irradiation characteristics and geometry. A set of operating values of the electronic component are measured during the irradiation of the electronic component. The sensitivity of the electronic component are measured for a number of irradiation conditions lower than all of the conditions listed in the specifications. The measured results are extrapolated to the other irradiation conditions of the specifications. | 07-24-2014 |
| 20140232428 | Prognostic Circuit of Electromigration Failure for Integrated Circuit - A prognostic circuit of EM failure for IC is disclosed, which includes a current monitoring module, the current monitoring module includes a current output module electrically connected with a monitoring metal wire, and one or more conductive metals covered by an oxide layer and electrically insulated with the monitoring metal wire, the current output module includes at least one current source, the conductive metal is electrically connected with the output port of the current monitoring module, and the monitoring metal wire is surrounded by the conductive metal. The above prognostic circuit can give a warning for short-circuit failure caused by a whisker created by EM. Meanwhile, the prognostic circuit of the present disclosure can also be added a resistance warning, and it can indicate the failure of the resistance increased by EM and the short circuit caused by whisker, so as to greatly increase the warning efficiency of the EM. | 08-21-2014 |
| 20140253169 | BURST NOISE IN LINE TEST - A type of device (which can be deployed in a semiconductor manufacturing line) determining whether a device-under-test is generating burst noise. A transimpedance amplifier converts a current-based noise signal to a voltage based noise signal to apply the following tests aimed at determining the presence of burst noise: (i) sufficiently wide pulse width in the noise signal; (ii) sufficiently random pulse width in the noise signal; (iii) sufficiently wide pulse separation in the noise signal; (iv) sufficiently random pulse separation in the noise signal; and (v) sufficiently large pulse amplitude (or magnitude) in the noise signal. | 09-11-2014 |
| 20140253170 | Electronic Control Circuit Comprising Power Transistors And Method For Monitoring The Service Life Of The Power Transistors - The disclosure relates to an electronic control circuit for an electric device, in particular designed as a commutation electric system of an EC motor, having a plurality of power transistors which are controlled in an operating mode for controlling the device. An additional, similar, non-charged reference transistor in the operating mode of the power transistors is arranged or formed together with the power transistors on a common support or substrate. The circuit also comprises means for applying to the reference transistor and at least one power transistor, respectively one test flow in a test mode for measuring the respective associated saturation voltage and for evaluating saturation tension differences resulting from the measured saturation voltages of the reference transistors and the respective power transistors taking into account the temperature of the support/substrate produced during the measurement as the criterion for an aging process and an expected remaining service life of the power transistors. The disclosure also relates to a method for monitoring power transistors in said type of electronic control circuit with respect to the expected remaining service life thereof. | 09-11-2014 |
| 20140266290 | PROCESS DETECTION CIRCUIT - A process detection circuit can detect process information in both PMOS and NMOS devices without external components or trimming. The process detection circuit may be able to identify process information on a gate-source voltage (V | 09-18-2014 |
| 20140266291 | METHOD, DEVICE AND SYSTEM FOR AUTOMATIC DETECTION OF DEFECTS IN TSV VIAS - A method for automatic detection of defects in TSV vias formed in a layer of semiconductor material, this detection taking place before stacking this layer with a plurality of other layers of semiconductor material for the design of a multilayer chip integrated circuit, comprising: measurement on each of said TSV vias of at least one parameter derived from an electrical characteristic of the TSV vias; detection of defects in said TSV vias according to a comparison of the parameters measured with at least one reference parameter, and calculation of said at least one reference parameter using the measured parameters. The parameter measured on each of the TSV vias comprises an oscillation frequency value derived from a capacitive characteristic of the TSV vias. | 09-18-2014 |
| 20140300385 | METHOD AND DEVICE FOR PULSE WIDTH ESTIMATION - A pulse width estimation method, applied between an integrated circuit and a circuit system for generating a reference pulse with a predetermined pulse width, includes steps for the following: generating an under-test pulse with an under-test pulse width by the integrated circuit; delivering the under-test and reference pulses to the integrated circuit for multiplying the under-test pulse width and the predetermined pulse width thereof by a timing gain and thereby obtaining a gained under-test pulse and a gained reference pulse, respectively; providing, by the integrated circuit, a count pulse for sampling the gained under-test pulse and the gained reference pulse and thereby obtaining a first count number and a second count number, respectively; and estimating the under-test pulse width by using the predetermined pulse width, the first count number and the second count number. A pulse width estimation device is also provided. | 10-09-2014 |
| 20140333341 | TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES - Methods, systems, and apparatus for testing semiconductor devices. | 11-13-2014 |
| 20140347088 | Method and Circuit Of Pulse-Vanishing Test - Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element. | 11-27-2014 |
| 20140347089 | Testing of Thru-Silicon Vias - A system and a method are disclosed for testing thru-silicon vias (TSVs) in a silicon die. A silicon die containing multiple TSVs is mounted on a wafer tape. Two probe points are probed on the exposed side of the silicon die. A resistance is measured between the two probe points and an electrical integrity is determined based on the measured resistance. | 11-27-2014 |
| 20140354324 | METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR PACKAGE HAVING A PACKAGE ON PACKAGE (POP) DESIGN - Embodiments include a testing arrangement for testing a first package, the testing arrangement comprising a frame having a top section and a bottom section, wherein the bottom section of the frame comprises a pickup section, and wherein the pickup section has a first air pathway; a second package mounted on a top surface of the bottom section of the frame such that a second air pathway is defined between (i) the second package and (ii) the top surface of the bottom section of the frame; and a vacuum path defined by (i) the first air pathway and (ii) the second air pathway, wherein during testing of the first package, a vacuum in the vacuum path is generated such that the pickup section of the bottom section of the frame holds the first package. | 12-04-2014 |
| 20140361806 | Configurable Vertical Integration - The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method. | 12-11-2014 |
| 20140368230 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND MEASURING METHOD THEREOF - To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed. | 12-18-2014 |
| 20140375348 | SHORT-CHECKING METHODS - In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage. | 12-25-2014 |
| 20140375349 | TESTER AND TEST SYSTEM INCLUDING THE SAME - Provided are a tester configured to test a semiconductor device and a test system including the same. The tester may include at least one contact unit and at least one memory controller. The contact unit is in contact with the semiconductor device. The memory controller is connected to the contact unit. The memory controller controls data input/output (I/O) operations of the semiconductor device and tests the semiconductor device. | 12-25-2014 |
| 20150008953 | APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST - A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed. | 01-08-2015 |
| 20150022232 | RECONFIGURABLE SEMICONDUCTOR DEVICE - A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in accordance with an operation switch signal. | 01-22-2015 |
| 20150028913 | TESTING APPARATUS AND TESTING METHOD - The present invention proposes a testing method for testing a semiconductor element, including: providing a semiconductor element having a first surface on which a first testing area is formed and a second surface on which a second testing surface is formed; placing the semiconductor element on a plane surface, allowing any one of the first surface and the second surface to be in no parallel to the plane surface; and electrically connecting a testing apparatus to the first testing area and the second testing area of the semiconductor element. The semiconductor element is placed in a non-horizontal manner on the testing apparatus, which makes contact with the two opposing surfaces of the semiconductor element in a horizontal way without directly exerting a downward force against the surface of the semiconductor element, thereby preventing the semiconductor element from damages. | 01-29-2015 |
| 20150028914 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a through silicon via (TSV) formed in a semiconductor substrate including a first-type impurity; and a first doping region formed in the semiconductor substrate located below the TSV. The first doping region is configured to include a second-type impurity and selectively electrically coupled to the TSV. | 01-29-2015 |
| 20150035555 | CIRCUIT LIFETIME MEASURING DEVICE AND METHOD - The present invention discloses a circuit lifetime measuring device to estimate the rest lifetime of a target circuit, comprising: a reference clock receiving end for receiving a reference clock; a correlation signal generating circuit for providing a correlation signal in which at least some operating settings of the correlation signal generating circuit and the target circuit vary synchronously; a storage circuit for storing an initial relation between the reference clock and the correlation signal; a measuring circuit, coupled to the reference clock receiving end and the correlation signal generating circuit, for measuring a present relation between the reference clock and the correlation signal; and an estimating circuit, coupled to the storage circuit and the measuring circuit, for generating an estimation value according to the initial relation and the present relation, wherein the estimation value indicates the rest lifetime of the target circuit. | 02-05-2015 |
| 20150042371 | SEMICONDUCTOR DEVICE DEFECT MONITORING - An arrangement of semiconductor devices to monitor semiconductor defects. There is a first semiconductor device arranged in proximity to a second semiconductor device, the second semiconductor device having a plurality of temperature sensing devices at locations in the second semiconductor device; a plurality of through silicon vias extending between the first semiconductor device and the second semiconductor device to electrically connect the first semiconductor device to the second semiconductor device; and a testing program to cause the plurality of temperature sensing devices in the second semiconductor device to sense the temperature at a plurality of corresponding locations in the first semiconductor device such that a predetermined rise in temperature at one location of the plurality of temperature sensing devices in the second semiconductor device is indicative of a defect in the corresponding location in the first semiconductor device. Methods of monitoring defects are also disclosed. | 02-12-2015 |
| 20150042372 | Addressable test circuit and test method for key parameters of transistors - Methods of testing key parameters of transistors can be achieved using an addressable test circuit. Saturation current and leakage current of transistor are measured through different test signal lines. The addressable test circuit can be applied to a plurality of MOS transistors, each MOS transistor has a gate end G, a drain end D, a source end S, and a substrate B, wherein the S end and D end of each MOS transistor are respectively connected to different test signal lines. The test circuit can have a high area utilization rate such that it has the capacity to put a lot of transistors within one small wafer area. In addition, each transistor's I | 02-12-2015 |
| 20150054542 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF DETECTING DEFECT IN THE ORGANIC LIGHT-EMITTING DISPLAY DEVICE - A method of detecting a defect in an organic light-emitting display device includes: preparing an organic light-emitting display device including an organic light-emitting display panel which includes a plurality of pixels, where each of the pixels includes a driving transistor which operates in a saturation region or a transition region based on a potential difference between a source and a drain thereof and outputs a driving current, and an organic light-emitting diode which emits light based on the driving current; providing a plurality of voltages to the organic light-emitting display panel to operate the driving transistor in the transition region, and determining whether the organic light-emitting display device is defective based on an image, which is displayed on the organic light-emitting display panel based on data applied thereto. | 02-26-2015 |
| 20150061720 | SYSTEM AND APPARATUS FOR MEASURING CAPACITANCE - Systems and methods for determining a capacitance on a device-under-test (“DUT”). An example implementation includes a voltage signal generator that generates a voltage signal alternating between a high voltage and a low voltage at regular time intervals. The voltage signal generator causes a DUT current to flow in the DUT. The DUT current comprises a leakage current and a capacitance measurement current in response to the voltage signal. A current signal generator receives the DUT current from the DUT. The current signal generator generates a cancellation current signal alternating between high and low values at the regular time intervals of the voltage signal such that the cancellation current signal cancels the leakage current through the DUT. A signal measurement circuit receives the capacitance measurement current remaining after the leakage current is canceled to generate an output voltage having an output voltage value used to determine a capacitance of the DUT. | 03-05-2015 |
| 20150061721 | SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of stacked chips, a reference through silicon via (TSV) set passing through the plurality of stacked chips, a plurality of TSVs passing through the plurality of stacked chips, a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set and a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs. | 03-05-2015 |
| 20150061722 | SEMICONDUCTOR DEVICE - Disclosed herein is an apparatus that includes a first internal-potential generation circuit that generates a first internal potential from a power supply potential and that outputs the first internal potential to a first node, and an internal-potential force circuit that includes a first switch element provided between the first node and a second external terminal. The internal-potential force circuit causes the first switch element to enter into an off-state when the test signal supplied to a third external terminal is activated and a potential level of a first external terminal is a first level, and causes the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is a second level different from the first level. | 03-05-2015 |
| 20150061723 | DRIVER IC, DISPLAY DEVICE, AND INSPECTION SYSTEM - A display device includes, on a TFT substrate, a driver IC having a first bump and a second bump, a first terminal and a second terminal connecting respectively to the first bump and the second bump, and wiring interconnecting the first terminal and the second terminal. The driver IC also includes a resistance detection circuit that detects resistance between the first bump and the second bump. | 03-05-2015 |
| 20150061724 | CORRECTION FOR STRESS INDUCED LEAKAGE CURRENT IN DIELECTRIC RELIABILITY EVALUATIONS - Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients. | 03-05-2015 |
| 20150070042 | SYSTEMS AND METHODS FOR INTERNAL AND EXTERNAL ERROR DETECTION IN SENSOR OUTPUT INTERFACES - Integrated circuit systems, such as sensor systems, having on-board-diagnostic (OBD) circuits for the detection of errors presenting internal to the systems are disclosed, along with related methods. In one embodiment, an ADC multiplexer receives analog output readback from an output driver and provides a signal triggering an OBD circuit for internal error indication performed completely independent of digital-to-analog converters (DAC) and output drivers, which can be the point of failure. | 03-12-2015 |
| 20150070043 | INSPECTION METHOD AND INSPECTION DEVICE OF INTEGRATED CIRCUIT DEVICE - A method of inspecting a semiconductor device in which a plurality of conductive members is stacked includes drilling through the conductive layers using a drill and, while drilling, monitoring a probe device that is electrically connected to one of the conductive layers. When an electrical connection is established between the drill and probe device, the drilling is halted and said one of the conductive layers is inspected. | 03-12-2015 |
| 20150070044 | RADIO FREQUENCY CHARACTERISTICS MEASUREMENT JIG DEVICE - A radio frequency characteristics measurement jig device includes: a ground conductor part; a first coplanar line; a connection substrate; and a holding part. The first coplanar line includes a first dielectric layer, a first center conductive layer and first ground conductive layers. The connection substrate includes a second dielectric layer, a second center conductive layer, second ground conductive layers, and a third ground conductive layer. The holding part is configured to press the connection substrate to the first coplanar line and the signal terminal so as to allow electrical continuity between the first center conductive layer and the second center conductive layer on the first region, to allow electrical continuity between the first ground conductive layer and the second ground conductive layer, and to allow electrical continuity between the second center conductive layer on the second region and the signal terminal. | 03-12-2015 |
| 20150070045 | ULTRA FAST TRANSISTOR THRESHOLD VOLTAGE EXTRACTION - A method for performing a semiconductor parametric test comprising performing a full voltage sweep for a first component on a first semiconductor wafer to determine a first value of an electrical characterization parameter for the first component, wherein the full voltage sweep comprises a range between about a minimum input voltage level of the first component and about a maximum input voltage level of the first component, determining a smart sensing window (SSW) for a plurality of subsequent components on the first semiconductor wafer according to the first value, wherein the SSW comprises a range comprising a portion of the full voltage sweep range, performing a partial voltage sweep in the SSW for each of the subsequent components to determine a second value of the electrical characterization parameter for each of the subsequent semiconductor components, and adapting the SSW for at least some of the subsequent components. | 03-12-2015 |
| 20150070046 | SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING THE SAME - According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire. | 03-12-2015 |
| 20150077154 | SYSTEM FOR MEASURING SOFT STARTER CURRENT AND METHOD OF MAKING SAME - A system for measuring soft starter current includes a current monitoring system having a controller and a current transfer device that includes a first sold state switching device. A first current sensor is coupled to the first solid state switching device and the controller to sense off-state current of the first solid state switching device. The controller is configured to determine an operational status of the first solid state switching device. | 03-19-2015 |
| 20150084665 | METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE - A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing. | 03-26-2015 |
| 20150091601 | ON CHIP BIAS TEMPERATURE INSTABILITY CHARACTERIZATION OF A SEMICONDUCTOR DEVICE - Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals. | 04-02-2015 |
| 20150091602 | OPTIMIZED WAVELENGTH PHOTON EMISSION MICROSCOPE FOR VLSI DEVICES - A method for emission testing of a semiconductor device (DUT), by mounting the DUT onto an test bench of an emission tester, the emission tester having an optical detector; electrically connecting the DUT to an electrical tester; applying electrical test signals to the DUT while keeping test parameters constant; serially inserting one of a plurality of shortpass filters into an optical path of the emission tester and collecting emission test signal from the optical detector until all available shortpass filters have been inserted into the optical path; determining appropriate shortpass filter providing highest signal to noise ratio of the emission signal; inserting the appropriate shortpass filter into the optical path; and, performing emission testing on the DUT. | 04-02-2015 |
| 20150091603 | SEMICONDUCTOR UNIT AND TEST METHOD - A semiconductor unit includes: a substrate made of a semiconductor; and a device group formed on the substrate and configured of a plurality of first capacitors, in which the device group includes one or a plurality of first conductive layers and a second conductive layer, the first and second conductive layers provided to be superimposed on each other in part or as a whole with an insulating film in between, the first conductive layer includes an edge extending along one direction, the second conductive layer includes a plurality of sub-conductive layers having substantially same shapes as one another, and the plurality of sub-conductive layers are arranged in relatively different positions with respect to the edge of the first conductive layer. | 04-02-2015 |
| 20150102833 | Instantaneous IR Drop Measurement Circuit - A circuit for measuring instantaneous voltage drops in an IC is disclosed. In one embodiment, a measurement circuit is configured to perform measurements of a voltage drop between a supply voltage node and reference (e.g., ground) node. The measurement circuit may perform consecutive voltage measurements over a number of clock cycles. The measurements may be compared to a reference voltage, and the results of the comparisons may be provided to a register unit. The register unit may include a number of storage locations indicating at which cycles, if any, voltage droops have occurred. Additionally, the register may store information indicating maximum and minimum voltage droops. | 04-16-2015 |
| 20150102834 | SYNTHETIC TEST CIRCUIT FOR THYRISTOR VALVE IN HVDC TRANSMISSION - Provided is a synthetic test circuit for synthetic-testing a thyristor valve in high voltage direct current (HVDC). A resonant circuit applies forward DC current, a reverse DC voltage, and a forward DC voltage to synthetic-test the thyristor valve. A current generation unit generates DC current that is above a reference current value to supply the generated DC current into the resonant circuit. A voltage generates unit generating a DC voltage that is above a reference voltage value to supply the generated DC voltage into the resonant circuit. The resonant circuit includes a charging auxiliary valve for charging a gate driver of the thyristor valve. | 04-16-2015 |
| 20150102835 | SUBSTRATE PLATE FOR MEMS DEVICES - A substrate plate is provided for at least one MEMS device to be mounted thereon. The MEMS device has a certain footprint on the substrate plate, and the substrate plate has a pattern of electrically conductive leads to be connected to electric components of the MEMS device. The pattern forms contact pads within the footprint of the MEMS device and includes at least one lead structure that extends on the substrate plate outside of the footprint of the MEMS device and connects a number of the contact pads to an extra contact pad. The lead structure is a shunt bar that interconnects a plurality of contact pads of the MEMS device and is arranged to be removed by means of a dicing cut separating the substrate plate into a plurality of chip-sized units. At least a major part of the extra contact pad is formed within the footprint of one of the MEMS devices. | 04-16-2015 |
| 20150109019 | METHOD FOR EVALUATING SEMICONDUCTOR DEVICE - A method for evaluating a buried channel in a semiconductor device including a semiconductor layer having a stacked-layer structure is provided. A method for evaluating a semiconductor device is provided, which includes the steps of: electrically short-circuiting a source and a drain of a transistor; applying DC voltage and AC voltage to a gate to obtain a CV characteristic that indicates a relationship between the DC voltage and a capacitance between the gate and each of the source and the drain; and determining that a semiconductor layer of the transistor includes a stacked-layer structure, when the capacitance in a region in an accumulation state in the CV characteristic is increased stepwise. | 04-23-2015 |
| 20150123694 | INSPECTION APPARATUS, INSPECTION SYSTEM, INSPECTION METHOD OF SEMICONDUCTOR DEVICES, AND MANUFACTURING METHOD OF INSPECTED SEMICONDUCTOR DEVICES - An inspection apparatus for inspecting output signal of a semiconductor device is provided with a monitor device configured to sense a signal on the monitor line and a plurality of inspection circuits connected to the monitor line. Each inspection circuit is provided with a semiconductor device support allowing a semiconductor device to be set thereon and including a signal terminal to which a signal is input from the set semiconductor device, a first resistor connected between the signal terminal and the monitor line, a selector terminal, and a first diode connected between the signal terminal and the selector terminal so that a cathode of the first diode is connected to a selector terminal side. | 05-07-2015 |
| 20150123695 | EDGE-EMITTING ETCHED-FACET LASERS - A laser chip having a substrate, an epitaxial structure on the substrate, the epitaxial structure including an active region and the active region generating light, a waveguide formed in the epitaxial structure extending in a first direction, the waveguide having a front etched facet and a back etched facet that define an edge-emitting laser, and a first recessed region formed in the epitaxial structure, the first recessed region being arranged at a distance from the waveguide and having an opening adjacent to the back etched facet, the first recessed region facilitating testing of an adjacent laser chip prior to singulation of the laser chip. | 05-07-2015 |
| 20150130500 | Configurable Vertical Integration - The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method. | 05-14-2015 |
| 20150145551 | SEMICONDUCTOR SUBSTRATE EVALUATING METHOD, SEMICONDUCTOR SUBSTRATE FOR EVALUATION, AND SEMICONDUCTOR DEVICE - On an EP substrate | 05-28-2015 |
| 20150293168 | SEMICONDUCTOR DEVICE - A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for transmission of test confirmation information; an information provider suitable for providing the test confirmation information to the plurality of TSVs; and an output controller suitable for selectively blocking one of the output paths including a failed one among the plurality of TSVs. | 10-15-2015 |
| 20150293169 | METHOD, SYSTEMS, AND DEVICES FOR INSPECTING SEMICONDUCTOR DEVICES - Present example embodiments relate generally to methods, logic, systems, and devices for inspecting a semiconductor device. Example methods comprise applying an initial energy from an energy source to a first location of a conductive layer of the semiconductor device. Example methods further comprise measuring a resultant energy passing through the conductive layer using a probe at a second location of the conductive layer and analyzing the measured resultant energy passing through the conductive layer. Example methods further comprise determining a presence of an inconsistency in the conductive layer based on the analyzing. | 10-15-2015 |
| 20150309087 | OVERCURRENT DETECTOR - An overcurrent detector that includes a sense transistor connected to a sense resistor, a second transistor matched to the sense transistor and connected in parallel to a second resistor, and a voltage comparator coupled to the sense transistor and second resistor. The sense transistor is configured to connect in a same gate and source connection with a driver output transistor. The second transistor and second resistor are configured to receive a current reference and generate a voltage reference. The voltage comparator is configured to compare the voltage reference with a voltage drop across the sense resistor. | 10-29-2015 |
| 20150309113 | MEASURING SETUP AND HOLD TIMES USING A VIRTUAL DELAY - Methodologies and an apparatus for measuring setup and hold times of fabricated semiconductor devices are provided. Embodiments include: providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time or hold time of a device under test are generated. | 10-29-2015 |
| 20150316617 | SWITCH FAILURE DETECTION DEVICE, BATTERY PACK INCLUDING THE SAME, AND METHOD OF DETECTING FAILURE OF ELECTRONIC SWITCH - A switch failure detection device configured to be installed in an electric system including an electric storage device, the switch failure detection device including at least one electronic switch to be connected in a path in which a charging current to the electric storage device and a discharging current from the electric storage device flow, the at least one electronic switch including a first electronic switch, at least one rectifier for passing a discharging current by bypassing the electronic switch when the electronic switch is turned off, the at least one rectifier including a first rectifier being connected parallel to or being parasitic to the first electronic switch such that a forward direction thereof corresponds to a direction in which the discharging current flows, a switch voltage detection circuit configured to detect a voltage drop caused by the at least one electronic switch, and a controller. | 11-05-2015 |
| 20150346246 | Method and Apparatus for Supply Voltage Glitch Detection in a Monolithic Integrated Circuit Device - A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth. | 12-03-2015 |
| 20150346270 | TEST METHOD AND TEST ARRANGEMENT - A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell. | 12-03-2015 |
| 20150346271 | METHODS, APPARATUS AND SYSTEM FOR SCREENING PROCESS SPLITS FOR TECHNOLOGY DEVELOPMENT - At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted. | 12-03-2015 |
| 20150355267 | SYSTEM AND METHOD FOR ELECTRICAL TESTING OF THROUGH SILICON VIAS (TSVs) - A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure. | 12-10-2015 |
| 20150362539 | OUTPUT RESISTANCE TESTING STRUCTURE AND METHOD OF USING THE SAME - A testing structure includes a first transistor having a first dopant type connected to a current source. The testing structure further includes a second transistor having a second dopant type, opposite to the first dopant type. The second transistor is connected to a device under test (DUT). The second transistor is connected in series with the first transistor in a cascode arrangement. The cascode arrangement is capable of measuring an output resistance of the DUT of greater than 1 mega-ohm (MΩ). | 12-17-2015 |
| 20150370110 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR MEASURING THE SAME, DISPLAY DEVICE - The invention discloses an array substrate, a method for manufacturing the same and a measuring method, a display device. The array substrate comprises an electrical connection block exposed to its surface, by manufacturing a passivation layer via hole in a passivation layer, a drain electrode or a pixel electrode of a thin-film transistor is exposed, so that the electrical connection block fills the passivation layer via hole and is provided in contact with the drain electrode or the pixel electrode. Thereby, when the electrical characteristic value of a TFT is measured, the pixel probe of a measuring apparatus may be electrically connected with the drain electrode or the pixel electrode by directly contacting the electrical connection block, so that the measuring of the electrical characteristics of the TFT may be realized. | 12-24-2015 |
| 20160011266 | SEMICONDUCTOR APPARATUS AND POWER CONVERSION APPARATUS | 01-14-2016 |
| 20160043029 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups. | 02-11-2016 |
| 20160047853 | TEST SYSTEM THAT PERFORMS SIMULTANEOUS TESTS OF MULTIPLE TEST UNITS - A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated. | 02-18-2016 |
| 20160061880 | METHODS, APPARATUS AND SYSTEM FOR TDDB TESTING - At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) on a plurality of devices. A first device and a second device are provided for testing. A test signal is provided for performing a time-dependent dielectric breakdown (TDDB) test on the first and second devices. A selection signal for selecting said first and second devices for performing said TDDB test. The first and second devices are arranged in series with a first resistor such that based upon said selecting, the test signal is applied substantially simultaneously to the first and second devices through the first resistor. A determination is made as to whether a breakdown and/or a failure of at least one of the first and second devices has occurred based upon a change in voltage across the first resistor. | 03-03-2016 |
| 20160079707 | SHORT CONTACT IN A TESTING APPARATUS FOR WIRELESS INTEGRATED CIRCUITS - An electrical contact for use in an integrated circuit testing apparatus with a very short conducting contact pin. The shortness of the contact pin is made possible due to the unique design and coupling of the contact pin with an elastomer, and both supported by a housing in such a way that the contact pin test height is brought down to 0.5 mm, whilst providing a deflection of 0.1 mm with is sufficient in order to provide adequate penetration to matte tin plated devices. The contact pin of this invention looks almost like the letter “F”, rotated 90° to the left, so that it lies on its left side. The rectangular shaped elastomer is placed between the prongs of the “F”. The bottom part of the “F” is curved upwards so that it is almost parallel to the prongs. | 03-17-2016 |
| 20160131709 | RECHARGEABLE POWER MODULE AND TEST SYSTEM INCLUDING THE SAME - A rechargeable power module (RPM) may include a rechargeable energy storage device such as a battery or capacitor, a charging circuit, a direct-current (DC) to DC converter, a low drop-out (LDO) voltage regulator and a controller. The charging circuit provides the rechargeable energy storage device with a charging current based on power requirements of device under test and the state of charge, or storage, of the energy storage device. | 05-12-2016 |
| 20160139197 | CIRCUIT, SENSOR AND METHOD FOR DETERMINING AN OSCILLATION BEHAVIOR - A circuitry comprises at least one oscillating circuit section, wherein the circuit section comprises a circuit component, which can be affected by the external influence such that an oscillation behavior of the circuit section can be altered by the external influence. The circuitry is furthermore designed thereby to determine the oscillation behavior of the circuit section by a sampling at numerous defined frequencies. As a result, it may be possible to improve a compromise regarding the production and implementation of such a circuitry. | 05-19-2016 |
| 20160154049 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE | 06-02-2016 |
| 20160161545 | HIGH RESISTIVITY SUBSTRATE FINAL RESISTANCE TEST STRUCTURE - A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants. | 06-09-2016 |
| 20160161552 | Methods and Apparatus for Testing Inaccessible Interface Circuits in a Semiconductor Device - A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion. | 06-09-2016 |
| 20160163607 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND METHOD OF TESTING SEMICONDUCTOR DEVICE - A semiconductor device may include a semiconductor substrate doped with a first type impurity; a through electrode inserted in the semiconductor substrate; an active area formed in the semiconductor substrate to surround an upper portion of sidewalls of the through electrode, and doped with a second type impurity; an insulating layer formed between the semiconductor substrate and the through electrode, and between the active area and the through electrode; a drive circuit suitable for applying a first voltage to the through electrode in a test operation; and a test pad connected to the active area electrically in the test operation, to which a voltage is applied from outside. | 06-09-2016 |
| 20160172311 | IC WITH INSULATING TRENCH AND RELATED METHODS | 06-16-2016 |
| 20160178667 | CONTROLLING A PER-PIN MEASUREMENT UNIT | 06-23-2016 |
| 20160377671 | AGING DETERMINATION OF POWER SEMICONDUCTOR DEVICE IN ELECTRIC DRIVE SYSTEM - Monitoring aging in an electric drive system includes energizing the electric drive system such that electrical current flows through a power semiconductor device therein, determining a value indicative of a voltage across the power semiconductor device, at a current level where voltage is substantially independent of temperature, comparing the determined value with a reference value, and outputting a signal responsive to a difference between the values that is indicative of an aging state of the power semiconductor device. | 12-29-2016 |
| 20160377672 | ON-CHIP COMBINED HOT CARRIER INJECTION AND BIAS TEMPERATURE INSTABILITY MONITOR - Methods and circuits for monitoring circuit degradation include measuring degradation in a plurality of on-chip test oscillators that vary according to a quantity that influences hot carrier injection (HCI) degradation. The measured degradation for the plurality of test oscillators is extrapolated to determine a bias temperature instability (BTI) contribution to the measured degradation. The BTI contribution is subtracted from the measured degradation at a predetermined value of the quantity to determine the HCI degradation for devices represented by the predetermined value. | 12-29-2016 |
| 20180024186 | METHOD, DEVICE AND SYSTEM FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A SUBSTRATE | 01-25-2018 |
| 20180024196 | POWER SUPPLY PROTECTIVE DEVICE, POWER SUPPLY DEVICE AND SWITCH FAILURE DIAGNOSING METHOD | 01-25-2018 |
| 20190147780 | PIXEL INSPECTION METHOD, PIXEL INSPECTION DEVICE, AND DISPLAY DEVICE | 05-16-2019 |
