| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 324762020 | Packaged integrated circuits | 32 |
| 20110018575 | METHOD AND SYSTEM FOR ASSESSING RELIABILITY OF INTEGRATED CIRCUIT - The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC). | 01-27-2011 |
| 20110043243 | MEASUREMENT OF PARTIALLY DEPLETED SILICON-ON-INSULATOR CMOS CIRCUIT LEAKAGE CURRENT UNDER DIFFERENT STEADY STATE SWITCHING CONDITIONS - A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip. | 02-24-2011 |
| 20110050272 | METHOD AND CIRCUIT FOR TESTING INTEGRATED CIRCUIT - A test controller switches the operation of output stages in an integrated circuit between a normal operation mode and a test mode. The output stages are respectively connected to switch elements. A level shifter generates a switch signal for controlling activation and deactivation of the switch elements in accordance with the normal operation mode and the test mode. | 03-03-2011 |
| 20110057682 | Electronic self-healing methods for radio-frequency receivers - Systems and methods for providing self-healing integrated circuits. The method is characterized in that the behavior of a circuit or a device in response to an input signal is observed. One or more operational parameters or characteristics of the circuit or the device are derived. A corrective action to bring the operational parameters or characteristics of the circuit or device within a desired range is deduced, if needed. The corrective action can be the application of a correction signal or a modification of one or more parameters or characteristics of an element in the circuit. The calculated corrective action, if needed, is applied to bring the operational parameters or characteristics of the circuit or device within the desired range. Optionally, the operational parameters or characteristics of the circuit or the device after the correction is effectuated can be checked. | 03-10-2011 |
| 20110080189 | YIELD ENHANCEMENT FOR STACKED CHIPS THROUGH ROTATIONALLY-CONNECTING-INTERPOSER - A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield. | 04-07-2011 |
| 20110148456 | Method and Device for Measuring Inter-chip Signals - A method and device for measuring a signal of a die to be placed within a package is disclosed. At least one die as a Device Under Test (DUT) is mounted on a substrate and a chip-type measurement instrument is mounted on the substrate, or embedded into the substrate, wherein the instrument analyzes and/or processes the signal of the DUT and may provide stimulus signal to the DUT. The substrate having the DUT and the measurement instrument is mounted on a circuit board that has plural electrodes to be connected to the signal paths of the DUT and the instrument. An electrode is coupled to a standard interface port to provide the signal of the chip-type instrument to an external instrument. | 06-23-2011 |
| 20110215826 | Semiconductor Package Test Apparatus - A semiconductor package test apparatus having a test head and a test handler is provided. The semiconductor package test apparatus may include an insert in which a plurality of semiconductor packages are stacked and received in an offset fashion. Further, the semiconductor package test apparatus may include a plurality of sockets located adjacent to the insert and each of the inserts may have a plurality of socket pins. The sockets have different surface levels and are aligned with the semiconductor packages. | 09-08-2011 |
| 20110227601 | TEST METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST SYSTEM, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A test system tests a semiconductor integrated circuit. The semiconductor integrated circuit including a signal terminal to and from a signal is input and output, an RF circuit which processes an RF signal, and a capacitor which is connected between the signal terminal and the RF circuit. The test system has a probe which applies a test signal to the signal terminal and a tester which tests the RF circuit. Before the RF circuit is tested, with the probe and the signal terminal in contact with each other, the tester determines whether the probe and the signal terminal are in a conductive state. | 09-22-2011 |
| 20110298488 | THROUGH CARRIER DUAL SIDE LOOP-BACK TESTING OF TSV DIE AFTER DIE ATTACH TO SUBSTRATE - A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter. | 12-08-2011 |
| 20120112783 | TEST APPARATUS - A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer. | 05-10-2012 |
| 20120119777 | Dynamic Voltage and Frequency Management - In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit. | 05-17-2012 |
| 20120161807 | SINGLE LEVEL OF METAL TEST STRUCTURE FOR DIFFERENTIAL TIMING AND VARIABILITY MEASUREMENTS OF INTEGRATED CIRCUITS - A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device. | 06-28-2012 |
| 20120187977 | SEMICONDUCTOR DEVICE CAPABLE OF BEING TESTED AFTER PACKAGING - Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines. | 07-26-2012 |
| 20130021055 | SCAN TESTING SYSTEM, METHOD AND APPARATUS - Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. | 01-24-2013 |
| 20130120019 | THERMAL PAD SHORTS TEST FOR WIRE BONDED STRIP TESTING - A method of testing a packaged semiconductor device under test (DUT) including a leadframe having a plurality of pins and at least one thermal pad with a semiconductor die having topside bond pads wire-bonded by bond wires to the plurality of pins and secured to the thermal pad. A leadframe sheet is provided including a plurality of packaged DUTs including support members that connect to the packaged DUTs. The thermal pads are shorted to one another, and the leadframe sheet is trimmed for electrically isolating the pins from one another. A first electrical contact is provided to the thermal pad. Active pins of the plurality of pins are electrically contacted with a contactor. Automatic testing identifies shorts between the active pins and the thermal pad. | 05-16-2013 |
| 20130187677 | SYSTEM AND METHOD FOR CALIBRATING CHIPS IN A 3D CHIP STACK ARCHITECTURE - A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip. | 07-25-2013 |
| 20130193996 | Semiconductor Package with Improved Testability - An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball. | 08-01-2013 |
| 20130307576 | System and Method for Testing an Integrated Circuit - In accordance with an embodiment, a method of testing an integrated circuit, includes receiving a supply voltage on the integrated circuit via a first input pin, providing power to circuits disposed on the integrated circuit via the first input pin, comparing the supply voltage to an internally generated voltage, generating a digital output value based on the comparing, and applying the digital output value to a pin of the integrated circuit. | 11-21-2013 |
| 20140111242 | METHOD AND APPARATUS FOR TESTING INTERCONNECTION RELIABILITY OF A BALL GRID ARRAY ON A TESTING PRINTED CIRCUIT BOARD - An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit is presented. The assembly comprises a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon. Vias extend through the testing PCB from a surface to an underside thereof within the IC test region. Each via has an IO pad or ground pad electrically connectable thereto. An IC package having an IC die connected thereto by solder bumps is connected to the IC test region by solder balls, such that each of the IO pads is electrically connectable to a respective pair of the solder balls and solder bumps by the vias. A method of testing interconnection reliability of the BGA using the apparatus is also presented. | 04-24-2014 |
| 20140111243 | TRANSITION DELAY DETECTOR FOR INTERCONNECT TEST - A test circuitry configured to test for transition delay defects in inter-die interconnects is disclosed. In one aspect, the test circuitry comprises an input port configured to receive a test data value and a data storage element configured to temporarily store the test data value. The test circuitry additionally comprises a second inter-die interconnect configured to be electrically connected to a first inter-die interconnect so as to form a feedback loop for transferring the test data value from the data storage element back to the data storage element. The test circuitry additionally comprises a data conditioner configured to condition the fed back test data value so as to make it distinguishable from the stored test data value. The test circuitry additionally comprises a clock pulse generator configured to generate a delayed clock pulse. The test circuitry additionally comprises a selection logic configured to apply the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. The test circuitry further comprises a readout unit for reading out a test data value stored in the data storage element. | 04-24-2014 |
| 20140145747 | LIGHT ACTIVATED TEST CONNECTIONS - A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test. | 05-29-2014 |
| 20140191778 | ON CHIP ELECTROSTATIC DISCHARGE (ESD) EVENT MONITORING - An approach for monitoring electrostatic discharge (ESD) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an ESD pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure. The approach further includes circuit source and logic gates of the canary device, connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure. The approach further includes a logic gate of the ESD transistor, connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure. In addition, the enable signal is also connected to the input terminal through a resistor of the circuit structure. | 07-10-2014 |
| 20140253171 | PACKAGE INTEGRITY MONITOR WITH SACRIFICIAL BUMPS - An apparatus with package integrity monitoring capability, includes: a package having a die connected to an interposer through a plurality of bumps, wherein at least some of the bumps comprise dummy bumps; a package integrity monitor having a transmitter to transmit a test signal and a receiver to receive the test signal; and a first scan chain comprising a plurality of alternating interconnects in the die and in the interposer connecting some of the dummy bumps in series, wherein the first scan chain has a first end coupled to the transmitter of the package integrity monitor and a second end coupled to the receiver of the package integrity monitor. | 09-11-2014 |
| 20140285229 | Testing Integrated Circuit Packaging for Shorts - An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested. | 09-25-2014 |
| 20140368231 | Power Semiconductor Module Comprising a Power Electronics Circuit and an Arrangement for Measuring and Transferring Measurement Data - A power semiconductor module includes a power electronics circuit and a measuring circuit for measuring a physical parameter occurring in the power electronics circuit and for providing a corresponding measurement signal. A transmission circuit is coupled to a secondary side of a transfer unit, and an evaluation circuit is coupled to the primary side and galvanically isolated from the transmission circuit by the transfer unit. The evaluation circuit supplies an AC voltage to the primary side, causing primary current to flow on the primary side, which in turn results in secondary current on the secondary side, the secondary current being supplied to the transmission circuit. The transmission circuit receives the measurement signal and modulates the secondary current in accordance with the measurement signal, which results in a modulation of the primary current. The evaluation circuit evaluates the modulation of the primary current and generates an output signal dependent thereon. | 12-18-2014 |
| 20150061725 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a test bump pad, a first bump pad coupled to a first through-silicon-via (TSV), a second bump pad coupled to a second TSV, a latching unit, coupled between the test bump pad and the first bump pad, suitable for storing data, and a switching unit suitable for selectively coupling the first bump pad to the second bump pad in response to a test operation control signal. | 03-05-2015 |
| 20150123696 | METHODOLOGY FOR TESTING INTEGRATED CIRCUITS - An integrated circuit is disclosed. The integrated circuit includes input and output pads, a first integrated circuit portion having first circuitry, and a second integrated circuit portion having second circuitry different from the first circuitry. The first integrated circuit portion is configured to provide an input test signal from the input pad to the second integrated circuit portion, and provide an output test signal from the second integrated circuit portion to the output pad, the output test signal being generated by second integrated circuit portion in response to the input test signal. | 05-07-2015 |
| 20150123697 | METHODS AND APPARATUSES FOR AC/DC CHARACTERIZATION - Aspects of an apparatus for characterizing an integrated circuit device are provided. The apparatus includes a first connection circuit configured to selectively couple at least one terminal of the integrated circuit device to a termination circuit for AC loopback and a second connection circuit configured to selectively couple the at least one terminal of the integrated circuit device to a test resource for DC characterization. In another aspect, an apparatus for characterizing an integrated circuit is provided. The apparatus includes a board configured to couple to the integrated circuit and a resource to characterize the integrated circuit. The board includes means for detecting physical misalignment of the board and the resource to characterize the integrated circuit. | 05-07-2015 |
| 20150323589 | COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS THEREWITH - A composite integrated circuit (IC) includes a first circuit layer, a second circuit layer having a first chip and a second chip, and a first wireless power transfer (WPT) device in the first chip or the first circuit layer. The first WPT device generates a power supply voltage by extracting energy from an electromagnetic signal. A first tracking circuit in the second chip or the first circuit layer is powered by the power supply voltage from the first WPT device and stores or outputs tracking data in response to an instruction extracted from the electromagnetic signal. | 11-12-2015 |
| 20150323590 | ON-CHIP CURRENT TEST CIRCUIT - An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor. | 11-12-2015 |
| 20160187417 | TESTING METHOD - A testing method including the following steps is provided. A lead frame is provided, wherein the lead frame includes a frame body and a plurality of lead frame units which are connected with each other through the frame body and are arranged in array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins which are connected with each other. A plurality of controllers are bonded with the lead frame units and each of the controllers is electrically connected with the corresponding lead frame unit. The frame body of each of the lead frame units is electrically isolated from the second pins. A first electrical testing is performed to each of the lead frame units carrying the controllers. | 06-30-2016 |
| 20160195581 | APPARATUSES AND METHODS FOR DIE SEAL CRACK DETECTION | 07-07-2016 |
