| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 324762060 | Multiple chip module | 8 |
| 20110175639 | Semiconductor device semiconductor device testing method, and data processing system - To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit. | 07-21-2011 |
| 20110199114 | BIT FAILURE SIGNATURE IDENTIFICATION - A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature. | 08-18-2011 |
| 20130088255 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device. | 04-11-2013 |
| 20140021978 | TEST METHOD FOR SEMICONDUCTOR DEVICE HAVING STACKED PLURAL SEMICONDUCTOR CHIPS - Disclosed herein is a method for testing a semiconductor device, the method includes: preparing a first semiconductor chip having a first bump electrode and a first driver circuit that drives the first bump electrode, and a second semiconductor chip having a second bump electrode and a second driver circuit that drives the second bump electrode; staking the first and second semiconductor chips so that the first bump electrode and the second bump electrode are electrically connected to each other to form a current path including the first and second bump electrodes; and driving, in a test mode, the current path to a first potential by the first driver circuit while driving the current path to a second potential different from the first potential by the second driver circuit. | 01-23-2014 |
| 20140062523 | SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF - A semiconductor apparatus includes a chip containing a plurality of through-vias, a test voltage input unit, and a test result reception unit. The test voltage input unit applies a test voltage to one of the plurality of through-vias. The test result reception unit receives an output signal outputted from one or more of the plurality of through-vias. | 03-06-2014 |
| 20140145750 | CIRCUITS FOR SELF-RECONFIGURATION OR INTRINSIC FUNCTIONAL CHANGES OF CHIPS BEFORE VS. AFTER STACKING - A method and system for testing one or more semiconductor structures, for example, chips or wafers, in a three-dimensional stack. The method and system includes controlling a logic signal of a first circuit in a first chip or wafer connected to a supply voltage to indicate a first state during pre-assembly testing of the first chip or wafer. The method and system further includes controlling the logic signal to indicate a second state when the first circuit is connected to a second circuit of a second chip or wafer resulting in a combined circuit. The combined circuit is in a three-dimensional chip or wafer stack during post-assembly testing of the three-dimensional chip or wafer stack. | 05-29-2014 |
| 20160011265 | SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF | 01-14-2016 |
| 20160061886 | INTEGRATED CIRCUIT - An integrated circuit may include a first semiconductor device including a first through-silicon via configured for electrically coupling a first bump pad to a second bump pad, and may be configured to buffer a first internal test signal generated by a test signal inputted through the first bump pad and generate a first detection signal. The integrated circuit may include a second semiconductor device including a second through-silicon via configured for electrically coupling a third bump pad to a fourth bump pad, and may be configured to buffer a second internal test signal generated by the test signal inputted through the third bump pad and generate a second detection signal. The third bump pad may be electrically coupled with the second bump pad. | 03-03-2016 |
