| Entries |
| Document | Title | Date |
|---|
| 20080201628 | APPARATUS AND METHOD FOR DETERMINING A DETECTED PUNCTURED POSITION IN PUNCTURED CONVOLUTIONAL CODES - An apparatus for generating a detected punctured position in punctured convolutional codes. A delay line circuit has a plurality of delay elements connected in series, storing a finite sequence of an input bit stream. A logic gate circuit, coupled to outputs of a part of the delay elements of the delay line circuit in accordance with a parity check polynomial, performs a logic operation to output a number stream. The number stream is accumulated for possible punctured positions and the one of the possible punctured positions with a minimal accumulated number is selected and determined as the detected punctured position. | 08-21-2008 |
| 20080250301 | Apparatus and Method For Improving Reliability of Collected Sensor Data Over a Network - Apparatus and method suitable for improving reliability of collected sensor data over a network. One or more transient errors are predicted and corrected using correlation of corrected data. For example, sensor data can be collected from one or more sensor nodes in a network. A device other than a sensor node can use the data to develop a predictive model based upon inherent redundancy in the sensor data, and correct one or more later-received values deemed unreliable. | 10-09-2008 |
| 20080250302 | Convolutional Encoder and the Encoing Method Thereof - A convolutional encoder and the encoding method thereof, wherein the encoding method includes steps of: generating convolutional code according to the predefined criteria and with reference to the encoder's predefined convolutional encoding rate and constraint length; processing the data to be transmitted by using the convolutional code so that the coded data are suitable for propagation in multipath fading channel with Rayleigh fading, wherein the predefined criteria is to maximize the sum of Euclidean distance between each branch along the shortest error event path and each corresponding branch along the correct decoding path, and the shortest error event path is the decoding path having the minimum branches of non-zero Euclidean distance compared with the correct decoding path. | 10-09-2008 |
| 20080282133 | COOPERATIVE CONCATENATED CODING FOR WIRELESS SYSTEMS - Cooperative concatenated coding techniques are provided for wireless communications between at least two users and a base station. A network system employing cooperative concatenated coding includes cooperating user devices each configured to encode and transmit at least a portion of a joint message. The joint message includes at least a portion of a first message from a first cooperating user device and at least a portion of a second message from a second cooperating user device. An embodiment includes encoding a first message from a first cooperating user, receiving a second message from a second cooperating user and decoding the second message. The methodology also includes re-encoding at least a portion of the decoded message with at least a portion of the first message to form a combined message, and then transmitting at least a portion of the combined message. | 11-13-2008 |
| 20080288852 | MULTICARRIER COMMUNICATION SYSTEM CAPABLE OF SWITCHING MODULATION SCHEMES DURING COMMUNICATION - A multicarrier wireless communication system is capable of switching the modulation scheme used by each carrier during communication. This communication system includes error detectors for detecting error bits separately for respective carriers by comparing the data block of each carrier before and after correction. The modulation scheme used by a particular carrier is switched to an appropriate modulation scheme, when the S/N ratio of the particular carrier is deteriorated or improved, on the basis of the information about the corrected error bits. | 11-20-2008 |
| 20080301536 | CHANNEL CODING AND RATE MATCHING FOR LTE CONTROL CHANNELS - A method and apparatus for channel coding and rate matching of the Physical Uplink Control Channel (PUCCH) and the Physical Downlink Control Channel (PDCCH) is disclosed that uses convolutional encoding to code the control channels. Rate matching is performed using a circular buffer based rate matching algorithm. A rate matching module may contain a single interleaver or may alternatively comprise a plurality of sub-block interleavers. Interleaved coded bits may be stored in the circular buffer in an interlaced format, or output streams from separate sub-block interleavers may be stored contiguously. When a plurality of sub-block interleavers are used, different interleaving patterns may be used. Rate matching may use bit puncturing or repetition to match the rate of the available physical channel resource. Rate matched output bits may be interleaved using a channel interleaver. | 12-04-2008 |
| 20080307292 | Method and Apparatus for Digit-Serial Communications for Iterative Digital Processing Algorithms - An architecture and a method are provided for decoding codewords for codes such as low density parity check (LDPC) codes. An iterative decoding algorithm such as the Belief Propagation Algorithm (BPA) is employed that attempts to correct errors in an input block of symbols via a structure containing two sets of nodes through node processing and the passing of messages between nodes. Message passing and node processing is performed in a digit-serial manner instead of a bit-parallel manner. | 12-11-2008 |
| 20090119569 | Encoding system and method for encoding error control codes within bit streams - An encoding system for encoding error control codes may include a first encoder configured to encode an input bit stream to generate first bit streams of C-bits, where c is an integer greater than zero, and a second encoder may be configured to receive the first bit streams and shuffle data of the received first bit streams to generate second bit streams. The data shuffling of the first bit streams may adjust an error distribution of the second bit streams. An encoding method may include encoding an input bit stream to generate first bit streams of C-bits, and receiving the first bit streams and shuffling data of the received first bit streams to generate second bit streams. An error distribution of the second bit streams may be adjusted based on the data shuffling. | 05-07-2009 |
| 20090144603 | Assigning Codes to and Repairing Huffman Trees - A method for assigning codes to Huffman trees and repairing invalid Huffman trees is disclosed using a calculated delta and moving nodes within the Huffman tree by adjusting their encode register entries. | 06-04-2009 |
| 20090144604 | CONVOLUTIONAL ENCODING WITH PARTITIONED PARALLEL ENCODING OPERATIONS - Convolutional encoding throughput is increased by partitioning input information bits into a plurality of blocks that are convolutionally encoded in parallel. A plurality of convolutional encoding operations which have respective initial encode states that are mutually different from one another are applied in parallel to one of the blocks to produce a respectively corresponding plurality of convolutional encoding results. One of the convolutional encoding results is selected based on a convolutional encoding operation applied to another of the blocks. | 06-04-2009 |
| 20090150755 | OPTIMUM DISTANCE SPECTRUM FEEDFORWARD TAIL-BITING CONVOLUTIONAL CODES - A method of generating a set of generator polynomials for use as a tail biting convolution code to operate on data transmitted over a channel comprises: (1) selecting valid combinations of generator polynomials to include in a pool of potential codes, each valid combination being a potential code; (2) determining first lines of a weight spectrum for each potential code in the pool and including potential codes of the pool having best first lines in a candidate set; (3) determining best codes of the candidate set based on the first L number of lines in the weight spectrum; (4) selecting an optimum code(s) from the best codes; and (5) configuring a shift register circuit(s) of a data transceiver to implement the optimum code(s). | 06-11-2009 |
| 20090158130 | METHOD AND APPARATUS FOR TURBO ENCODING AND DECODING - A method and apparatus for turbo encoding and method and apparatus for turbo decoding are disclosed, by which encoding and decoding speeds of turbo codes and performance thereof can be enhanced. In performing turbo encoding on inputted information bits by a unit of an information frame including a predetermined number of bits, the present invention includes dividing the information frame into at least two information sub-blocks, encoding each of the at least two information sub-blocks independently, rearranging information bits configuring the information frame by interleaving the information frame, dividing the rearranged information frame into at least two information sub-blocks, and encoding each of the at least two information sub-blocks independently. | 06-18-2009 |
| 20090193320 | APPARATUS, AND ASSOCIATED METHOD, FOR DECODING CONVOLUTIONALLY ENCODED DATA - An apparatus, and an associated method, for correcting errors in decoded data, decoded by a convolutional decoder, such as an SOVA (Soft Output Viterbi Algorithm). A CRC check is performed upon the decoded data. If the CRC check fails, a conclusion is made that the decoded data contains errors. Portions of the decoded data indicated to exhibit low levels of reliability are toggled with values of most-likely error events. A corrected sequence of the decoded data is formed that corrects for the errors in the decoded data. | 07-30-2009 |
| 20090249171 | TURBO DECODER, BASE STATION AND DECODING METHOD - A turbo decoder includes a state transition probability computing unit which obtains a state transition probability from data, a flag, and a priori probability from a previous stage, an alpha and beta metric computing unit which obtains an alpha metric and a beta metric from the state transition probability by computing a plurality of processes concurrently in a time sequence, and a normalization unit which obtains decoded data and a priori probability for a next stage based on the state transition probability obtained by the state transition probability computing unit and on the alpha metric and the beta metric obtained by the alpha and beta metric computing unit. | 10-01-2009 |
| 20090327846 | Convolution Encoder, Encoding Device, and Convolution Encoding Method - A bit register is restored to the initial state thereof irrespective of the state of the bit register even when a convolution encoder includes a circular section. | 12-31-2009 |
| 20100023844 | METHOD FOR INTERLEAVING CONTINUOUS LENGTH SEQUENCE - An interleaver provision method for providing a continuous length, an interleaving method, and a turbo-encoder thereof are disclosed. The interleaving method selects a basic interleaver having a proper length from among the basic interleaver set, which is predetermined to have the length represented by a multiple of the ARP fluctuation vector period. The interleaving method performs the dummy insertion and the pruning process to have the length acting as the basic-interleaver length, so that it can provide the ARP interleaver having a continuous length. | 01-28-2010 |
| 20100031129 | MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS - Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that operate to check the data digits for error in each IC device according to an algorithm associated with the IC device, the algorithm being different for each IC device. Each IC device will act in response to the data digits if no error is detected in the data digits. Additional apparatus, systems, and methods are disclosed. | 02-04-2010 |
| 20100042908 | DATA AND ERROR CORRECTION CODE MIXING DEVICE AND METHOD - Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy. | 02-18-2010 |
| 20100050059 | SYSTEM AND METHOD FOR REMOVING PDCCH DETECTION ERRORS IN A TELECOMMUNICATIONS NETWORK - A system, method and node for unambiguous encoding of Physical Downlink Control Channel (PDCCH) channels in a Long Term Evolution (LTE) telecommunications system to remove detection errors. The method includes the step of modifying a size of a circular buffer by excluding at least one coded bit from the circular buffer. The circular buffer collects interleaved bits from a PDCCH payload having a plurality of bits. The PDCCH payload is encoded with a convolutional code. The bits of the PDCCH payload are then interleaved. The interleaved bits are collected into the modified circular buffer. The bits are then selected from the modified circular buffer for transmission. | 02-25-2010 |
| 20100153826 | APPARATUS AND METHOD FOR TAIL BITING CONVOLUTIONAL ENCODING - Provided are an apparatus and a method for tail biting convolutional encoding. The apparatus includes a plurality of shift registers and at least one operator. The plurality of shift registers sequentially performs a shift operation on input bit-stream. The operator outputs an encoded bit-stream by performing convolutional encoding on an output of the shift register using a generator polynomial corresponding to a predetermined code rate. A transmission encoded bit-stream is created by replacing encoded data for a certain initial bit-stream of the encoded bit-stream with a bit-stream obtained by subsequently performing convolutional encoding on the initial bit-stream. | 06-17-2010 |
| 20100192046 | CHANNEL ENCODING - A channel encoding method of calculating, using a programmable processor, a code identical with a code obtained with a hardware channel encoder. The method comprises:—a first step ( | 07-29-2010 |
| 20100192047 | TRANSMITTING DEVICE AND TRANSMITTING METHOD - A transmitting device and method enabling improvement of the reception quality on the receiving side when the LDPC-CC (Low-Density Parity-Check Convolutional Codes) encoding is used. The transmitting device ( | 07-29-2010 |
| 20100218075 | APPARATUS AND METHOD FOR TRANSMITTING SIGNAL USING BIT GROUPING IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for transmitting a signal using a bit grouping method in a wireless communication system is disclosed. Interleaved subblocks are maintained, and output bit sequences are modulated in due order after bit grouping and bit selection. The bit grouping method is advantageous in that bit reliability is uniformly distributed. | 08-26-2010 |
| 20100235720 | CHANNEL ENCODING AND DECODING APPARATUSES AND METHODS - An encoding apparatus for use in a radio transmitter has a unit for turbo-SPC encoding a plurality of information bits which bits constitute a transmit signal, and deriving at least one set of redundant bits from one set of the information bits; and a redundancy-adjusting unit for decreasing or increasing the redundant bits according to a channel-encoding rate designated by a control signal, and adjusting the ratio of the number of the information bits to the number of the redundant bits. At least some of the redundant bits decreased or increased by the redundancy-adjusting unit are derived from an identical set of the information bits. | 09-16-2010 |
| 20100235721 | Rate Matching and De-Rate Matching for an LTE Transport Channel - Described embodiments provide for rate matching with an encoded sequence of data bits. The encoded sequence of data bits is divided into two or more sub-blocks, with each sub-block having at least one column of bits, each including a set of valid bits. A set of dummy bits is generated and appended to each column of each sub-block. A starting point index for the set of valid bits within each sub-block is generated and the number of bits supported by the physical layer is determined. Only the valid bits of each sub-block are interleaved, based on each starting point index, until either i) there are no valid bits remaining, or ii) the number of interleaved bits reaches the number of bits supported by the physical layer. All dummy bits and any valid bits exceeding the number of bits supported by the physical layer are omitted. | 09-16-2010 |
| 20100262895 | Turbo-Coding DOCSIS Information for Satellite Communications - Methods and systems for modifying DOCSIS-based transmission paths for communication in higher frequency and/or wireless environments, such as wireless terrestrial communication systems and satellite communication systems. An inner turbo-code is combined with a DOCSIS based Reed-Solomon (“RS”) forward error correction (“FEC”) coding scheme, to produce a concatenated turbo-RS code (other FEC codes can be utilized). In phase and quadrature phase (“I-Q”) processing is utilized to enable relatively low cost up-converter implementations. The I-Q processing is preferably performed at baseband, essentially pre-compensating for analog variations in the transmit path. Power amplifier on/off control capable of controlling on/off RF power control of remote transmitters is modulated on a transmit cable to reduce the need for a separate cable. | 10-14-2010 |
| 20100287452 | Tail-biting convolutional codes for uplink fast feedback control channel - An apparatus and method for processing fast feedback payload data to generate symbols for transmission through a fast feedback channel in a wireless network are presented. The technique first encodes payload data using a tail biting convolutional code. The encoded bits are then de-multiplexed to five different data subblocks in a sequential fashion. Subblock interleaving is then used to interleave the data of the subblocks according to a predetermine scheme. A bit selector then selects interleaved subblock bit for output. The selected bits may then be modulated by a modulator using quadrature phase shift keying (QPSK). The resulting symbols may then be mapped to a predetermined fast feedback subcarriers within a feedback channel. | 11-11-2010 |
| 20100299581 | SERIAL TURBO TRELLIS CODED MODULATION USING A SERIALLY CONCATENATED CODER - Serial concatenated trellis coded modulation (SCTCM) includes an outer coder, an interleaver, a recursive inner coder and a mapping element. The outer coder receives data to be coded and produces outer coded data. The interleaver permutes the outer coded data to produce interleaved data. The recursive inner coder codes the interleaved data to produce inner coded data. The mapping element maps the inner coded data to a symbol. The recursive inner coder has a structure which facilitates iterative decoding of the symbols at a decoder system. The recursive inner coder and the mapping element are selected to maximize the effective free Euclidean distance of a trellis coded modulator formed from the recursive inner coder and the mapping element. The decoder system includes a demodulation unit, an inner SISO (soft-input soft-output) decoder, a deinterleaver, an outer SISO decoder, and an interleaver. | 11-25-2010 |
| 20110041042 | APPARATUS AND METHOD FOR DETERMINING INTERLEAVED ADDRESS OF TURBO INTERLEAVER - An apparatus and method for determining interleaved addresses of a turbo interleaver are disclosed. A new interleaving size of received data is compared with a previously-stored interleaving size. When the compared interleaving sizes are equal to each other, the received data is decoded using previously-stored interleaved addresses. When the compared interleaving sizes are different from each other, the received data is decoded using new interleaved addresses generated with the new interleaving size. The turbo interleaver generates interleaved addresses at minimum number of code blocks rather than every code block, resulting in reduction of decoding delay and improvement of decoding performance. | 02-17-2011 |
| 20110047445 | METHOD FOR RECOVERY OF LOST AND/OR CORRUPTED DATA - A method for recovery of lost and/or corrupted data, whereby this data is encoded by means of an encoder connected to the transmitter device and transmitted via a transmission channel to the receiver device. The transmitted data is decoded by means of a decoder connected to the receiver device wherein lost and/or corrupted data is restored during decoding. Encoding and decoding are performed by using a convolutional code. According to the disclosure the window size, on which the decoder connected to the receiver device operates, is variable so that the window size can be adapted to the erasure rate of the transmission channel and/or to the delay service requirement. | 02-24-2011 |
| 20110060970 | METHOD OF PERFORMING INTERLEAVING AND DATA TRANSMISSION APPARATUS - A method of performing interleaving and a data transmission apparatus are disclosed, in which interleaving is performed for input data streams using bit reverse ordering (BRO) operation. A method of performing interleaving for input data streams comprises writing respective bits of the input data stream in a row direction of a memory matrix in accordance with the input order, performing row permutation for index of each row of the memory matrix using an R-bit (R is an integer) bit reverse ordering (BRO) operation, performing pruning for a row which satisfies a given condition, performing column permutation using BRO operation for index of each column of the memory matrix, and reading to output each bit in a column direction of the memory matrix where the column permutation has been performed. | 03-10-2011 |
| 20110060971 | TAIL-BITING DECODING METHOD AND DEVICE - A tail-biting decoding method and device are provided, so as to improve accuracy of backtracking state determination and decrease decoding delay. The method includes the following steps. Survivor paths of a training system are acquired. The training system is formed of a first transport block and a second transport block connected in series. The number of the survivor paths passing through each first state of the second transport block is counted. A first state having a maximum number of the survivor paths may be selected as a backtracking state of the second transport block. Backtracking decoding is performed on the second transport block by using the survivor paths on the backtracking state, so as to obtain a decoding result. | 03-10-2011 |
| 20110113307 | APPARATUS AND METHOD FOR TRANSMITTING DATA USING A CTC (CONVOLUTIONAL TURBO CODE) ENCODER IN A MOBILE COMMUNICATION SYSTEM - Disclosed are an apparatus and a method for transmitting data using a CTC (Convolutional Turbo Code) encoder in a mobile communication system. The data transmission method according to the present invention includes: a first encoding step of encoding input data bits inputted through two input terminals of the CTC encoder and outputting first encoding bits; a step of interleaving the input data bits by using four CTC interleaver parameters (P0, P1, P2, and P3) corresponding to the sizes of the input data bits; a second encoding step of encoding the interleaved data bits and outputting second encoding bits; and a step of selectively transmitting the input data bits, the first encoding bits, and the second encoding bits to a receiving side in accordance with a predetermined coding rate, wherein the sizes of the input data bits are one of M-number of predefined data bit sizes, and P0 of the CTC interleaver parameters corresponding to the sizes of the input data bits is a relative prime number to N which is ½ of a data block size, P1 is a natural number which is a multiple of 2, P2 is a natural number which is a multiple of 4, and P3 is a natural number which is a multiple of 2 if P1 mod4=2 and a natural number which is a multiple of 4 if P1mod4=0. | 05-12-2011 |
| 20110119567 | SIGNAL PROCESSING METHOD AND COMMUNICATION SYSTEM USING THE SAME - A signal processing circuit in a transmitter of a communication system comprises an appending circuit, a scrambler, an FEC encoder and a stream parser. The appending circuit is configured to divide a packet data string into a plurality of divided data strings, append a predetermined string to the tail of each divided data string, and output the appended data strings sequentially. The scrambler is configured to perform a scramble operation for the appended data strings. The FEC encoder is configured to sequentially encode the output data strings of the scrambler into convolutional code-words complying with the requirements of a MIMO communication system. The stream parser is configured to forward the convolutional code-words to at least a stream signal processing circuit. | 05-19-2011 |
| 20110167321 | APPARATUS AND METHOD OF TRANSMITTING AND RECEIVING DATA FOR IMPROVING TRANSMISSION RATE - A data transmitter and receiver for improving a data rate, and more particularly, to an apparatus and method of transmitting and receiving an orthogonal frequency division multiplexing (OFDM) symbol in which a pilot signal is added to a data signal is provided. The apparatus includes a transmitter including: a pilot adder to add a pilot signal to a data signal; and a guard interval inserting unit to insert a guard interval to the data signal with the added pilot signal, and a receiver including: a guard interval removal unit to remove a guard interval in a received time domain signal; a fast Fourier transform (FFT) unit to transform the time domain signal in which the guard interval is removed to a frequency domain signal; a channel estimator to estimate a channel value from the time domain signal in which the guard interval is removed; an equalizer to equalize the frequency domain signal based on the estimated channel value; and a pilot signal removal unit to remove the pilot signal in the equalized frequency domain signal. | 07-07-2011 |
| 20110258521 | INTERLEAVING SCHEME FOR AN LDPC CODED QPSK/8PSK SYSTEM - An approach is provided for interleaving low density parity check (LDPC) encoded bits in QPSK/8PSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use. | 10-20-2011 |
| 20110289391 | INTERLEAVER DEVICE AND RECEIVER FOR A SIGNAL GENERATED BY THE INTERLEAVER DEVICE - The inventive concept enables backward-compatible extension of existing interleaver-based transmission systems to the effect that in addition to an existing logical transport channel, which is interleaved using a standardized interleaver profile, further logical transport channels may be transmitted via the same physical transmission channel. In this context, the first transport channel obviously is reduced in terms of data rate, so that the additional transport channels may actually obtain a transmission capacity that is needed accordingly. Interleaver profiles of the further logical transport channels are derived, to this end, from the interleaver profile of the first transport channel. | 11-24-2011 |
| 20110314358 | Method and Circuit for BER Estimation - This invention relates to a method and a circuit for estimating the bit error rate in a data transmission system. Symbols are detected (u) by a maximum likelihood detector ( | 12-22-2011 |
| 20110320920 | CODING APPARATUS, RECEIVING APPARATUS, WIRELESS COMMUNICATION SYSTEM, PUNCTURING PATTERN SELECTING METHOD AND PROGRAM THEREOF - By controlling to select encoding appropriately considering characteristics of equalization and decoding of a receiving apparatus employing a turbo equalization technology, it is possible to attain a high transmission characteristic. Information bits of two systems including a sequence which is input to a first RSC encoding unit | 12-29-2011 |
| 20120110422 | TRANSMISSION DEVICE - A transmission device in a communication system where a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deletion of the dummy bits from the results of the systematic encoding is transmitted. The transmission device inserts dummy bits into information bits based on an interleaving pattern of an interleaving portion in a turbo encoder; performs systematic encoding of the information bits into which the dummy bits are inserted, and then deletes the dummy bits from the results of the systematic encoding to generate a systematic code; and transmits the systematic code. By considering the interleaving pattern, original bit positions, which, after interleaving, exists within the ranges of stipulated numbers of bits at the beginning and at the end, are determined in advance, and the dummy bit insertion portion executes control so as not to insert dummy bits into the original bit positions. | 05-03-2012 |
| 20120124453 | METHOD AND APPARATUS FOR A PARAMETERIZED INTERLEAVER DESIGN PROCESS - A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations. | 05-17-2012 |
| 20120151304 | Decoding Tail-Biting Convolutional Codes - A user equipment (UE) comprising at least one component configured to decode a tail-biting convolution code (TBCC) by calculating a plurality of paths that correspond to a plurality of encoder starting states and trace back at least one of the calculated paths per at least one iteration until a trace-back convergence check (TCC) condition fails, wherein the TCC condition fails if a starting state of a first traced back path among the calculated paths is not equal to a starting state of a subsequent traced back path. | 06-14-2012 |
| 20120166916 | COMPUTATIONALLY EFFICIENT CONVOLUTIONAL CODING WITH RATE-MATCHING - An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate. | 06-28-2012 |
| 20120185756 | APPARATUS AND METHOD FOR TRANSMITTING DATA USING A CTC (CONVOLUTIONAL TURBO CODE) ENCODER IN A MOBILE COMMUNICATION SYSTEM - A method of transmitting data using a Convolutional Turbo Code (CTC) encoder by a transmitting end in a mobile communication system includes providing first encoded bits by encoding input data bits inputted to two input ports of the CTC encoder, interleaving the input data bits using 4 CTC interleaver parameters (P | 07-19-2012 |
| 20120192041 | PRE-DECODED TAIL-BITING CONVOLUTIONAL CODE DECODER AND DECODING METHOD THEREOF - A pre-decoded tail-biting convolutional code (TBCC) decoder and a decoding method thereof are provided. The decoder includes a pre-decoder, a storage module, and a control module. The pre-decoder receives a current state, a neighboring state, and a current path status corresponding to sequential data encoded in TBCC, generates predicted decoded bits, and determines whether states corresponding to minimum path metrics of neighboring stages are in continuity according to the current state, the neighboring state, and a current path status. The storage module is connected to the pre-decoder and stores the predicted decoded bits. The control module is connected to the storage module and the pre-decoder. In addition, the control module selects to output the decoded bits from the storage module when the continuity between the states corresponding to the minimum path metrics of the neighboring stages reaches a truncation length. | 07-26-2012 |
| 20120198315 | SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION USING A VARIABLE CONSTRAINT LENGTH CONVOLUTIONAL ENCODER - Systems and methods are provided for selecting transmission parameters used in the transmission of a communication signal in a wireless communications device. In one embodiment, a computer-implemented method for determining a convolutional code constraint length and/or a modulation type is provided. The method includes obtaining a channel condition for a channel associated with transmission of the communication signal. Based at least in part on the channel condition, the method includes selecting a convolutional code constraint length and/or a modulation type for transmitting the communications signal. In some embodiments, the method also includes selecting a data rate for transmitting the communications signal. Other aspects, embodiments, and features are also claimed and described. | 08-02-2012 |
| 20120210196 | COOPERATIVE CONCATENATED CODING FOR WIRELESS SYSTEMS - Cooperative concatenated coding techniques are provided for wireless communications between at least two users and a base station. A network system employing cooperative concatenated coding includes cooperating user devices each configured to encode and transmit at least a portion of a joint message. The joint message includes at least a portion of a first message from a first cooperating user device and at least a portion of a second message from a second cooperating user device. An embodiment includes encoding a first message from a first cooperating user, receiving a second message from a second cooperating user and decoding the second message. The methodology also includes re-encoding at least a portion of the decoded message with at least a portion of the first message to form a combined message, and then transmitting at least a portion of the combined message. | 08-16-2012 |
| 20120254706 | Method And Apparatus Relating To Channel Decoding - The present invention relates to channel decoding and provides ways and means for improved channel decoding of data frames. The frame has been channel encoded and transmitted to a receiver. The frame includes a part with information that is unknown to the receiver and another part with information for which the receiver generates at least one data hypothesis predicting its information content. The receiver performs a hypothesis-based decoding of the received encoded frame, wherein the at least one data hypothesis is used to improve a probability of successful decoding. The invention may advantageously be used to improve decoding of frames containing short control messages with fill bits, e.g. acknowledgement messages. | 10-04-2012 |
| 20120272125 | Stopping Methods for Iterative Signal Processing - A stopping method for an iterative signal processing includes a first step of receiving the state signatures generated by the iterative signal processing. A next step includes accumulating the state signatures into a stopping index variable. A next step includes stopping iterative decoding when the stopping index variable is less than a predetermined threshold. | 10-25-2012 |
| 20120278686 | SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING - The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information. | 11-01-2012 |
| 20120290902 | FAULT-TOLERANT NON-VOLATILE INTEGRATED CIRCUIT MEMORY - Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices. | 11-15-2012 |
| 20120324316 | Turbo Parallel Concatenated Convolutional Code Implementation on Multiple-Issue Processor Cores - An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals. | 12-20-2012 |
| 20130007568 | ERROR CORRECTING CODE DECODING DEVICE, ERROR CORRECTING CODE DECODING METHOD AND ERROR CORRECTING CODE DECODING PROGRAM - Provided is an error correction code decoding apparatus capable of performing a decoding process efficiently for various interleaver sizes while suppressing an increase in apparatus size. The error correction code decoding apparatus includes: a simultaneous decoding selection unit configured to select whether a first and a second elementary codes are to be subjected to simultaneous decoding depending on a size of an interleaver; a reception information storage unit configured to store reception information at a position in accordance with a selection result from the simultaneous decoding selection unit; an external information storage unit configured to store external information corresponding to each of the first and the second elementary codes at a position in accordance with the selection result from the simultaneous decoding selection unit; and a soft-input soft output decoding unit including a plurality of soft-input soft-output decoders that perform soft-input soft-output decoding on each of divided blocks of the first and the second elementary codes in parallel, the soft-input soft output decoding unit configured to repeat decoding of the first elementary code and the second elementary code when simultaneous decoding is not selected by the simultaneous decoding selection unit, and configured to repeat simultaneous decoding of the first and the second elementary codes when simultaneous decoding is selected by the simultaneous decoding selection unit. | 01-03-2013 |
| 20130042167 | RUNTIME SYSTEM FAULT TREE ANALYSIS METHOD, SYSTEM AND PROGRAM - The original MCS of a system fault tree includes sufficient conditions required for a top system hazard. If a fault occurs in a component and the component is restored, the current MCS of a system and the critical components can be calculated on the basis of the original MCS by means of several calculation patterns. | 02-14-2013 |
| 20130104008 | Error-Correcting Encoding Apparatus - An apparatus for encoding source data, that includes a first encoder configured to encode the source data to produce first additional data; and a randomizing unit configured to randomize the source data to produce randomized data; and a second encoder configured to encode the randomized data to produce second additional data; and a selector configured to select a number of bits from the first and second additional data to produce first selected data and second selected data, wherein the number of selected bits is selected based upon a data length of an output sequence determined by a transmission frame format, and wherein the data length of the output sequence is variable. | 04-25-2013 |
| 20130111305 | CHANNEL DECODING METHOD AND DECODER FOR TAIL-BITING CODES | 05-02-2013 |
| 20130124947 | TAIL-BITING CONVOLUTIONAL DECODER AND DECODING METHOD - Techniques are provided for decoding tail-biting convolutional codes by using information within the received data stream that traditionally has not been used or been available to the convolutional decoder, e.g., cyclic redundancy check (CRC) and bit information known by both the transmitter and receiver. Further, a single parallel trace-back is used that reduces implementation complexity. In addition, the least reliable decisions made during forward processing may be reversed in order to generate additional possible codeword candidates. These techniques can be used to reduce false detection rates (FDRs) and/or detection error rates (DERs). | 05-16-2013 |
| 20130145238 | ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LOW PARITY DENSITY CHECK CODES - Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline. | 06-06-2013 |
| 20130198592 | TURBO CODE PARALLEL INTERLEAVER AND PARALLEL INTERLEAVING METHOD THEREOF - A Turbo code parallel interleaver and a parallel interleaving method are disclosed by the disclosure. The Turbo code parallel interleaver comprises: an interleaving unit, configured to generate a column address for parallel-reading data and a row address of each row of data being row-interleaved, input the column address and the column address after delay to a CB matrix unit, input the row address of each row to a switching output unit, and input the row address of each row after delay to a switching input unit; a switching output unit, configured to receive the data of each row output by the CB matrix unit, perform the inter-row interleaving for the data of each row according to the row address of each row, and input the interleaved data to a parallel MAP unit for the MAP computing; and a switching input unit. | 08-01-2013 |
| 20130254638 | ENCODER, DECODER, TRANSMITTING APPARATUS, AND RECEIVING APPARATUS - There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder connects a first encoder to a second encoder to perform encoding and thereby carry out LDPC-CC encoding, the first encoder performing encoding based on an partial parity check matrix for information bits obtained by extracting a sequence corresponding to the information bits in a parity check matrix and the second encoder performing encoding based on a partial parity check matrix for parity bits obtained by extracting a sequence corresponding to the parity bits in the parity check matrix. A termination sequence generator generates a termination sequence including the same number of bits as the memory length of the first encoder and provides the generated termination sequence as an input sequence. | 09-26-2013 |
| 20130297993 | ENCODING METHOD, AND DECODING METHOD - An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula. | 11-07-2013 |
| 20130311857 | ENCODING METHOD, DECODING METHOD - An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula. | 11-21-2013 |
| 20140006910 | ERROR CORRECTION ENCODING METHOD, DECODING METHOD AND ASSOCIATED DEVICES | 01-02-2014 |
| 20140053047 | METHOD AND APPARATUS OF TRIPLE-DECODING FOR IEEE 802.11p PHYSICAL LAYER MECHANISM - A method for receiving and storing a packet of symbols. The method decodes the packet of symbols using a first decoding algorithm, and if the first decoding algorithm fails to correctly decode the packet of symbols, then the method decodes the packet of symbols using a second decoding algorithm. If the second decoding algorithm fails to decode the packet of symbols, then a third decoding algorithm is used. The third decoding algorithm can be sub-packet decoding, where a first sub-packet is part of the packet of symbols. If the first sub-packet is decoded successfully, then the method generates a channel estimate using the properly decoded information, and then uses that channel estimate to decode a subsequent sub-packet using the channel estimate, where the second sub-packet is a set of symbols that are a portion of the packet of symbols. | 02-20-2014 |
| 20140068393 | SYMBOL FLIPPING DECODERS OF NON-BINARY LOW-DENSITY PARITY CHECK (LDPC) CODES - Systems and methods are provided for decoding data. A decoder retrieves data related to a symbol and identifies a plurality of candidate values for the symbol. The decoder determines a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances, and the decoder determines whether to update a value of the symbol based at least in part on the plurality of distances. | 03-06-2014 |
| 20140337693 | LOW-COMPLEXITY DECODER FOR CONVOLUTIONAL CODING - The invention relates, according to the first form thereof, to a transmission error correction method, wherein at least two encoded binary series from a binary series that is to be transmitted and encoded by means of a convolutional code are received from a communication channel. Said method is characterized in that same comprises the following steps: producing, from two received encoded binary series, comparison binary series that coincide in the absence of transmission errors on the communication channel; comparing the comparison binary series and forming a detection binary series corresponding to the logic operation OU-exclusive of the two comparison binary series; and, in the event that the comparison binary series diverge from a divergence point, verifying if the series made up of P bits of the detection binary series from the divergence point corresponds to a listed transmission error and correcting, if necessary, the received encoded binary series. | 11-13-2014 |
| 20150058704 | PARAMETERIZED INTERLEAVER FOR A MULTI-RATE SYSTEM - A parameterized interleaver structure is presented. The interleaver is designed to specify and maintain a maximum delay, irrespective of code rate and number of code blocks. The disclosed interleaver in effect concatenates two interleaver structures together. When the arm index is greater than a defined number N1, the arm delay is calculated using a set of parameters M2, D2, and N, where M2 is a maximum delay for an interleaver arm, D2 is the delay decrement, and N is the arm index, running from 1 to N, where N is the total number of arms in the interleaver. However, when the arm index N is less than or equal to N1, the delay can be calculated in a similar manner, but using a second set of parameters, namely M1, D1, and N instead, which involves a different delay length. This approach has the dual benefit of specifying both the maximum delay of the interleaver and the minimum required delay to process data. | 02-26-2015 |
| 20150100860 | Systems and Methods of Vector-DMA cache-XOR for MPCC Erasure Coding - System and method embodiments are provided for managing storage systems. In an embodiment, a network component for managing data storage includes a storage interface configured to couple to a plurality of storage devices; and a vector-direct memory access (DMA) cache-exclusive OR (XOR) engine coupled to the storage interface and configured for a multiple parities convolution codes (MPCC) erasure coding to accelerate M parities parallel calculations and the erasures cross-iterations decoding, wherein a single XOR-engine with caches and a vector-DMA address generator is shared by the MPCC erasure coding engine for pipelining external dual data rate (DDR4) memory accesses, where M is a positive integer greater than two. | 04-09-2015 |
| 20160049963 | CONVOLUTIONAL DEINTERLEAVER - A receiver ( | 02-18-2016 |
