Class / Patent application number | Description | Number of patent applications / Date published |
714746000 |
Digital data error correction
| 5901 |
714724000 |
Digital logic testing
| 1537 |
714799000 |
Error/fault detection technique
| 771 |
714718000 |
Memory testing
| 692 |
714704000 |
Error count or rate
| 254 |
714712000 |
Transmission facility testing
| 60 |
714701000 |
Data formatting to improve error detection correction capability
| 56 |
714710000 |
Replacement of memory spare location, portion, or segment
| 54 |
714700000 |
Skew detection correction
| 39 |
714798000 |
Error detection for synchronization control
| 16 |
714703000 |
Testing of error-check system
| 14 |
714709000 |
Data pulse evaluation/bit decision | 4 |
20100031097 | DETECTION APPARATUS - A detection apparatus detecting an error component contained in two signals (A, B) approximated by a cosine and sine functions representing an object position, the detection apparatus including an arithmetic portion ( | 02-04-2010 |
20120124432 | SYSTEM AND METHOD FOR PHASE ERROR REDUCTION IN QUANTUM SYSTEMS - One embodiment of the invention includes a quantum system. The system includes a superconducting qubit that is controlled by a control parameter to manipulate a photon for performing quantum operations. The system also includes a quantum resonator system coupled to the superconducting qubit and which includes a first resonator and a second resonator having approximately equal resonator frequencies. The quantum resonator system can represent a first quantum logic state based on a first physical quantum state of the first and second resonators with respect to storage of the photon and a second quantum logic state based on a second physical quantum state of the first and second resonators with respect to storage of the photon. | 05-17-2012 |
20140019816 | ERROR CORRECTION DEVICE - In an error correction device, a frame generation section receives pulse signals as temperature information of a power switching element transmitted from a PWM comparator. The frame generation section sets a first correction pulse signal, a second correction pulse signal and the temperature information sequentially into each frame. A pulse width of the first correction pulse signal corresponds to a pulse width when a time ratio thereof becomes 100%. A pulse width of the second correction pulse signal corresponds to a pulse width when a time ratio thereof becomes 50%. A microcomputer receives the temperature information through a photocoupler and corrects the received temperature information. The microcomputer calculates a temperature detection value of the power switching element on the basis of the corrected temperature information. | 01-16-2014 |
20160140005 | PULSED-LATCH BASED RAZOR WITH 1-CYCLE ERROR RECOVERY SCHEME - Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error. | 05-19-2016 |
Entries |
Document | Title | Date |
20080201619 | ERROR CORRECTING DEVICE, ERROR CORRECTING METHOD AND DISK SYSTEM - There is provided an error correcting device, including: a demodulation circuit that reads data from an optical disk and demodulates the data to generate demodulated data; a PI syndrome generation circuit that generates a PI syndrome of the demodulated data and outputs the PI syndrome to an external memory; a PO syndrome generation circuit that generates a PO syndrome of the demodulated data and outputs the PO syndrome to the external memory; and an error correcting circuit that reads the PI syndrome and the PO syndrome from the external memory and performs error correction on the demodulated data stored in the external memory, based on the syndromes. | 08-21-2008 |
20080244336 | SET-CYCLIC COMPARISON METHOD FOR LOW-DENSITY PARITY-CHECK DECODER - The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder. | 10-02-2008 |
20080244337 | Method and System for Automated Handling of Errors in Execution of System Management Flows Consisting of System Management Tasks - A method and system for automated error handling in system management flows by enhancing workflow engines by an error handling component and by adding a supportive error handling layer to invoked system management tasks which serves m the counterpart to the workflow engine's error handling component. The additional functionality of the task-provided, error handling layer is accessible for the workflow engine via extended Web services interfaces. The workflow engine's error handling component and the task-provided error handling layer allow for the definition of a standard protocol between the workflow engine and invoked tasks for automated error handling. Furthermore, an interface and method of communication between the enhanced workflow engine and an external error resolving device (such as an expert system) is defined with the purpose of using the external error resolving device for automatic error recovery. The internal or external error resolving device is capable of performing corrective actions on the managed IT infrastructure using mechanisms outside the scope of this invention. The benefit of the presented architecture is that the complexity concerning error handling is completely removed from system management flow definitions, and the designer of a system management flow can concentrate on the logical structure of the flow (e.g. the correct sequence of tasks). | 10-02-2008 |
20090113256 | Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding - The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Decoding is performed in a pipelined manner using a layered belief propagation technique and scalable resources, which are configurable to accommodate at least two codeword lengths and at least two code rates. A computer program product, apparatus and device are also described. | 04-30-2009 |
20090287968 | NETWORK COMMUNICATION THROUGH A SPECIFIED INTERMEDIATE DESTINATION - This disclosure provides a method of routing communications over a network through an intermediate destination, and it also provides a “universal proxy” that may be used for this purpose. A host wishing to deliver information to a client sends packets as part of a first exchange or “session” to the intermediate destination, which performs error detection and recovery for received packets. The intermediate destination then (if desired) masks the source and transmits the information to the client in a second session, with the intermediate destination controlling transmission (e.g., specifying transmission protocol) and performing loss recovery as appropriate. This methodology enables a number of applications, including masquerading of source identity through the intermediate destination, and TCP acceleration (e.g., by subscribing to a service where the intermediate destination is used to accelerate communications or offer special types of processing or services). A “universal proxy” can be implemented as a single network appliance, accessible to act as a proxy from anywhere on a wide area network (e.g. the Internet, using an IP address). If desired, the universal proxy can also be configured as a two-way proxy. | 11-19-2009 |
20090292960 | Method for Correlating an Error Message From a PCI Express Endpoint - In a method of handling errors in a digital system that includes a root complex in data communication with at least one endpoint, the endpoint including at least one advanced error reporting register, an error is detected by the endpoint. Error data indicative of the error is stored in an advanced error reporting register. An indication of which transaction caused the error is stored in a secondary location. An error message packet that includes the error data and the indication of which transaction caused the error is generated. The error message packet is transmitted to the root complex. The root complex is caused to take a preselected action in response to the error message packet. | 11-26-2009 |
20090327820 | Demapper Using Floating-Point Representation of Soft Bits - The subject matter disclosed herein provides methods and systems for converting fixed-point soft bit values, provided by a demapper, into floating-point soft bits values. In one aspect, there is provided a method. The method may include receiving, from a demapper, soft bits formatted as a fixed-point value. Moreover, the soft bits may be converted from the fixed-point value to a floating-point value. The floating-point value is punctured to remove a bit. The converted soft bits are provided to a buffer to enable decoding of the buffered soft bits. Related systems, apparatus, methods, and/or articles are also described. | 12-31-2009 |
20100011259 | ELECTRONIC APPARATUS AND UNIT UTILIZED IN ELECTRONIC SYSTEM - A printer apparatus generates a fixed-length packet by appending a termination identifier for representing a termination point of sub-data. The printer apparatus transmits the packet to a unit. Upon receiving the packet, the unit detects burst error based upon the termination identifier. | 01-14-2010 |
20110087931 | TEST APPARATUS AND TRANSMISSION DEVICE - Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; and a control apparatus that controls the test unit. The control apparatus includes a first buffer and a second buffer that buffer access requests to the test unit; a data output section that buffers, in the first buffer, access requests to be sent from the control apparatus to the test unit and, when an error occurs, buffers the access requests in the second buffer instead of the first buffer; and a transmitting section that sequentially transmits the access requests in the first buffer to the test unit and, when an error occurs, sequentially transmits the access requests in the second buffer to the test unit. | 04-14-2011 |
20110302463 | APPROXIMATE ERROR CONJUGATION GRADIENT MINIMIZATION METHODS - In one embodiment, a method includes selecting a subset of rays from a set of all rays to use in an error calculation for a constrained conjugate gradient minimization problem, calculating an approximate error using the subset of rays, and calculating a minimum in a conjugate gradient direction based on the approximate error. In another embodiment, a system includes a processor for executing logic, logic for selecting a subset of rays from a set of all rays to use in an error calculation for a constrained conjugate gradient minimization problem, logic for calculating an approximate error using the subset of rays, and logic for calculating a minimum in a conjugate gradient direction based on the approximate error. In other embodiments, computer program products, methods, and systems are described capable of using approximate error in constrained conjugate gradient minimization problems. | 12-08-2011 |