Class / Patent application number | Description | Number of patent applications / Date published |
714798000 | Error detection for synchronization control | 16 |
20080201629 | METHOD AND SYSTEM FOR DETECTING SYNCHRONIZATION ERRORS IN PROGRAMS - A method and system for error detection in programs with collective synchronization and/or procedures are provided. In one aspect, the method and system may use interprocedural analysis for matching synchronizations in a program in order to detect synchronization errors, and, if no such errors exist, may determine the synchronization phases of the program. The method and system in one aspect may use a combination of path expressions and interprocedural program slicing to match the synchronization statements that may execute along each program path. If the synchronization matching succeeds, the method and system in one aspect may determine the sets of synchronization statements that synchronize together. A matching failure may indicate the presence of a synchronization error and the method and system in one aspect may construct a counter example to illustrate the error. | 08-21-2008 |
20080282134 | Methods and Apparatus for Detection of Performance Conditions in Processing System - Techniques are disclosed for detection of performance conditions in processing systems. For example, a method of detecting a performance condition in at least one particular processing device of a processing system having a plurality of processing devices includes the following steps. Data is input to a data structure associated with the particular processing device, over a given time period. The input data may be a buffer or a bucket. The input data represents data associated with the execution of at least one function performed by the particular processing device. The given time period includes the time period between consecutive heartbeat signals transmitted by the particular processing device. At least a portion of the input data is removed from the data structure associated with the particular processing device, near the end of the given time period. The removed input data is compared to an expected function execution level. An alarm signal is generated, when warranted, based on the comparison of the removed input data to the expected function execution level such that a performance condition in the particular processing device is determinable. | 11-13-2008 |
20090138786 | COMMUNICATION CONTROL APPARATUS, COMMUNICATION CONTROL METHOD, AND COMMUNICATION CONTROL PROGRAM - A communication control apparatus transmits data to an other communication control apparatus and receives a notification as to whether the data has normally been received or not from the other communication control apparatus. The communication control apparatus includes setting changing means for changing setting of a transmission circuit when reception error which is a notification that the data has not normally been received is received from the other communication control apparatus. | 05-28-2009 |
20100023846 | METHODS AND APPARATUSES FOR PERFORMING ERROR DETECTION AND ERROR CORRECTION FOR SYNCHRONIZATION FRAME - According to methods and apparatuses for performing error detection and error correction for a synchronization frame in embodiments of the present invention, a transmitter acquires a transmitter check sequence according to contents of a synchronization frame sequence; and a receiver acquires a receiver information sequence related to the check sequence. When performing error detection, the receiver acquires a receiver check sequence according to the receiver information sequence and a generator polynomial and determines whether the synchronization frame transmission is valid according to the receiver check sequence and the transmitter check sequence; when performing error correction, the receiver acquires a syndrome sequence according to the receiver information sequence, acquires an error pattern according to the syndrome sequence and acquires a result of error correction according to the error pattern and the receiver information sequence. | 01-28-2010 |
20100050061 | CLOCK DOMAIN CHECK METHOD, CLOCK DOMAIN CHECK PROGRAM, AND RECORDING MEDIUM - To reduce pseudo errors. | 02-25-2010 |
20100083076 | Terminal device, time adjusting method of terminal device and communication system - A terminal device includes: a time information receiving unit which receives measured time and an estimated error of another terminal device; an estimated error calculating unit which calculates an error containing the estimated error of another terminal device received by the time information receiving unit as an updating-use estimated error; and a time updating unit which, when the updating-use estimated error calculated by the estimated error calculating unit is smaller than an estimated error stored in an estimated error memory unit, stores the updating-use estimated error calculated by the estimated error calculating unit in the estimated error memory unit thus updating the estimated error stored in the estimated error memory unit, and adjusts a measured time measured by a time measuring unit in response to the measured time of another terminal device received by the time information receiving unit. | 04-01-2010 |
20100318884 | CLOCK AND RESET SYNCHRONIZATION OF HIGH-INTEGRITY LOCKSTEP SELF-CHECKING PAIRS - An apparatus comprises first and second modules configured to operate in a lockstep mode and a reset mode. Each of the first and second modules is configured to asynchronously enter the reset mode when a parent reset signal is asserted at that module. Each of the first and second modules is configured to, in response to the asserted parent reset signal being negated at that module, indicate to the other module that that module is ready to exit reset mode and exit the reset mode when the other module has also indicated that the other module is ready to exit reset mode. | 12-16-2010 |
20110004813 | Low overhead circuit and method for predicting timing errors - Data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a data input, a data output and a processing path arranged between the data input and the data output. The processing path comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal; and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data. The data processing circuitry further comprises: a plurality of retention circuits for storing data in a low power mode, the plurality of retention circuits being arranged in parallel with the processing path; and at least one potential error detecting circuit for determining during processing of the data if the data signal pending at an input to one of the plurality of synchronisation circuits is stable during a predetermined time prior to capture of the data and for signalling a potential error if the data input is determined to be unstable during the predetermined time. The at least one potential error detecting circuit comprising: a potential error detecting path for transmitting the data signal pending at the input of the one of the plurality of synchronisation circuits to one of the retention circuits the potential error detecting path comprising delay circuitry for delaying the data signal such that the data signal arrives at the retention circuit the predetermined time after it arrives at the synchronisation circuit; and comparison circuitry for comparing a value of the data signal captured by one of the synchronisation circuits with a value of the data signal captured by a corresponding one of the retention circuits, the comparison circuitry being configured to signal a potential error in response to detecting a difference in the captured data values. | 01-06-2011 |
20110022934 | SYSTEM AND APPARATUS FOR SYNCHRONIZATION BETWEEN HETEROGENEOUS PERIODIC CLOCK DOMAINS, CIRCUIT FOR DETECTING SYNCHRONIZATION FAILURE AND DATA RECEIVING METHOD - The present invention relates to a system and an apparatus for synchronization between heterogeneous periodic clock domains, a synchronization failure detecting circuit, and a data receiving method. The synchronization system between heterogeneous periodic clock domains including a sender and a receiver operated according to heterogeneous periodic first clock and second clock, respectively, includes: a sender that outputs a prediction clock obtained by delaying the first clock for a first time; and a receiver that predicts success and failure of synchronization between the first clock and the second clock by using the prediction clock and selectively delays the second clock for a second time according to the predicted results to synchronize the second clock with the first clock. | 01-27-2011 |
20110107190 | OBSCURING INFORMATION IN MESSAGES USING COMPRESSION WITH SITE-SPECIFIC PREBUILT DICTIONARY - Obscuring information in messages to be exchanged over a communications network. In one aspect, the information comprises path name information and parameters for use in a Uniform Resource Locator (“URL”). In another aspect, the information comprises links and parameters used in forms, where hidden parameters are removed from a form and used as URL parameters. A compression dictionary is used to create a compressed form of the information. An identifier of the dictionary and an error detection code (such as a checksum) computed over the compressed information are concatenated with the compressed information, and this is encoded for sending on an outbound message. The original information is then recovered from an inbound message which contains the obscured information by reversing the processing used for the obscuring. | 05-05-2011 |
20110113310 | APPARATUS AND METHOD FOR CLOCK SIGNAL SYNCHRONIZATION IN JTAG TESTING IN SYSTEMS HAVING SELECTABLE MODULES PROCESSING DATA SIGNALS AT DIFFERENT RATES - In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit. | 05-12-2011 |
20110302479 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR RESOLVING A DATA CONFLICT - In accordance with embodiments, there are provided mechanisms and methods for resolving a data conflict. These mechanisms and methods for resolving a data conflict can enable an improved user experience, increased efficiency, time savings, etc. | 12-08-2011 |
20130104009 | PROCESSING UNIT - A processing unit includes: a cache memory including a plurality of memory elements; an error detection circuit configured to detect an error when a first timing for reading data from the cache memory is behind a threshold; a latch circuit configured to set a second timing for latching the data based on an output from the error detection circuit and to latch the data at the second timing; and a processing unit core to process the data latched by the latch circuit. | 04-25-2013 |
20140281841 | Systems and Methods for Sync Mark Mis-Detection Protection - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream. | 09-18-2014 |
20140304572 | ULTRA LOW-POWER PIPELINED PROCESSOR - A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage. | 10-09-2014 |
20150033101 | APPARATUS AND METHOD FOR DETECTING A FAULT WITH A CLOCK SOURCE - A method includes receiving a first clock signal from a first clock source at a clock monitoring unit. The method also includes counting a first number of pulses in the first clock signal during a specified time period. The method further includes identifying a fault with the first clock source when the first number does not have an acceptable value. In addition, the method includes testing the clock monitoring unit by determining whether the clock monitoring unit identifies an artificial clock fault. The time period could be defined by receiving a second clock signal, counting a second number of pulses in the second clock signal, and signaling when the second number meets or exceeds a threshold value. In response to the identified fault with the first clock source, a second clock source could be used to provide a second clock signal. | 01-29-2015 |