Entries |
Document | Title | Date |
20080215934 | DETECTING METHOD AND SYSTEM FOR CONSISTENCY OF LINK SCRAMBLING CONFIGURATION - A detecting method for the consistency of a link scrambling configuration, comprises: setting the first threshold of the data packet error rate received by the receiving end; when the receiving end receiving date from the link, counting the received data packet error rate; judging whether the error rate is above the set first threshold; if yes, determining that the link scrambling configurations between transmitting end and receiving end are inconsistent; if not, determining that the link scrambling configurations between transmitting end and receiving end are consistent. The invention provides that the ports could detect the consistency of the link scrambling configuration automatically when configuring the link scrambling code, thereby enables the receive device to adjust the configuration of scrambling code to achieve the consistency of scrambling code between both ends of the link, and improves the maintenance of devices. | 09-04-2008 |
20080222461 | APPARATUS AND METHOD FOR CALCULATING ERROR METRICS IN A DIGITAL COMMUNICATION SYSTEM - A method and an apparatus for calculating an error metric in a digital communication receiver. In the receiver, an input data stream is used to generate at least one input bit stream. The combinational logic unit performs an error-check operation on delayed and current bits of the input bit stream using a polynomial error-check equation previously determined. Finally, an accumulator is used to accumulate a number of trials with respect to the error check operation and generates a nominal error-check number based on the number of the correct trials. | 09-11-2008 |
20080222462 | IMAGE FORMING SYSTEM, IMAGE PROCESSING APPARATUS, DETERMINATION DEVICE, AND IMAGE PROCESSING METHOD - An object of the present invention is to provide an image forming system, an image processing apparatus, a determination device, and image processing method that are capable of preventing users' convenience from reducing even when an image forming apparatus prints a coded image with a low print precision. A first MFP is connected through a LAN to a second MFP for performing error-correcting coding of original information, for creating a coded image by imaging the original information with the error-correcting code, and for forming the created coded image on a sheet. The first MFP extracts the original information from the coded image on the sheet obtained by reading the sheet on which the coded image is formed. Thereafter, the first MFP transmits to the second MFP an error detection rate at the time when the original information is extracted. | 09-11-2008 |
20080244339 | Read level control apparatuses and methods - Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate. | 10-02-2008 |
20080256403 | Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit - A first mathematical expression indicating a dependence of SER on an information storage node diffusion layer area at the same information storage node voltage Vn is derived with a use of a result of measuring a relationship between SER and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of MISFET using a plurality of information storage node voltages Vn as a parameter. Then, a second mathematical expression is derived from the measurement result by substituting a relationship indicating a dependence of SER on an information storage node voltage at the same information storage node diffusion layer area Sc into the first mathematical expression. SER can be calculated by substituting a desired information storage node diffusion layer area and a desired information storage node voltage of a storage circuit or an information holding circuit into the second mathematical expression. | 10-16-2008 |
20080294948 | Protocol Tester and Method for Performing a Protocol Test - Embodiments of the present invention provide a protocol tester for performing a protocol test, said protocol tester exhibiting an input for the feeding in of data, a protocol decoding device for the decoding of data, and an output for providing the decoded data, the protocol tester also comprising a device for measuring the bit error rate. A corresponding method for performing a protocol test is also provided. | 11-27-2008 |
20080307273 | System And Method For Predictive Failure Detection - A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period. | 12-11-2008 |
20080313509 | METHOD AND APPARATUS FOR PREVENTING SOFT ERROR ACCUMULATION IN REGISTER ARRAYS - A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold. | 12-18-2008 |
20080320344 | Method for Testing the Error Ratio Ber of a Device According to Confidence Level, Test Time and Selectivity - A method for testing the error ratio BER of a device under test against a specified allowable error ratio comprises the steps: measuring ns samples of the output of the device, thereby detecting ne erroneous samples of these ns samples, defining BER(ne)=ne/ns as the preliminary error ratio and deciding to pass the device, if the preliminary error ratio BER(ne) is smaller than an early pass limit EPL(ne). The early pass limit is constructed by using an empirically or analytically derived distribution for a specific number of devices each having the specified allowable error ratio by separating a specific portion DD of the best devices from the distribution for a specific number of erroneous samples ne and proceeding further with the remaining part of the distribution for an incremented number of erroneous samples. | 12-25-2008 |
20090006910 | SELECTIVE HYBRID ARQ - Briefly, in accordance with one or more embodiments, a HARQ process may be selectively executed according to longer term and/or shorter term packet error rate statistics to be within one or more requirements of an application. As result, the number of retransmissions for the HARQ process may be reduced or minimized. | 01-01-2009 |
20090019326 | Self-synchronizing bit error analyzer and circuit - A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set. | 01-15-2009 |
20090049347 | Method and apparatus for bit error determination in multi-tone transceivers - A transceiver with a plurality of components coupled to one another to form a transmit path and a receive path for multi-tone modulation of user data across a communication medium. The transceiver includes a framer and a deframer. The framer is configured to momentarily suspend framing of user data before processing bits associated with tones targeted for reference data transport and injects the pre-agreed reference pattern therein, after which framing of user data resumes. The deframer is configured to momentarily suspend deframing of received user data bits before processing bits associated with tones targeted for transport of pre-agreed reference data and extracts the received reference bits thereof for comparison with the corresponding pre-agreed reference bits to determine errors therein, after which deframing of user data resumes. | 02-19-2009 |
20090070642 | SYSTEM AND METHOD OF DYNAMICALLY MAPPING OUT FAULTY MEMORY AREAS - An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and each bit in the physical memory fault table can represent an equal block of the memory. | 03-12-2009 |
20090077432 | Semiconductor Memory Device - Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. | 03-19-2009 |
20090077433 | SELF-HEALING LINK SEQUENCE COUNTS WITHIN A CIRCULAR BUFFER - Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into a transmit buffer allowing the transmitting device to begin transmitting packets with the sequence count expected by the receiving device. | 03-19-2009 |
20090089630 | METHOD AND SYSTEM FOR ANALYSIS OF A SYSTEM FOR MATCHING DATA RECORDS - Embodiments disclosed herein provide a system and method for analyzing an identity hub. Particularly, a user can connect to the identity hub, load an initial set of data records, create and/or edit an identity hub configuration locally, analyze and/or validate the configuration via a set of analysis tools, including an entity analysis tool, a data analysis tool, a bucket analysis tool, and a linkage analysis tool, and remotely deploy the validated configuration to an identity hub instance. In some embodiments, through a graphical user interface, these analysis tools enable the user to analyze and modify the configuration of the identity hub in real time while the identity hub is operating to ensure data quality and enhance system performance. | 04-02-2009 |
20090100301 | RECEPTION DEVICE, RECEPTION METHOD, INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - A reception device configured to receive a signal of a transmitted bit string transmitted from a transmission device which transmits a bit string includes: a receiving unit arranged to receive a signal from the transmission device and output a received bit string corresponding to the transmitted bit string; a storing unit arranged to store an error rate table wherein said received bit string is correlated with an error rate of post-data which is data of one bit or greater received following the received bit string being in error; and an error correcting unit arranged to perform error correcting of the post-data of the received bit string. | 04-16-2009 |
20090138767 | Self-diagnostic circuit and self-diagnostic method for detecting errors - A self-diagnostic circuit includes a setting unit receiving a plurality of detection signals generated in an integrated circuit device, and determining a type of detection signal to be detected among the received plurality of detection signals. A counter is coupled to the setting unit and counts a number of a signal corresponding to the type of the detection signal to be detected. | 05-28-2009 |
20090164854 | System And Method For Measuring And Depicting Performance Of A Serial Communications Link - A system for measuring performance of a serial communications link includes a system under test including at least one transmitter and at least one receiver coupled together via a serial data communications link, wherein at least one of the transmitter and the receiver has at least one tunable parameter, at least one controller coupled to at least one of a transmitter and a receiver via a joint test action group JTAG interface, and logic configured to perform a bit error ratio test (BERT) at a plurality of receiver phase locations over a defined time period and concluding the BERT for a particular phase location if a BERT error count is greater than 0 at the particular phase location. | 06-25-2009 |
20090177931 | Memory device and error control codes decoding method - Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device. | 07-09-2009 |
20090177932 | METHOD AND APPARATUS FOR TRACKING, REPORTING AND CORRECTING SINGLE-BIT MEMORY ERRORS - Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data. | 07-09-2009 |
20090193301 | Semiconductor memory device and refresh period controlling method - Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors. | 07-30-2009 |
20090199056 | MEMORY DIAGNOSIS METHOD - A method of an apparatus for diagnosing a memory including a storing module for storing diagnosis information relating to memory errors in a memory to be diagnosed, the apparatus capable of detecting memory errors, the method includes: testing the memory and detecting a memory error for each of a plurality of areas of the memory; dividing at least one of the areas into a plurality of sub-areas upon detection of a memory error in the at least one of the areas; testing the sub-areas and detecting a memory error for each of the plurality of the sub-areas; counting the number of sub-areas where a memory error is detected; and storing information of the number of the sub-areas where a memory error is detected together with information of the at least one of the areas containing the sub-areas into the storing module. | 08-06-2009 |
20090210757 | Anti-Jamming Piecewise Coding Method for Parallel Inference Channels - A method for encoding includes encoding K blocks of information for transmission on N subchannels responsive to a number of redundant blocks M according to one of i) employing a single parity check code when the number of redundant blocks M is about 1; ii) employing a code exhibited by a code graph having one third of variable nodes are connected to one of the check nodes, another one third of variable nodes is connected to the other check node and the remaining one third of variable nodes is connected to both check nodes, when the number of redundant blocks M is 2; iii) employing a first process for determining a code for the K blocks of information, when the number of redundant blocks M is about 3 together with K blocks of information less than about 150 or the number of redundant blocks M is about 4 together with K blocks of information less than about 20; and iv) employing a second process for determining a code for the K blocks of information with redundant block M values other than for steps i), ii) and iii). | 08-20-2009 |
20090217110 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT INVOLVING ERROR THRESHOLDS - A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value. | 08-27-2009 |
20090222701 | Apparatus for determining number of bits to be stored in memory cell - Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell. | 09-03-2009 |
20090235128 | Data detecting apparatus based on channel information and method thereof - An apparatus and a method for detecting data stored in a memory cell based on channel information of the memory cell are provided. The data detecting apparatus may include a voltage comparison unit that compares a plurality of soft decision reference voltages between neighboring hard decision reference voltages with a threshold voltage of a memory cell to determine a region including the threshold voltage, and a data detection unit that detects data stored in the memory cell based on channel information of the memory cell according to the region. The data detecting apparatus may further include a reference voltage determination unit that determines the plurality of soft decision reference voltages based on the channel information of the memory cell. | 09-17-2009 |
20090235129 | Apparatus and method for hybrid detection of memory data - The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit. | 09-17-2009 |
20090259894 | ERROR CORRECTION FOR DISK STORAGE MEDIA - Embodiments of the invention provide methods and systems for improving the reliability of data stored on disk media. Logical redundancy is introduced into the data, and the data within a logical storage unit is divided into sectors that are spatially separated by interleaving them with sectors of other logical storage units. The logical redundancy and spatial separation reduce or minimize the effects of localized damage to the storage disk, such as the damage caused by a scratch or fingerprint. Thus, the data is stored on the disk in a layout that improves the likelihood that the data can be recovered despite the presence of an error that prevents one sector from being read correctly. | 10-15-2009 |
20090282299 | EVALUATION METHOD OF RANDOM ERROR DISTRIBUTION AND EVALUATION APPARATUS THEREOF - A degree of conformity of error distribution of a digital signal to the Poisson distribution is quantitatively determined. The digital signal including error data, which is randomly generated at a predetermined error rate, is divided into data number of measurement units, wherein the data number is determined on the basis of the error rate. A sample number of the measurement units are acquired from the measurement units, and the number of errors contained in each measurement unit is measured as a measurement value. Further, the number of times of occurrence of each measurement value is calculated, a Poisson distribution function is calculated, and a degree of a bond between the Poisson distribution and the distribution of the number of times of occurrence is determined by using the chi-square goodness-of-fit test method. | 11-12-2009 |
20090287969 | ELECTRONIC APPARATUS AND BIT ERROR RATE TOLERANCE METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DEVICES - The present invention provides an apparatus and method for using a bit error rate tolerance (BERT) technique for high-speed programming of non-volatile electronic memory devices. The device programmer is comprised of an embedded computer system and specialized electronic circuitry to interface to the device to be programmed. According to one aspect of the invention, the device programmer contains digital registers to accumulate the number of incorrect data bits encountered during the verification of the device programming operation. A field-programmable input to the device programmer specifies the BERT to be allowed at precise intervals within the device. Devices that are found to exceed the specified BERT shall be rejected. | 11-19-2009 |
20090287970 | COMMUNICATION TERMINAL DEVICE AND RECEPTION ENVIRONMENT REPORTING METHOD - A communication terminal device and a reception environment reporting method produce a more excellent throughput, by making a report of a reception environment with higher accuracy. An SIR measuring section measures an SIR from a reception signal that has been received from a base transceiver station. A CQI converter converts the SIR that has been measured by the SIR measuring section into a CQI value. A BLER calculating section calculates a block error rate of the reception signal. A CQI correcting section corrects the CQI value that has been calculated by the CQI converter, in accordance with the block error rate. A CQI transmitter transmits the CQI value that has been corrected by the CQI correcting section, to the base transceiver station. | 11-19-2009 |
20090307542 | MEMORY MEDIA CHARACTERIZATION FOR DEVELOPMENT OF SIGNAL PROCESSORS - Methods and apparatus utilizing media characterization of memory devices facilitate the development of signal processors for analyzing memory device outputs. Models are developed from capturing output of memory devices of the type utilizing analog signals to communicate data values of two or more bits of information. The models are used to generate signals representative of the expected output of a memory device having an input data pattern. Read channels and/or controllers then process those signals to determine an output data pattern. By comparing the output data pattern to the input data pattern, the accuracy of the signal processing can be gauged. | 12-10-2009 |
20090319838 | DETERMINING CONTRIBUTION OF BURST NOISE TO DATA ERRORS - A method for determining a contribution of burst noise to a bit error rate in a digital system for reception of an interleaved forward error correction-enabled digital symbol stream is described. The method is based on identifying errored symbols at a decoding stage, determining their positions in the interleaved stream, and performing a windowing operation such that the errored symbols located within the window in the interleaved stream are designated as burst errored symbols. A corresponding digital receiver and a digital transmission system are also disclosed. | 12-24-2009 |
20090327821 | ACCUMULATED ERROR TIME MONITORING DIAGNOSTIC CONTROL SYSTEM - A diagnostic system includes N dedicated diagnostic modules that each correspond with a respective one of multiple control systems. The N dedicated diagnostic modules each generate status signals indicating results of respective diagnostic tests. A diagnostic error time monitor determines an accumulated error time value between error events for each of the control systems based on the status signals. The diagnostic error time monitor selectively reports a fault to a respective one of the N dedicated diagnostic modules based on the accumulated error time value. | 12-31-2009 |
20100005349 | ENHANCED MICROPROCESSOR INTERCONNECT WITH BIT SHADOWING - A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate. | 01-07-2010 |
20100011260 | MEMORY SYSTEM - To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. | 01-14-2010 |
20100031096 | INTERNAL FAIL BIT OR BYTE COUNTER - Briefly, in accordance with one or more embodiments, an internal fail byte counter is disclosed. | 02-04-2010 |
20100042876 | System and Method for Wireless Transmission Using Hybrid ARQ Based on Average Mutual Information Per Bit - A method and system for packet transmission in a hybrid automatic repeat request (ARQ) system. A modulation and a block length for a transmission are determined based on the average mutual information per bit. The average mutual information per bit is computed based on a current channel signal-to-noise ratio and a plurality of previous transmissions, each being transmitted with a respective coded block length, modulation form, and signal-to-noise ratio. A block error rate is computed for the potential block lengths and modulations based on the average mutual information per bit, and a throughput of the current transmission is determined based on the block error rate. The modulation form and the block length of the transmission are determined based on an analysis of the throughput. If the receiver cannot decode the current transmission, the transmitter repeats the computation to determine the modulation and the block length for retransmission. | 02-18-2010 |
20100042877 | Systems and Methods for Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the soft output and the data signal, and to assert a defect indication based at least in part on the soft output and the data signal. The gating circuit is operable to modify the soft output of the detector whenever the defect indication is asserted. | 02-18-2010 |
20100050028 | NETWORK DEVICE AND METHOD FOR SIMULTANEOUSLY CALCULATING NETWORK THROUGHPUT AND PACKET ERROR RATE - A network device and a method simultaneously calculates network throughput and packet error rate of a device under test (DUT). The network device, communicating with a server via the DUT, transforms TCP data packets to IP data packets, transmits the IP data packets to the server via the DUT, records size of total number of the TCP data packets, time cost for transmitting the TCP data packets to the server, and a first number of the IP data packets transmitted by the network device, and obtains a second number of the IP data packets that are received by the server. The network device further calculates the network throughput of the DUT according to the size and the time, and calculates the packet error rate of the DUT according to the first number and the second number of the IP data packets. | 02-25-2010 |
20100058125 | DATA DEVICES INCLUDING MULTIPLE ERROR CORRECTION CODES AND METHODS OF UTILIZING - A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold. | 03-04-2010 |
20100064185 | Link Performance Abstraction for ML Receivers based on RBIR Metrics - A PHY abstraction mapping between the link level and system level performance is presented based on mapping between the mean RBIR (Received Bit Information Rate) of the transmitted symbols and their received LLR values after symbol-level ML detection in SISO/MIMO wireless systems, such as WiMAX. In MIMO antenna configuration, the mapping is presented for both vertical and horizontal encoding. An embodiment of this invention provides the PER/BLER prediction in the actual system, enabling the system to use more aggressive methods to improve the system performance. | 03-11-2010 |
20100070808 | METHOD AND APPARATUS FOR REDUCING POSITRON EMISSION TOMOGRAPHY (PET) EVENT LOSSES BY EFFECTIVE BANDWIDTH UTILIZATION - An event data transmission scheme is provided for reducing positron emission tomography event losses. The event data transmission scheme employs a more effective use of available data bandwidth. Each of a plurality of detector data slots is connected directly to a data aggregation control interface, and the control interface is connected to a coincidence processor. | 03-18-2010 |
20100077266 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector. | 03-25-2010 |
20100083060 | SYSTEM AND METHOD FOR MPEG CRC ERROR BASED VIDEO NETWORK FAULT DETECTION - Disclosed herein are systems, methods, and computer readable-media for detecting and identifying network faults. The method includes recording cyclic redundancy check (CRC) errors gathered by a data stream analyzer, if the number of CRC errors exceeds a threshold, sending a notification to an automated fault manager which (1) analyzes the number of CRC errors, (2) determines a cause of the CRC errors, and (3) takes appropriate corrective action based on the analysis. The method can further include storing CRC error measurements in a log organized by date and time, analyzing stored CRC error measurements to anticipate future CRC errors, and taking preventive action in advance of anticipated future CRC errors. The automated fault manager can be a rule-based fault/performance management system. The notification can be a Simple Network Management Protocol (SNMP) trap. The data stream analyzer can be an MPEG transport stream analyzer. The automated fault manager can be a video provider or a part of a network management system. The threshold can be either dynamic or static and can be based on video stream priority. | 04-01-2010 |
20100088557 | SYSTEMS AND METHODS FOR MULTIPLE CODING RATES IN FLASH DEVICES - A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the flash memory location; and selecting the encoding rate as a function of the effective error rate such that the number of redundancy bytes is sufficient to overcome the anticipated rate of expected reading errors with a predetermined degree of certainty. | 04-08-2010 |
20100095166 | Protocol Aware Error Ratio Tester - A method and an apparatus for testing the physical layer of high speed serial communication devices and systems with a protocol aware test and measurement system is disclosed. This system includes two major units, a General Purpose Platform (GPP) that includes a protocol awareness and is capable of traffic generation and reception at a protocol level, and an Analog Front End (AFE) that includes physical layer testing capabilities. Physical layer testing is divided into two sets of testing procedures: Receiver testing and Transmitter testing. This test system can be used in a traditional BERT setting where the test system commands the Device Under Test (DUT) to be placed into either a loop back mode and the tester is expecting the same bit flow it transmitted, coming back from the DUT, or into a more advanced mode where the test system is in communication with the DUT like a protocol exerciser and counts the frame error ratio while stressing the DUT. This frame error ratio is protocol dependent and each protocol receiver has its own way of reporting transmission errors to the transmitter. The protocol awareness of this invention is capable of detecting such a level of errors. | 04-15-2010 |
20100107020 | CALCULATION APPARATUS, CALCULATION METHOD, PROGRAM, RECORDING MEDIUM, TEST SYSTEM AND ELECTRONIC DEVICE - Provided is a calculating apparatus that calculates a characteristic of a target signal, comprising a designating section that receives a designation of either a bit error rate or a sampling timing; and a calculating section that calculates a range of sampling timings over which the bit error rate is less than a designated value or a bit error rate at a designated sampling timing by using a relational expression between the sampling timing and the bit error rate in a transmission model for transmitting a signal having jitter that includes a random component and a deterministic component having a prescribed probability density distribution, the relational expression achieved by substituting, as parameters, a standard deviation of a random component in jitter of the target signal and a peak-to-peak value of a deterministic component in the jitter of the target signal. | 04-29-2010 |
20100107021 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold. | 04-29-2010 |
20100122127 | METHOD AND SYSTEM FOR CORRECTING BURST ERRORS IN COMMUNICATIONS NETWORKS, RELATED NETWORK AND COMPUTER-PROGRAM PRODUCT - The errors that may occur in transmitted numerical data on a channel affected by burst errors, are corrected via the operations of: ordering the numerical data in blocks each comprising a definite number of data packets; generating for each block a respective set of error-correction packets comprising a respective number of correction packets, the respective number identifying a level of redundancy for correcting the errors; and modifying dynamically the level of redundancy according to the characteristics of the bursts and of the correct-reception intervals between two bursts. Preferential application is on local networks, such as W-LANs for use in the domestic environments. | 05-13-2010 |
20100125764 | ERROR RATE ESTIMATION/APPLICATION TO CODE-RATE ADAPTION - The disclosure proposes bit-error-rate (BER) and symbol-error-rate (SER) estimation techniques and its application to incremental-redundancy and rate-adaptation for modern-coded hybrid-ARQ systems. In particular, BER/SER estimators are proposed based on iterative refinement of mixture-density modeling of the bit/symbol decision metrics. For hybrid-ARQ systems, rate-adaptation functions are proposed based on BER/SER estimators for failed transmissions. Methods are disclosed for code-rate selection based on successfully decoded blocks as well as incremental parity size selection for retransmission of failed blocks Techniques disclosed here apply to forward-error-correction codes employed for digital data communication systems. | 05-20-2010 |
20100131807 | DECODING ALGORITHM FOR QUADRATIC RESIDUE CODES - A decoding algorithm for quadratic residue codes applicable to the decoding of all quadratic residue codes is provided. The decoding algorithm employs digital signals to obtain a plurality of known syndromes. These known syndromes are used to calculate a plurality of unknown syndromes. The inverse-free Berlekamp-Massey algorithm is then used to calculate the error polynomial, after which the Chien search algorithm is used to determine the error locations. Adjustments can then be made to the digital signal bits corresponding to the error locations to obtain the correct code. | 05-27-2010 |
20100162055 | MEMORY SYSTEM, TRANSFER CONTROLLER, AND MEMORY CONTROL METHOD - A memory system includes a nonvolatile memory, a volatile buffer memory connected to the nonvolatile memory, an error counting unit that detects, for each of divided areas formed by dividing a storage area of the volatile buffer memory into a plurality of areas, a parity error in inputting data to and outputting data from the divided areas and counts a number of times of accumulation of the parity error, and a control unit that sets the divided area, in which the number of times of accumulation of the parity error counted by the error counting unit exceeds a predetermined number of times, in a disabled state. | 06-24-2010 |
20100169723 | LINK ADAPTATION IN WIRELESS NETWORKS - An embodiment of a system for physical link adaptation in a wireless communication network such as e.g., a WLAN, selectively varies the physical mode of operation of the transmission channels serving the mobile stations in the network. The system includes an estimation module to evaluate transmission losses due to collisions as well as transmission losses due to channel errors over the transmission channel, and an adaptation module to select the physical mode of operation of the transmission channel as a function of the transmission losses due to collisions and to channel errors as evaluated by the estimation module. | 07-01-2010 |
20100169724 | METHOD AND SYSTEM FOR RECOGNIZING RADIO LINK FAILURES ASSOCIATED WITH HSUPA AND HSDPA CHANNELS - A method and system for detecting radio link (RL) failures between a wireless transmit/receive unit (WTRU) and a Node-B are disclosed. When signaling radio bearers (SRBs) are supported by high speed uplink packet access (HSUPA), an RL failure is recognized based on detection of improper operation of at least one of an absolute grant channel (AGCH), a relative grant channel (RGCH), a hybrid-automatic repeat request (H-ARQ) information channel (HICH), an enhanced uplink dedicated physical control channel (E-DPCCH) and an enhanced uplink dedicated physical data channel (E-DPDCH). When SRBs are supported by high speed downlink packet access (HSDPA), an RL failure is recognized based on detection of improper operation of at least one of a high speed shared control channel (HS-SCCH), a high speed physical downlink shared channel (HS-PDSCH) and a high speed dedicated physical control channel (HS-DPCCH). | 07-01-2010 |
20100174953 | COMMUNICATION APPARATUS AND CONTROL METHOD THEREOF - A communication apparatus complying with the ITU-T Recommendations v.34 and control method thereof are disclosed. The communication apparatus predicts a timing at which reception of image data in an amount of the error frames sent from another communication device is terminated, based on the number of error frames which are not normally received when receiving image data from the another communication device through a primary channel. The communication apparatus controls to shift from the primary channel to a control channel in accordance with the predicted timing when the image data is received in an amount of the error frames on the primary channel from the another communication device. | 07-08-2010 |
20100174954 | NON-POLYNOMIAL PROCESSING UNIT FOR SOFT-DECISION ERROR CORRECTION CODING - A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method. | 07-08-2010 |
20100180166 | Error Correcting DPCM Transcoding - A digital system is provided that converts compressed data using an indexed transcoding lookup table. A stream of compressed data samples has data samples that represent one of n values corresponding to the first compression format. The transcoding table has at least n indexed entries, and each of the n indexed entries contains a data value corresponding to a second compression format. The transcoding table is accessed by using each of a portion of the received data samples as an index into the table to form a set of transcoded data samples that have a second compression format. The set of transcoded data samples form a stream of compressed data samples that have the second compression format. The transcoding table may be augmented to perform transcoding error correction by concatenating an error value with the data sample to index the table. | 07-15-2010 |
20100211833 | SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS - A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks. | 08-19-2010 |
20100229053 | METHOD AND APPARATUS FOR TIME VERNIER CALIBRATION - Disclosed is a method and apparatus for calibrating a time vernier with an input data signal, a reference signal and a third trigger signal, all of which have pre-defined related frequencies so as to allow for accurate determination of vernier delays and strobe placement in an ATE system. | 09-09-2010 |
20100229054 | WIRELESS COMMUNICATION APPARATUS - A wireless communication apparatus performs data communication with a base station using a plurality of transport channels (TRCHs) that share a frequency band, and selects a reference TRCH using coding schemes of data to be transmitted using the TRCHs. After that, the wireless communication apparatus performs outer loop control so that a block error rate (BLER) of the data to be transmitted using the reference TRCH is set to a target BLER. | 09-09-2010 |
20100235690 | BITMAP CLUSTER ANALYSIS OF DEFECTS IN INTEGRATED CIRCUITS - A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When a defect data set is received, the system and method start with a fail bit and search for neighboring fail bits. The specified radius is used to qualify the found fail bits to be part of the bit cluster or not. If a minimum count of fail bits is not met, the system and method will stop searching and move to the next fail bit. If a minimum count of fail bits is met, the search continues for the next fail bit until the maximum fail bit count specified by the user is reached. Aggregation is provided such that once bit clusters have been classified, the number of clusters that have the exact match or partial match to each other is counted. The user may set the partial match as a threshold count to establish a match. | 09-16-2010 |
20100241912 | Fast bit-error rate calculation mode for QKD systems - A fast bit-error rate (F-BER) calculation mode for a QKD system is disclosed, wherein the method includes establishing versions of a sifted key in respective sifted-bits (SB) buffers in respective QKD stations (Alice and Bob). The method also includes sending Alice's version of the sifted key to Bob, and Bob performing a comparison of the two sifted key versions. The number of bit errors between the two sifted key versions relative to the length of the sifted key yields the F-BER. The F-BER is calculated much more quickly than the conventional BER calculation (“N-BER”), which involves performing a relatively complex error-correction algorithm. The F-BER calculation mode is particularly useful in quickly setting up and/or calibrating a QKD system, and can be repeated quickly to provide updated BER measurements after each QKD system adjustment. | 09-23-2010 |
20100241913 | FLEXIBLE, DENSE LINE CARD ARCHITECTURE - The disclosure relates to optical fiber transmission systems, and in particular, pertains to the transceiver cards in an optical fiber transport system. In particular the disclosure teaches an improved transceiver card architecture that allows high density, flexibility and interchangeability of functionality. | 09-23-2010 |
20100251038 | DECODING ERROR DETECTION METHOD AND DECODING DEVICE IN RADIO COMMUNICATIONS SYSTEM - A decoding device includes a decoding unit that decodes control data to generate decode data, the control data indicating a state of a radio propagation channel; a reliability calculating unit that calculates a reliability indicator indicating a reliability of the decode data; and an outputting unit that outputs decode data whose reliability indicator is larger than a specified threshold; wherein the reliability calculating unit calculates the reliability indicator of decode data to be decoded, based on a similarity indicator indicating a similarity between the decode data to be decoded and previous decode data whose reliability indicator is larger than the threshold. | 09-30-2010 |
20100251039 | MEMORY DEVICE - A first module calculates a failure occurrence risk index of each data storage area address. A second module calculates a power saving index of each data storage area address. A third module calculates an access speed index per unit data volume necessary to access each data storage area address. A fourth module generates a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed. A fifth module selects a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distributes the data to the candidate address. | 09-30-2010 |
20100287423 | TAIL EXTRAPOLATOR AND METHOD - This invention discloses a method which comprises quantizing an input signal. The number of equal quantized values during a period of time is counted thereby obtaining said number of counts ( | 11-11-2010 |
20100313084 | SEMICONDUCTOR STORAGE DEVICE - As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value. | 12-09-2010 |
20100318861 | MODE SELECTION FOR DATA TRANSMISSION IN WIRELESS COMMUNICATION CHANNELS BASED ON STATISTICAL PARAMETERS - A method and communication system for selecting a mode for encoding data for transmission in a wireless communication channel between a transmit unit and a receive unit. The data is initially transmitted in an initial mode and the selection of the subsequent mode is based on a selection of first-order and second-order statistical parameters of short-term and long-term quality parameters. Suitable short-term quality parameters include signal-to-interference and noise ratio (SINR), signal-to-noise ratio (SNR), power level and suitable long-term quality parameters include error rates such as bit error rate (BER) and packet error rate (PER). The method of the invention can be employed in Multiple Input Multiple Output (MIMO), Multiple Input Single Output (MISO), Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) communication systems to make subsequent mode selection faster and more efficient. Furthermore the method can be used in communication systems employing various transmission protocols including OFDMA, FDMA, CDMA, TDMA. | 12-16-2010 |
20100332922 | METHOD FOR MANAGING DEVICE AND SOLID STATE DISK DRIVE UTILIZING THE SAME - A solid state disk drive is provided. The solid state disk drive includes a multiple level cell (MLC) memory device and a controller. The MLC memory device includes memory blocks each comprising memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner. | 12-30-2010 |
20110010592 | INFORMATION TRANSMITTING METHOD AND INFORMATION TRANSMITTING SYSTEM - Information transmitting arrangements for transmitting information through a plurality of base stations from a master station to a plurality of slave stations which communicate with the base stations. | 01-13-2011 |
20110022904 | MODEM-ASSISTED BIT ERROR CONCEALMENT FOR AUDIO COMMUNICATIONS SYSTEMS - Systems and methods are described for managing bit errors present in a series of encoded bits representative of a portion of an audio signal, wherein the series of encoded bits is received over a communication link in an audio communications system. At least one characteristic of a portion of a received modulated carrier signal that is demodulated to produce the series of encoded bits is determined. A number of bit errors present in the series of encoded bits is then determined based on the at least one characteristic. Based on the estimated number of bit errors, one of a plurality of methods for producing a series of digital audio samples representative of the portion of the audio signal is selectively performed. The series of digital audio samples produced by the selected method is then converted into a form suitable for playback to a user. | 01-27-2011 |
20110029826 | Systems and Methods for Re-using Decoding Parity in a Detector Circuit - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving an LDPC codeword, and grouping active bits from the LDPC codeword into a series of data bits including one or more user data bits including and at least one LDPC parity bit. The series of data bits satisfies an LDPC parity equation. | 02-03-2011 |
20110035634 | STORAGE DEVICE WITH ADAPTIVE ERROR-CORRECTING CODE FOR IMPROVED AREAL EFFICIENCY - A method for adaptively applying an error-correcting code to a storage device is disclosed. A determination is made that a system is in an idle state of input/output requests. First data symbols are copied into a first location within a buffer. First data symbol errors corrected using a first error-correcting code. Second data symbols including corrected bits are written in a second location on the recording media with a second error-correcting code. An error number for the second data symbols in the second location is determined. If the error number is below a first threshold error number, the first data symbols are deleted. If the error number is above the first threshold error number, the second data symbols are deleted. | 02-10-2011 |
20110055643 | RECEIVER POWER SAVING VIA BLOCK CODE FAILURE DETECTION - A communication system includes a receiver configured to receive a packet that contains plural codewords, and a codeword failure detector cooperatively operable with the receiver. The codeword failure detector can be configured to detect a codeword failure in at least one codeword of the plural codewords as it is being received by the receiver, and to terminate reception at the receiver, when the codeword failure is detected before the end of the packet, to put the receiver into a power save mode for a duration of a remainder of the packet that contains the at least one codeword. | 03-03-2011 |
20110066900 | NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A non-volatile memory device including: a memory cell array storing an electrically rewritable resistance value as data in a non-volatile manner; a first cache circuit configured to hold program data to be programmed in the cell array; a second cache circuit configured to hold preprogrammed data read from an area of the cell array; and a judging circuit configured to compare and check the program data with the preprogrammed data, and judge whether there are one or more disagreement bits therebetween or not. | 03-17-2011 |
20110066901 | Automated Quality Management System - Various embodiments of the invention provide methods and systems for automated quality management and/or monitoring of organization operations, including for example data processing operations. In one aspect of the invention, a quality management system uses an error rate measurement module to automatically monitor the quality of an organizational operation. Information is processed by the organizational operation. The error rate measurement module samples the processed information. It also automatically determines, without human intervention, an error rate based on the sampled information. The error rate accounts for both a frequency of errors and an operational impact of errors. | 03-17-2011 |
20110087933 | POWER CONSUMPTION IN LDPC DECODER FOR LOW-POWER APPLICATIONS - This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders. | 04-14-2011 |
20110099437 | Loss Tolerant Transmission Control Protocol - A particular device includes a transmitter. The transmitter is adapted to estimate a packet erasure rate for packets of a data window to be transmitted to a receiver. The transmitter is adapted to determine a number of proactive forward error control (FEC) packets for the data window based on the estimated packet erasure rate. The transmitter is adapted to determine a packet size for the packets in the data window based on a window size of the data window and the determined number of proactive FEC packets. The transmitter is also adapted to transmit the data window to the receiver. The packets in the transmitted data window have a size corresponding to the determined packet size and include the determined number of proactive FEC packets. | 04-28-2011 |
20110107160 | TIME-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY - A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount. | 05-05-2011 |
20110113294 | TUNABLE EARLY-STOPPING FOR DECODERS - A method of decoding channel outputs using an iterative decoder to provide hard decisions on information bits includes activating each SISO decoder of the iterative decoder to provide soft-decisions associated with the information bits. The method also includes computing a fidelity estimate and stopping decoding based on the fidelity estimate. | 05-12-2011 |
20110119536 | Estimating Bit Error Rate Performance of Signals - A system for estimating bit error rates (BER) may include using a normalization factor that scales a BER to substantially normalize a Q-scale for a distribution under analysis. A normalization factor may be selected, for example, to provide a best linear fit for both right and left sides of a cumulative distribution function (CDF). In some examples, the normalized Q-scale algorithm may identify means and probabilistic amplitude(s) of Gaussian jitter contributors in the dominant extreme behavior on both sides of the distribution. For such contributors, means may be obtained from intercepts of both sides of the CDF(Qnorm(BER) with the Q(BER)=0 axis, standard deviations (sigmas) may be obtained from reciprocals of slopes of best linear fits, and amplitudes may be obtained directly from the normalization factors. In an illustrative example, a normalized Q-scale algorithm may be used to accurately predict bit error rates for sampled repeating or non-repeating data patterns. | 05-19-2011 |
20110145663 | Read level control apparatuses and methods - Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate. | 06-16-2011 |
20110191644 | Method and apparatus for SAS speed adjustment - A method for maintaining reliable communication on a bidirectional communication link is provided. A receiver on the bidirectional communication link detects an error and maintains a count of detected errors. The transmitter on the bidirectional communication link polls the receiver in order to determine the count of detected errors, and performs a downshift evaluation for the bidirectional communication link. In response to performing the downshift evaluation for the bidirectional communication link, the transmitter maintains a transmission speed of the bidirectional communication link if the downshift evaluation determines that forgoing transmission speed downshift is required for the bidirectional communication link, and reduces the transmission speed of the path if the downshift evaluation determines that transmission speed downshift is required for the bidirectional communication link. | 08-04-2011 |
20110191645 | METHOD AND APPARATUS FOR ADJUSTING NUMBER OF ITERATIONS IN ITERATIVE DECODING PROCEDURE - In a method of determining an iteration value for an iterative decoding process of a hard disk drive, a bit error rate (BER) of a digital signal is measured in multiple iterations. A difference is calculated between BERs of consecutive iterations, and the calculated differences are compared with a reference value. An adjusted iteration value is then determined based on the comparison. | 08-04-2011 |
20110225470 | Serial Interface Device Built-In Self Test - A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined. | 09-15-2011 |
20110239061 | SYSTEMS AND METHODS FOR RETRIEVING DATA - Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not. | 09-29-2011 |
20110258495 | METHODS OF CALCULATING COMPENSATION VOLTAGE AND ADJUSTING THRESHOLD VOLTAGE AND MEMORY APPARATUS AND CONTROLLER - Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage. | 10-20-2011 |
20110258496 | DATA READING METHOD, MEMORY STORAGE APPARATUS AND MEMORY CONTROLLER THEREOF - A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read. | 10-20-2011 |
20110264968 | CABLE WITH FIELD-WRITEABLE MEMORY - A method includes monitoring a use of a cable assembly that includes a communication cable terminated by a termination module. Data indicative of the use is written to a writeable non-volatile memory in the termination module. The use of the cable assembly is acted upon by reading the data from the non-volatile memory. | 10-27-2011 |
20110271155 | Method and Apparatus for Measuring Symbol and Bit Error Rates Independent of Disparity Errors - A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparator compares the reference test pattern with the SUT. The symbol comparator can produce a symbol error rate. One or more 8b to 10b converters receives the SUT from the input and the digitized data from the memory, and converts the data from an 8b coded format to a 10b coded format. A bit comparator compares the 10b coded reference test pattern with the 10b coded SUT in response to the symbol comparator. The bit comparator is coupled to a bit error counter, which produces a bit error rate independent of any disparity errors that may be present in the incoming digitized data received by the test and measurement instrument. | 11-03-2011 |
20110296258 | ERROR CORRECTING POINTERS FOR NON-VOLATILE STORAGE - Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point to the same cell, a precedence rule dictates the array entry with the higher index (the entry created later) takes precedence. To count the number of error correcting pointers in use, a null pointer address can be employed to indicate that a pointer is inactive, an activation bit can be added, and/or a counter, that represents the number of error correcting pointers that are active. Mechanisms are provided for wear-leveling within the error correction structure, or for pairing this scheme with single-error correcting bits for instances where transient failures may occur. The architecture also employs pointers to correct errors in volatile and non-volatile memories. | 12-01-2011 |
20110302466 | SIGNAL TRANSMISSION DEVICE FOR ELEVATOR - Each of a control panel node | 12-08-2011 |
20120030527 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. | 02-02-2012 |
20120030528 | SEMICONDUCTOR STORAGE DEVICE - As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value. | 02-02-2012 |
20120030529 | REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS - In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block. | 02-02-2012 |
20120042219 | States Encoding in Multi-Bit Flash Cells for Optimizing Error Rate - Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2 | 02-16-2012 |
20120060066 | SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION - This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold. | 03-08-2012 |
20120066559 | Built-in Bit Error Rate Test Circuit - System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification. | 03-15-2012 |
20120072784 | CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS - An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc. | 03-22-2012 |
20120072785 | BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER - An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate. | 03-22-2012 |
20120072786 | USE OF HASHING FUNCTION TO DISTINGUISH RANDOM AND REPEAT ERRORS IN A MEMORY SYSTEM - One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table. | 03-22-2012 |
20120079329 | ADAPTIVE WIRELESS VIDEO TRANSMISSION SYSTEMS AND METHODS - A method for providing error-resilient video content may include receiving video data reflective of multiple video frames and encoding the video data to generate a plurality of packets. The method may also include transmitting the first group of packets to at least two receivers and receiving feedback information regarding receiving status of respective ones of the plurality of packets, the feedback information being indicative of packets not received correctly. The method may further include examining error indications based on the feedback information and implementing a first error-correction policy if a variation in the error indications among the at least two receivers is below a first error threshold and a second error-correction policy if the variation is above the first error threshold. At least one of the first and second error-correction policies may include transmitting or retransmitting at least one packet using a different coding scheme. | 03-29-2012 |
20120131395 | METHOD AND APPARATUS FOR REDUCING BIT ERRORS - An apparatus and method for reduction of bit errors in continuous data transmission via a data transmission medium comprising. The apparatus ( | 05-24-2012 |
20120144253 | HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE - A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice. | 06-07-2012 |
20120151285 | METHOD FOR DETECTING THE VALIDITY OF DOWNLINK CONTROL INFORMATION IN TELECOMMUNICATION USER EQUIPMENT, DECODER AND BASEBAND RECEIVER FOR PERFORMING SAME - A method for detecting validity of downlink control information in telecommunication user equipment and a decoder and baseband receiver to perform the method are provided. The object of avoiding falsely detecting payload data and misinterpreting them is achieved by reverse encoding a bit output sequence of a Viterbi decoder; determining hard bits from a soft-bit input sequence of the decoder; determining a bit count of real received bits; comparing the reverse encoded bit stream to the determined hard bit stream and counting the number of mismatches to obtain an error count; comparing a bit error rate which is defined as a quotient of the error count and the bit count against a predefined threshold value; and rejecting the payload as invalid if said bit error rate is above said threshold value, even if a cyclic redundancy check of the payload gives a correct result. | 06-14-2012 |
20120151286 | Cross-Decoding for Non-Volatile Storage - Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages. Alternatively the controller adjusts the allocation to maximize total usable capacity by allocating to redundancy and data for the various pages, assuming that cross-decoding is to be used. | 06-14-2012 |
20120159269 | Measurement Device and Measurement Method - Disclosed is means for quantifying resistance to soft errors in a logic circuit. A logic block group | 06-21-2012 |
20120166895 | MULTICAST DIGITAL VIDEO LOST PACKET RECOVERY - An electronic communication network supports delivery of video program Internet protocol packets. A source device transmits both first and second video program Internet protocol packets. A first recipient device is assigned as positive acknowledgment leader by the source device and a second recipient device is assigned as negative acknowledgement leader by the source device. The first recipient device is operable to transmit to the source device a positive acknowledgment of receipt of the first video program Internet protocol packet. The second recipient device is operable to transmit to the source device a negative acknowledgment of non-receipt upon not receiving the first video program Internet protocol packet. The source device responds to the negative acknowledgement of non-receipt by the second recipient device by multicast resending the second video program Internet protocol packet to both the first and second recipient devices. | 06-28-2012 |
20120173935 | PLUGGABLE TRANSCEIVER MODULE WITH ENHANCED CIRCUITRY - Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links. | 07-05-2012 |
20120185739 | APPARATUS, AND ASSOCIATED METHOD, FOR ESTIMATING A BIT ERROR RATE OF DATA COMMUNICATED IN A COMMUNICATION SYSTEM - Apparatus, and an associated method, for estimating a bit error rate of data communicated to a receiving station of a digital communications system, such as a GSM/EDGE cellular communication system. Soft decision values, indicative of confidence levels that decided values have been correctly decided are compared with threshold values by a comparator. A count is accumulated by a counter to whose counted value is representative of decided data values having associated therewith low levels of confidence that the decided values are correct. The count value is used in the formulation of the BER estimation. | 07-19-2012 |
20120192020 | Detecting and Eliminating Potential Performance Degradation Caused by Neighboring Identical Scrambling Codes - One embodiment of the present invention relates to a method of detecting potential performance degradation caused by neighboring identical scrambling codes. The method includes detecting an existence of identical scrambling codes in received signals from different cell at the user equipment, and selectively eliminating one or more signals from consideration in processing of received signals based upon the detection. The invention also includes a receiver configured to detect potential performance degradation caused by neighboring identical scrambling codes. The receiver includes a detection component configured to detect an existence of identical scrambling codes in received signals from different base stations at the user equipment, and an elimination component configured to selectively eliminate one or more signals from consideration in processing of received signals based upon the detection by the detection component. | 07-26-2012 |
20120226950 | DATA CLASSIFICATION BASED ON CYCLIC REDUNDANCY CHECK AND DECODER METRIC - A method of data classification for use in a wireless communication system includes obtaining decoder metrics from a decoder. The decoder metrics correspond to data generated by the decoder. The decoder metrics include a symbol error rate (SER) and an energy metric (EM). The method also includes classifying the data into a first category if the data fails a cyclic redundancy check (CRC) check, into a second category if the data passes the CRC check and is determined to be unreliable, or into a third category if the data passes the CRC check and is determined to be reliable. A reliability of the data is determined based on the decoder metrics and an EM threshold. | 09-06-2012 |
20120239990 | FLASH STORAGE DEVICE WITH READ DISTURB MITIGATION - A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value. | 09-20-2012 |
20120246525 | METHOD FOR INITIATING A REFRESH OPERATION IN A SOLID-STATE NONVOLATILE MEMORY DEVICE - A method for initiating a refresh operation of a solid-state nonvolatile memory device coupled to a processor is disclosed. The method comprises determining an error number for a block of the solid-state nonvolatile memory. The error number corresponds to an amount of error bits in a page of the block having a greatest amount of error bits. The method further comprises comparing the error number with an error threshold and determining a reset number indicating an amount of times that the processor has been reset since a previous refresh operation was performed on the block of the solid-state nonvolatile memory. The method further includes comparing the number of resets with a reset threshold and refreshing the block of the solid-state nonvolatile memory when the number of errors exceeds the error threshold and the number of resets exceeds the reset threshold. | 09-27-2012 |
20120246526 | Parallelization of Error Analysis Circuitry for Reduced Power Consumption - A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry. | 09-27-2012 |
20120254676 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, CONTROLLING METHOD FOR INFORMATION PROCESSING APPARATUS AND PROGRAM - An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error. | 10-04-2012 |
20120266032 | MLC Self-RAID Flash Data Protection Scheme - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 10-18-2012 |
20120278670 | Image Processing Apparatus - An image processing apparatus of the present disclosure includes: a two-dimensional matrix barcode decoding unit configured to decode a two-dimensional matrix barcode in an image of image data; and a restoration determining unit configured (a) to obtain an error detection rate and error detection position information detected while the two-dimensional matrix barcode is decoded, (b) to compare the error detection rate with a predetermined threshold value, (c) on the basis of the comparison result, to determine whether the two-dimensional matrix barcode should be restored, and (d) to adjust the threshold value according to an error detection position determined from the error detection position information. | 11-01-2012 |
20120284574 | Non-Volatile Memory and Method Having Efficient On-Chip Block-Copying with Controlled Error Rate - A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget. | 11-08-2012 |
20120290887 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION SYSTEM - An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits. | 11-15-2012 |
20130013968 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ANALYZING MONITOR DATA INFORMATION FROM A PLURALITY OF MEMORY DEVICES HAVING FINITE ENDURANCE AND/OR RETENTION - A method according to one embodiment includes gathering information about monitor data from a plurality of memory devices having finite endurance and/or retention, the monitor data being (i) data of known content stored in dedicated memory cells of known write cycle count, and (ii) write protected for preventing the monitor data from being overwritten with user data; analyzing the monitor data information; and taking an action relating to at least one of the devices based on the analyzing. Additional systems, methods, and computer program products are also disclosed. | 01-10-2013 |
20130019129 | METHOD FOR DATA PACKET PROCESSING AT VERY HIGH DATA RATES AND EXTREMELY POOR TRANSMISSION CONDITIONSAANM Lawin; MirkoAACI MeiningenAACO DEAAGP Lawin; Mirko Meiningen DE - Provided are systems and methods for adaptive, error-tolerant pattern recognition in the transmission of digital data packets, in which an actual data pattern, including several bits, is detected and is compared with a theoretical data pattern; erroneous and/or correctly recognized bits are detected; erroneous and/or correctly recognized bits are added up (in each case); and the error sum (number of the errors) of the added-up erroneous bits is compared with a specifiable and changeable admissible maximum number of errors. | 01-17-2013 |
20130024735 | SOLID-STATE MEMORY-BASED STORAGE METHOD AND DEVICE WITH LOW ERROR RATE - Non-volatile solid-state memory-based storage devices and methods of operating the storage devices to have low initial error rates. The storage devices and methods use bit error rate comparison of duplicate writes to one or more non-volatile memory devices. The data set with a lower bit error rate as determined during verification is maintained, whereas data sets with higher bit error rates are discarded. A threshold of bit error rates can be used to trigger the duplication of data for bit error comparison. | 01-24-2013 |
20130036335 | DEVICES AND METHODS FOR BIT ERROR RATE MONITORING OF INTRA-PANEL DATA LINK - Devices and methods for monitoring a bit error rate of an intra-panel data link (e.g., a chip-on-glass (COG) data link) between a timing controller and a display driver are provided. For example, an electronic display according to an embodiment may include a timing controller and display driver circuitry. The timing controller may send test data over a data link to the display driver circuitry. The test data may include a known or predictable stream of data. The display driver circuitry may receive the test data via the data link and detect bit errors based at least partly on the test data. An indication of the bit errors may be displayed on an array of pixels of the display or provided to the timing controller via a separate back channel data link. | 02-07-2013 |
20130042157 | THROUGHPUT IMPROVEMENT IN WIRELESS SYSTEMS - Systems and methods are disclosed for improving throughput in a wireless system utilizing Hybrid Automatic Repeat Request (HARQ) retransmission. In general, prior to a HARQ-enabled transmission, one or more channel conditions for a corresponding transmit channel are obtained. Based on the one or more channel conditions, a set of target block error rates for the HARQ-enabled transmission are determined. In one embodiment, the set of target block error rates maximize throughput for the transmit channel utilizing HARQ retransmission. In another embodiment, the set of target block error rates optimize throughput and one or more additional parameters for the transmit channel utilizing HARQ retransmission. | 02-14-2013 |
20130080845 | INTERFACE WITH UNIVERSAL SERIAL COMMUNICATION - An interface with universal serial communication comprises a switching device, a medium device, and a data restoring device for transmitting the data and obtaining the serial communication via one signal line that is inter-strung by afore devices. By simplifying such communication device, the compatibility thereof could be enhanced. Moreover, during the data transmission, computation made by an error coefficient and an error beyond value in the switching device allows the transmitted data to be kept within an acceptable noise value, so that the accuracy of the data could be assured. | 03-28-2013 |
20130080846 | APPARATUS AND METHOD FOR RECEIVING A SECURE TELEGRAM - An apparatus includes a communication device and an evaluation unit, wherein the communication device can be linked to a communication bus and can receive secure telegrams by way of the communication bus, and wherein a secure telegram includes user data and CRC data in each instance. In at least one embodiment, in order to improve the communication within the secure bus system, the evaluation unit can determine an error rate from received secure telegrams by way of a CRC check and if a threshold value of the error rate stored in the evaluation unit is exceeded, can effect a secure state of the apparatus. | 03-28-2013 |
20130086438 | Systems and Methods for Efficient Parameter Modification - Various embodiments of the present invention provide systems and methods for data processing. | 04-04-2013 |
20130086439 | Systems and Methods for Parameter Selection Using Reliability Information - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, and a reliability monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output that includes soft data. The reliability monitor circuit is operable to determine a proxy error count based at least in part on the soft data, and to modify a parameter governing an operation of the data processing system based at least in part on the proxy error count. | 04-04-2013 |
20130132784 | DEVICE AND METHOD FOR DETERMINING A PHYSICAL QUANTITY - In a method and a device for determining a physical quantity from a number of measured values containing errors, grouping of the number of measured values containing errors into a plurality of subgroups of measured values is executed, wherein each subgroup includes a redundancy, so that more measured values than the number of measured quantities are contained in each subgroup. Hereupon, a reliability quantity for each subgroup is calculated based on the redundancy contained in the subgroup. Further, individual evidence is allocated to the measured values containing errors of each subgroup based on the reliability quantity for the respective subgroups. An evidence determiner determines one overall evidence each for each measured value containing errors based on the individual evidence quantities for a respective measured value. Hereupon, a processor calculates the physical quantity using at least some of the measured values containing errors and at least some of the overall evidences. | 05-23-2013 |
20130145224 | METHOD OF TRANSMITTING DATA BLOCK AND TRANSMITTER USING THE SAME - A method for transmitting a data block in a wireless communication system and a transmitter are provided. The transmitter transmits the data block to a receiver and generates a retransmission block for the retransmission of the data block if it is determined that the transmission fails. The transmitter determines whether the channel access is performed according to a transmit time of the retransmission block. | 06-06-2013 |
20130151911 | REDUCTION IN DECODER LOOP ITERATIONS - An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information. | 06-13-2013 |
20130151912 | ENHANCED ERROR CORRECTION IN MEMORY DEVICES - A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position. | 06-13-2013 |
20130166971 | Method And Apparatus For Encoding Channel Quality Indicator And Precoding Control Information Bits - A method and apparatus for encoding channel quality indicator (CQI) and precoding control information (PCI) bits are disclosed. Each of the input bits, such as CQI bits and/or PCI bits, has a particular significance. The input bits are encoded with a linear block coding. The input bits are provided with an unequal error protection based on the significance of each input bit. The input bits may be duplicated based on the significance of each input bit and equal protection coding may be performed. A generator matrix for the encoding may be generated by elementary operation of conventional basis sequences to provide more protection to a most significant bit (MSB). | 06-27-2013 |
20130185606 | SYSTEMS AND METHODS FOR PROACTIVELY REFRESHING NONVOLATILE MEMORY - System and methods for proactively refreshing portions of a nonvolatile memory are disclosed. A memory system may proactively refresh a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory meeting certain criteria determined from that data may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed. | 07-18-2013 |
20130198577 | MEMORY, MEMORY SYSTEM, AND ERROR CHECKING AND CORRECTING METHOD FOR MEMORY - A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method. | 08-01-2013 |
20130205176 | METHOD AND APPARATUS FOR REDUCING FALSE DETECTION OF CONTROL INFORMATION - A control channel may be used to transmit control information, such as Downlink Control Information (DCI), to a mobile device from a network component, such as a base station or a base node. The mobile device may use a blind decoding scheme to detect DCIs. A DCI may be falsely detected by the mobile device. According to some embodiments, data that has been decoded by a blind decoder, from buffer data for a candidate control channel, is re-encoded. The re-encoded data is compared to buffer data for the control channel. The decoded data is treated as control information dependent on the comparison of the re-encoded data with the buffer data. In some embodiments, comparing the re-encoded data to the buffer data includes generating a metric as a function of a degree of similarity between the re-encoded data and the buffer data. The metric may be compared to a threshold. | 08-08-2013 |
20130219233 | Systems and Methods for Quality Based Priority Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 08-22-2013 |
20130254603 | DECODING METHOD AND DECODING DEVICE - Embodiments of the present invention provide a decoding method and a decoding device. The method includes: performing iterative decoding on a multidimensional code to obtain incorrigible code words; determining locations of error bits in the incorrigible code words that are obtained by performing the iterative decoding on the multidimensional code, where the locations of error bits in the incorrigible code words are multidimensional coordinate locations of the error bits in the multidimensional code; correcting error bits of a part of the incorrigible code words in the multidimensional code according to the determined locations of the error bits in the incorrigible code words; and after the error bits of a part of the incorrigible code words in the multidimensional code are corrected, performing iterative decoding on the multidimensional code The embodiments of the present invention are applicable to the field of decoding technologies. | 09-26-2013 |
20130254604 | METHODS AND APPARATUS FOR ERROR RATE ESTIMATION - Methods and apparatus for estimating received error rates. In one embodiment, the estimation of received error rates is conducted in relation to a bus interface such as a high-speed High-Definition Multimedia Interface (HDMI) interface, and the method utilizes corrupted symbols that violate TMDS symbol rules, the corrupted symbols being easily detected and counted. In one exemplary implementation, a symbol error rate (SER) can be estimated from the number of detected invalid symbols. The SER can be used to diagnose the performance of the HDMI interface, and optionally as a basis for selecting or implementing corrective action(s). | 09-26-2013 |
20130297979 | Methods and Devices to Reduce Outer Code Failure Rate Variability - The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. | 11-07-2013 |
20130311840 | METHOD AND DEVICE FOR ESTIMATING INPUT BIT ERROR RATIO - An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing. | 11-21-2013 |
20130346811 | DECISION FEEDBACK EQUALIZER - A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. | 12-26-2013 |
20130346812 | WEAR LEVELING MEMORY USING ERROR RATE - The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group. | 12-26-2013 |
20140040681 | DEVICE BASED WEAR LEVELING - A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage. | 02-06-2014 |
20140040682 | METHOD AND SYSTEM FOR SYMBOL ERROR RATE ESTIMATION AND SECTOR QUALITY MEASUREMENT - A probabilistic approach of symbol error estimation is disclosed. The probabilistic approach of symbol error estimation reflects the number of symbol errors more precisely than the number of unsatisfied checks. The more precise quality metric calculated in accordance with the present disclosure allows a codec system to achieve a better overall performance. In addition, many other features that previously depend on the number of unsatisfied checks as the sector quality metric may also benefit by adopting the more precise quality metric. | 02-06-2014 |
20140040683 | REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS - In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block. | 02-06-2014 |
20140068357 | Assessment and Correction of Transmitted Data - Methods and systems for improving the quality of transmitted data are described. Multiple distinct communication channels are used to transmit segments representing the same pre-transmission block of a data packet. Upon receipt of these segments, a system identifies differences between the segments for those segments that meet a quality threshold. The system selects one of segments for subsequent transmission or re-assembly into a data packet based on the prior performance of the communication channels used to transmit the segments. | 03-06-2014 |
20140075250 | INTEGRITY CHECK OF MEASURED SIGNAL TRACE DATA - A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying. | 03-13-2014 |
20140082437 | Block And Page Level Bad Bit Line And Bits Screening Methods For Program Algorithm - A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test. | 03-20-2014 |
20140101498 | METHOD FOR ESTIMATING BLOCK ERROR RATE AND COMMUNICATION DEVICE - A method for estimating a block error rate and a communication device are applied to the field of communications technologies. The method for estimating a block error rate includes: decoding N received coded code blocks to obtain multiple posterior probabilities APPs, where N is a natural number greater than 1; obtaining, according to the multiple posterior probabilities APPs and a preset policy, a result indicating that the decoding of each coded code block is correct or incorrect, where the preset policy includes: when a sum of absolute values of the multiple APPs is greater than or equal to a preset threshold, the decoding is correct; and obtaining a decoding block error rate according to a result indicating whether the decoding of the N coded code blocks is correct. In this way, the estimation of a decoding block error rate is implemented. | 04-10-2014 |
20140115410 | Bit Error Rate Estimation for Wear Leveling and for Block Selection Based on Data Type - A method and system for wear balancing in a flash memory device using bit error probability is disclosed. The flash memory device includes blocks with different life spans, leading potentially to one block wearing out before the other. In order to avoid this, a controller is configured to determine a bit error probability of a block and determine, based on the bit error probability, whether to select the block for storage of data. A method and system for selecting a block in a flash memory device based on the type of data is disclosed. The type of data may comprise flash management data (which may be used to manage the flash memory device) and host data. An indication of age associated with the block (such as bit error probability) is analyzed in order to determine whether to store the data in the block based on the type of data. | 04-24-2014 |
20140143616 | DEFECT SCAN AND MANUFACTURE TEST - A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold. | 05-22-2014 |
20140173368 | DETECTING A MEMORY DEVICE DEFECT - A technique includes receiving data indicative of a time varying count of errors, which are attributable to at least one memory device. The technique includes filtering the indicated count and detecting a defect in the memory device(s), where the detecting includes selectively generating an indicator to represent that the memory device(s) is defective based at least in part on a result of the filtering. | 06-19-2014 |
20140181601 | METHOD OF TESTING MULTIPLE DATA PACKET SIGNAL TRANSCEIVERS CONCURRENTLY - A method of testing, such as for a bit error rate (BER), of multiple data packet signal transceivers during which a tester and the data packet signal transceivers exchange sequences of test data packets and summary data packets. The tester provides the test data packets which contain respective pluralities of data bits with respective predetermined bit patterns. Responsive thereto, the data packet signal transceivers provide the summary data packets which contain respective summary data indicative of the number of data bits with the respective predetermined bit patterns that are correctly received by corresponding ones of the data packet signal transceivers. | 06-26-2014 |
20140189446 | FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY - A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER. | 07-03-2014 |
20140195866 | Determining Worst-Case Bit Patterns Based Upon Data-Dependent Jitter - The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements. | 07-10-2014 |
20140223244 | FLASH STORAGE DEVICE WITH READ DISTURB MITIGATION - A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value. | 08-07-2014 |
20140237305 | APPARATUSES AND METHODS FOR COMPRESSING DATA RECEIVED OVER MULTIPLE MEMORY ACCESSES - Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator configured to compare data provided by a group of memory cells associated with a repair address. Each subset of one or more bits of the data is sequentially provided by the group of memory cells responsive to a respective memory access of a plurality of memory accesses. The example compression circuit further including an error bit latch coupled to the comparison circuit. The error bit latch configured to, responsive to an output received from the comparison circuit indicating an error, compress the data to an error bit by setting the error bit to an error detected state and latching the error bit having the error detected state. | 08-21-2014 |
20140258794 | MEMORY PAGE BUFFER - Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes. | 09-11-2014 |
20140281763 | METHOD, APPARATUS, AND SYSTEM FOR MEASUREMENT OF NOISE STATISTICS AND BIT ERROR RATIO ESTIMATION - A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ration determined for a device. | 09-18-2014 |
20140304560 | SHUTDOWNS AND DATA RECOVERY TO AVOID READ ERRORS WEAK PAGES IN A NON-VOLATILE MEMORY SYSTEM - A memory apparatus and methods are provided for preventing read errors on weak pages in a non-volatile memory system. In one example, a method includes identifying a weak page in a non-volatile memory device along a word line, wherein the weak page is partially written with at least some data; buffering data associated with the weak page to a weak page buffer that is coupled in communication with the non-volatile memory device; determining that an amount of data in the weak page buffer has reached a predetermined data level; and writing the data from the weak page buffer into the weak page along the word line in the non-volatile memory device. | 10-09-2014 |
20140331096 | Cross-Decoding for Non-Volatile Storage - Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages. Alternatively the controller adjusts the allocation to maximize total usable capacity by allocating to redundancy and data for the various pages, assuming that cross-decoding is to be used. | 11-06-2014 |
20140359381 | MEMORY CONTROLLER AND DATA STORAGE DEVICE - A memory controller sets an estimated cell error ratio CERest based on an estimated retention time Tret obtained from a calculated bit error ratio BER, a number of rewrite times NW/E, data Datatag of a target cell and data Dataadj of memory cells surrounding the target cell, sets an upper-level page LLRu and a lower-level page LLRl with regard to all bits of read-out one-page data using the set estimated cell error ratio CERest and performs error correction and decoding of data read out from a flash memory using the settings of the upper-level page LLRu and the lower-level page LLRl. This improves the error correction capability, while suppressing an increase in processing time. | 12-04-2014 |
20140372813 | METHOD FOR VERIFYING BAD PATTERN IN TIME SERIES SENSING DATA AND APPARATUS THEREOF - A method for verifying bad pattern in time series sensing data by calculating a bad pattern error rate, which can be applied to the time series sensing data measured and produced from a predetermined sensor provided in predetermined equipment, and an apparatus thereof are provided. The method includes receiving information on the bad pattern applied to time series sensing data measured by a suspicious sensor, accessing the time series sensing data of each product, generated by the suspicious sensor during a verification period, calculating similarity measures between the bad pattern based on the bad pattern information and the time series sensing data for each product, and calculating an error rate of the bad pattern based on the similarity measures. | 12-18-2014 |
20150052408 | GENERATING SOFT READ VALUES WHICH OPTIMIZE DYNAMIC RANGE - A plurality of bins and a plurality of soft read values are stored in a lookup table where those bins that are either a leftmost bin or a rightmost bin correspond to soft read values having a maximum magnitude. Bin identification information is received for a cell in solid state storage. A soft read value is generated for the cell in solid state storage, including by: accessing the lookup table, mapping the received bin identification information to one of the plurality of bins in the lookup table, and selecting the soft read value in the lookup table that corresponds to the bin which is mapped to. | 02-19-2015 |
20150067415 | MEMORY SYSTEM AND CONSTRUCTING METHOD OF LOGICAL BLOCK - According to one embodiment, a memory system includes a bit-error-rate manager configured to manage information associated with a bit error rate for each physical block, a logical-block constructing unit configured to construct a logical block based on the information associated with the bit error rate, and a block manager configured to manage the correspondence between the logical block constructed by the logical-block constructing unit and the physical blocks. The logical block is a collection of a plurality of physical blocks. | 03-05-2015 |
20150067416 | NRZ SIGNAL AMPLIFYING DEVICE AND METHOD, AND ERROR RATE MEASUREMENT DEVICE AND METHOD - To set an optimum offset voltage and detect an NRZ signal with a very small amplitude. An NRZ signal amplifying device | 03-05-2015 |
20150089310 | USE OF ERROR CORRECTION POINTERS TO HANDLE ERRORS IN MEMORY - Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed. | 03-26-2015 |
20150095726 | SNR margin determination based on FEC code and/or ECC decoding statistics - A communication device operates to support communications with one or more other communication devices. The communication device includes a processor and a communication interface to perform various operations including receiving forward error correction (FEC) coded signals from another communication device. The communication device iteratively decodes the FEC coded signals to make estimates of information encoded therein. The communication device then determines an operational error check rate based on error check failure of at least one of the FEC coded signals after performing a predetermined number of decoding iterations (e.g., that is less than a maximum number of decoding iterations performed by the device). The device then determines a signal to noise ratio (SNR) margin of the communication device by applying the operational error check rate to a characterization of the communication device that relates error check rate and SNR. | 04-02-2015 |
20150106666 | Speculative Bit Error Rate Calculator - An apparatus for calculating a speculative bit error rate includes a data decoder operable to iteratively decode received data to yield decoded data, and a speculative bit error calculator operable to calculate a bit error rate based on the decoded data and the received data while the data decoder is decoding the received data. The bit error rate is updated with each decoding iteration in the data decoder. | 04-16-2015 |
20150106667 | SOLID STATE STORAGE DEVICE AND CONTROLLING METHOD THEREOF - A solid state storage device and controlling method thereof are provided, and the method includes following steps. Data is programmed into a flash memory module by using a first programming scheme. A data error parameter of the flash memory module is determined. If the data error parameter is greater than an error predefine value, the data is programmed into the flash memory module by using a second programming scheme. The first programming scheme and the second programming scheme are respectively mapping to a first threshold voltage frame and a second threshold voltage frame, and voltage interval of the second threshold voltage frame is broader than voltage interval of the first threshold voltage frame. | 04-16-2015 |
20150106668 | ERROR BURST DETECTION FOR ASSESSING RELIABILITY OF A COMMUNICATION LINK - Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. In accordance with one aspect, embodiments are disclosed that facilitate assessing the probability of error bursts in receivers that include decision feedback equalizers (DFEs) and that perform non-contiguous mapping of received bits to frame bits. From this probability, calculation of a mean-time to false packet acceptance (MTTFPA) may be determined, and indication that a projected link MTTFPA is too low can be used to trigger an alert or invoke some safety mechanism. Associated operations may then be performed to ensure the link is prevented from being operated in an unsafe condition under which false packet acceptance may occur. | 04-16-2015 |
20150113341 | Efficient Reduction of Read Disturb Errors - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 04-23-2015 |
20150135023 | DATA RETENTION DETECTION TECHNIQUES FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller. A method includes writing an indication of a first error rate of a first set of bits to the non-volatile memory. The first set of bits is sensed from a word line of the non-volatile memory. The word line is sensed to generate a second set of bits in response to a first power-on event being initiated at the data storage device after writing the indication of the first error rate to the non-volatile memory. The method further includes setting a data retention flag in response to a difference between the first error rate and a second error rate associated with the second set of bits satisfying a threshold. | 05-14-2015 |
20150135024 | METHODS AND APPARATUS FOR DETECTING FRAME NUMBER DISCONTINUITIES BETWEEN RADIO NODES - A transmitting node communicates with a receiving node using a multi-layer communications protocol having a lower media access control, MAC, layer and a higher radio link control, RLC, layer. An RLC controller operates in an RLC unacknowledged mode, RLC UM. A MAC controller operates using hybrid automatic repeat request, HARQ, for transmitted MAC protocol data units. The RLC controller in the RLC UM transmits RLC protocol data units via the MAC layer. The MAC controller monitors transmission errors at the MAC layer and informs the RLC controller when detecting a predetermined number of consecutive transmission errors or a predetermined number of transmission errors during a predetermined time period so that the RLC controller can perform one or more actions. | 05-14-2015 |
20150135025 | DRIVING METHOD OF MEMORY CONTROLLER AND NONVOLATILE MEMORY DEVICE CONTROLLED BY MEMORY CONTROLLER - A method is for driving a memory controller which is configured to control a nonvolatile memory device. The method includes counting a number of error bits of read data provided from the nonvolatile memory device, determining a running average value using the number of error bits; and performing a wear leveling on the nonvolatile memory device using the running average value as a wear leveling index. | 05-14-2015 |
20150293808 | SOFT READ HANDLING OF READ NOISE - Aspects of the disclosure pertain to methods and systems that are configured to handle excessive read noise in soft read systems. In an implementation, a method includes determining a number of unexpected patterns of a soft read of a memory cell after a soft decoding failure. The method also includes determining whether the number of unexpected patterns is greater than a threshold number of unexpected patterns. When it is determined that the number of unexpected patterns is greater than the threshold number of unexpected patterns, the method at least one of: performing at least one more soft read of the memory cell with a larger read voltage spacing than an initial read that produced the soft decoding failure; and discarding a result of one or more soft reads of the memory cell and utilizing a remainder of results of respective other soft reads of the memory. | 10-15-2015 |
20150293809 | DATA STORING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data storing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes recording a bit error count of every predetermined area of every physical erasing unit and determining whether the bit error count of one of the predetermined areas of the physical programming unit of the physical erasing unit is more than a threshold bit error count. If the bit error count of one of the predetermined areas of the physical programming unit of the physical erasing unit is more than the threshold bit error count, the method also includes storing data under a second programming mode after an erasing operation is performed on the physical easing unit. Accordingly, defective physical erasing units may be effectively employed to prolong the lifespan of the memory storage apparatus. | 10-15-2015 |
20150293814 | METHOD FOR PROGRAMMING DATA, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - A method for programming data, a memory storage device and a memory control circuit unit are provided. The method includes: receiving a writing command which instructs to write data to a logical address belonging to a logical programming unit; if a physical erasing unit of a physical programming unit which the logical programming unit is mapped to is a first type physical erasing unit, programming the data and a parity code corresponding to the data into the physical programming unit according to a first code rate; and if the physical erasing unit is a second type physical erasing unit, programming the data and the parity code corresponding to the data into the physical programming unit according to a second code rate. The first code rate is higher than the second code rate. Therefore, the lifespan of the physical erasing unit having a higher bit error rate may be extended. | 10-15-2015 |
20150309852 | Data Interpretation With Modulation Error Ratio Analysis - Methods and systems for analyzing data are disclosed. An example method can comprise receiving a first data signal, decoding the first data signal, determining a second data signal based on the decoded first data signal, and determining a modulation error ratio based on a difference between the first data signal and the second data signal. | 10-29-2015 |
20150309853 | SYSTEM AND METHOD TO MEASURE AN ERROR RATE OF A WIRELESS LOCAL AREA NETWORK - Embodiments described herein relate generally to a communication between an element manager and a wireless local area network (WLAN) access point (AP). The WLAN AP may be configured with one or more counters. The one or more counters may measure events, such as data transmission and/or reception at the WLAN AP or a carrier sense multiple access with collision avoidance (CSMA/CA) procedure by the WLAN AP. The element manager may be configured to read one or more of these counters and compute one or more values based on the values read from the one or more counters. The element manager may be configured to communicate the one or more computed values to a network manager. Other embodiments may be described and/or claimed. | 10-29-2015 |
20150331732 | MEMORY DEVICE HAVING STORAGE FOR AN ERROR CODE CORRECTION EVENT COUNT - An integrated circuit memory device is disclosed. The memory device includes at least one group of storage cells. Logic derives a count of error code correction events for each of the at least one group of storage cells. Storage stores the count. A memory control interface selectively communicates the count to a memory controller. | 11-19-2015 |
20150331771 | Simulating Burst Errors in Mobile Data Communication Network System Level Simulations - The disclosed examples provide techniques for simulation of a wireless mobile network that includes block level simulation of burst errors. The simulation allows input of a variable burst error rate to a system level simulation of a communications network. Theoretical error rates are replaced with variable burst error rates in the simulation. Injecting burst errors at the system level provides a network simulation that more realistically reflects the effects of burst errors on network performance. | 11-19-2015 |
20150332735 | DYNAMIC CONTROL OF SIGNALING POWER BASED ON AN ERROR RATE - Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data. | 11-19-2015 |
20150339188 | METHOD FOR READ DISTURBANCE MANAGEMENT IN NON-VOLATILE MEMORY DEVICES - When performing a read operation on a non-volatile memory device which includes a plurality of memory sections each corresponding to a plurality of data units, the read count of a specific memory section and the error bits of its corresponding data units are monitored for determining whether data relocation should be perform. When the read count of the specific section exceeds a read count threshold and the error bits of any corresponding data unit exceeds an error threshold, data is moved from the specific memory section to another memory section of the non-volatile memory device, thereby preventing read disturbance from occurring in the specific memory sections. | 11-26-2015 |
20150347228 | METHOD AND APPARATUS FOR RELOCATING DATA IN NON-VOLATILE MEMORY - Apparatus and methods implemented therein are disclosed for relocating data stored in pages of a non-volatile memory. The number of memory chunks with invalid data in an SLC type first page is determined and if the number is above a first threshold and above a second threshold, a bit error rate (BER) for the valid data in the set of memory chunks of the first page is compared with a first BER threshold. If the BER is below the first BER threshold, an error correcting code (ECC) for valid data in a set of memory chunks of a second page is computed and the invalid data of the first page with valid data is replaced with valid data from the second page and the computed ECC. The valid data of the first and second page is relocated to a third page. | 12-03-2015 |
20150349806 | TECHNIQUE FOR ADAPTIVELY STRENGTHING ECC FOR FLASH CACHE - In an aspect of the subject matter, a “full” amount of the flash cache (e.g., storage cells) is initially utilized to store data i.e., substantially all of the storage space of the flash cache may be designated to store user data, with the remaining storage space designated to store ECC information (e.g., parity bits) associated with a predefined ECC algorithm utilized to encode the user data. When a bit errors associated with the user data reaches a predefined threshold value, the storage space of the flash cache may transition to store less user data so as to accommodate the space needed to store ECC information associated with a stronger ECC algorithm. The storage space of the flash cache designated to store user data is reduced, while the storage space designated to store ECC information is increased to accommodate the stronger ECC algorithm. | 12-03-2015 |
20150363247 | Accurate and Fast In-Service Estimation of Input Bit Error Ratio of Low Density Parity Check Decoders - A device receives signals over a communication medium and uses a low density parity check decoder to decode data in the signals. A number of unsatisfied parity checks are counted prior to a first decoding iteration of the low density parity check decoder on a basis of log likelihood ratios computed from the signals. An operational characteristic of the low density parity check decoder is computed based on an accumulated number of unsatisfied parity checks. | 12-17-2015 |
20150378801 | Systems and Methods for Fast Bit Error Rate Estimation - Changes in the distribution of memory cells across memory states allow calculation of Bit Error Rate (BER). Comparison of test data stored in memory and a known good copy of the test data provides test data BER from which user data BER may be obtained. Data may be handled differently according to its BER. | 12-31-2015 |
20160041891 | Storage Module and Method for Analysis and Disposition of Dynamically Tracked Read Error Events - A method for analyzing a read error event is provided comprising reading a page of data stored in memory, determining a read error event for the page of data, and identifying a scope of the read error event in the memory. In another embodiment, a method for performing a preliminary read error recovery is provided comprising reading a first data unit from memory and identifying a bit error rate for a first data unit with a correction engine, determining that the bit error rate is above a threshold, accessing a data structure including entries identifying data units and read error event information associated with the data units, identifying a second data unit in an entry that matches the first data unit, and performing a preliminary read error recovery process on the first data unit using the information in the entry to reduce the bit error rate below the threshold. | 02-11-2016 |
20160043832 | SECURE COMMUNICATION METHOD AND SYSTEM BASED ON BIT ERROR PROBABILITY - Embodiments of the present invention relates to a secure communication method and system based on a bit error probability. The method according to an exemplary embodiment of the present invention operates in various substantial channels. In addition, data communication security may be achieved using an MDS code that provides an optimal error correction performance when a code length and a transmission rate is given. | 02-11-2016 |
20160077745 | RATE MATCHING TECHNIQUE FOR BALANCING SEGMENT CLEANING AND I/O WORKLOAD - A rate matching technique may be configured to adjust a rate of cleaning of one or more selected segments of the storage array to accommodate a variable rate of incoming workload processed by a storage input/output (I/O) stack executing on one or more nodes of a cluster. An extent store layer of the storage I/O stack may clean a segment in accordance with segment cleaning which, illustratively, may be embodied as a segment cleaning process. The rate matching technique may be implemented as a feedback control mechanism configured to adjust the segment cleaning process based on the incoming workload. Components of the feedback control mechanism may include one or more weight schedulers and various accounting data structures, e.g., counters, configured to track the progress of segment cleaning and free space usage. The counters may also be used to balance the rates of segment cleaning and incoming I/O workload, which may change depending upon an incoming I/O rate. When the incoming I/O rate changes, the rate of segment cleaning may be adjusted accordingly to ensure that rates are substantially balanced. | 03-17-2016 |
20160077903 | Selective Sampling of Data Stored in Nonvolatile Memory - Data stored in a nonvolatile memory is selectively sampled based on write-erase cycle counts of blocks. Blocks with the lowest write-erase cycle counts are sampled to determine an error rate which is compared with a limit. If the error rate exceeds the limit then the sample is expanded to include blocks with the next lowest write-erase cycle counts. | 03-17-2016 |
20160085464 | Storage Module and Method for On-Chip Copy Gather - A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After that, the memory copies the data from the third data latch to a third word line. In another embodiment, a storage module is provided comprising a memory and an on-chip copy gather module. Other embodiments are provided. | 03-24-2016 |
20160085605 | Soft-Error-Rate Calculating Device - For a soft error of an electronic device, a technique capable of ensuring high reliability because of a low soft error rate (SER) is provided. By using building data including information of a structural object of a building and facility data including information of a plurality of facilities including an electronic device arranged in the building, a SER calculating device calculates a model including an attenuation index value representing a degree of attenuation of radiation entering the building attenuated by the structural object of the building until the radiation reaches a position of the facility arranged in the building, calculates a SER at each position of the facility arranged in the building by using the model including the attenuation index value, and outputs information including the SER at each position of the facility. | 03-24-2016 |
20160092284 | ESTIMATING FLASH QUALITY USING SELECTIVE ERROR EMPHASIS - A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types. | 03-31-2016 |
20160110124 | DETECTING ERROR COUNT DEVIATIONS FOR NON-VOLATILE MEMORY BLOCKS FOR ADVANCED NON-VOLATILE MEMORY BLOCK MANAGEMENT - Non-volatile memory block management. A method according to one embodiment includes determining a block health of at least some non-volatile memory blocks of a plurality of non-volatile memory blocks that are configured to store data. An error count margin threshold is calculated for each of the at least some non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the non-volatile memory blocks has been exceeded. | 04-21-2016 |
20160110237 | METHOD TO DETERMINE BER (BIT ERROR RATE) FROM AN EYE DIAGRAM - A system and method for calculating a bit error rate for a mask is described. For each time during the time duration of the mask, the minimum and maximum voltages of the mask at that time are determined. The maximum bit error rate can be calculated for each time by integrating between those voltages. The maximum bit error rate for all times during the time duration of the mask can be selected as the maximum bit error rate for the mask. | 04-21-2016 |
20160118132 | Low Impact Read Disturb Handling - A storage device system receives read commands from a host device and maintains a read disturb count for distinct zones of each of a plurality of non-volatile memory blocks in the storage device. The read disturb count for each zone corresponds to read operations performed in the zone and in predefined memory portions neighboring the zone. In accordance with a determination that the read disturb count for any zone satisfies predefined threshold criteria, the storage device performs a validation operation on one or more memory portions corresponding to that zone. If the validation operation is unsuccessful, the storage device resets the read disturb count for the zone and initiates a refresh operation on at least a portion of the corresponding block. If the validation operation is successful, the storage device resets the read disturb count for the zone that satisfied the predefined threshold criteria, and forgoes initiating the refresh operation. | 04-28-2016 |
20160124784 | SEMICONDUCTOR MEMORY DEVICES INCLUDING ERROR CORRECTION CIRCUITS AND METHODS OF OPERATING THE SEMICONDUCTOR MEMORY DEVICES - A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data. | 05-05-2016 |
20160179595 | MONITORING SERIAL LINK ERRORS | 06-23-2016 |
20160179596 | OPERATING METHOD OF DATA STORAGE DEVICE | 06-23-2016 |
20160179597 | FAILED BIT COUNT MEMORY ANALYTICS | 06-23-2016 |
20160188231 | ADAPTING ERASE CYCLE PARAMETERS TO PROMOTE ENDURANCE OF A MEMORY - In a data storage system including a non-volatile memory array, a controller repeatedly determines at least one health metric of the non-volatile memory array during an operating lifetime of the non-volatile memory array. In response to determining the at least one health metric, the controller selectively varies an erase parameter of the non-volatile memory array over the operating lifetime of the non-volatile memory array, such that endurance of the non-volatile memory array is improved. | 06-30-2016 |
20160203863 | RESISTIVE RANDOM-ACCESS MEMORY AND METHOD FOR CONTROLLING RESISTIVE RANDOM-ACCESS MEMORY | 07-14-2016 |