Class / Patent application number | Description | Number of patent applications / Date published |
714701000 | Data formatting to improve error detection correction capability | 56 |
20080256402 | METHOD AND CIRCUIT FOR REDUCING SATA TRANSMISSION DATA ERRORS BY ADJUSTING THE PERIOD OF SENDING ALIGN PRIMITIVES - A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced. | 10-16-2008 |
20080276138 | Dynamically configurable interleaver scheme using at least one dynamically changeable interleaving parameter - A method for encrypting and decrypting an original data stream comprising: (A) transmitting a copy of a key to an interleaver and to a de-interleaver, wherein the key includes a key-algorithm configured to describe an evolution in time of at least one interleaving parameter; (B) interleaving the original data stream by using the interleaver, wherein the interleaver compensates for a change in latency caused by at least one dynamically changeable interleaving parameter; and (C) recovering the original data stream from the interleaved data stream propagated through the communication channel by using the de-interleaver adapted to communicate with the communication channel, wherein the de-interleaver compensates for a change in latency caused by at least one dynamically changeable interleaving parameter. | 11-06-2008 |
20080288831 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 11-20-2008 |
20080288832 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 11-20-2008 |
20080288833 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 11-20-2008 |
20080294947 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 11-27-2008 |
20080313508 | Method and System for Adaptive Interleaving - A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system. | 12-18-2008 |
20090013223 | MULTI-BIT ERROR CORRECTION SCHEME IN MULTI-LEVEL MEMORY STORAGE SYSTEM - A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent characteristic parameter bands are assigned binary multi-bit values that differ by only one bit. In one embodiment, an error correction unit calculates an actual parity check value of the retrieved binary multi-bit values for the group of memory cells. If the actual parity check value is not equal to the expected parity check value, the error correction unit assigns the error memory cell a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that calculating a second actual parity check value correctly indicates the parity for the group of memory cells. | 01-08-2009 |
20090070641 | Method of using link adaptation and power control for streaming services in wireless networks - A method for improving the performance for a streaming service by link-adaptation and power-control in a wireless packet network such as an Enhanced General Packet Radio Services (EGPRS) cellular network is described. In particular, the effects of a combined link adaptation and power control scheme (referred to as an error-based scheme) for achieving a target error rate, which is non-zero but low enough so that limited retransmission and error concealment techniques are effective, is presented. | 03-12-2009 |
20090077430 | HYBRID AUTOMATIC REPEAT REQUEST APPARATUS AND METHOD FOR ALLOCATING PACKET-BASED FIXED RESOURCES IN A WIRELESS MOBILE COMMUNICATION SYSTEM - An apparatus and method for preventing errors in an HARQ operation and improving HARQ performance are provided. In the apparatus and method, upon receipt of HARQ feedback information, an information interpreter interprets the HARQ feedback information and determines whether the HARQ feedback information includes an error. If the HARQ feedback information includes an error, a scheduler controls a data pattern with the receiver to be generated. | 03-19-2009 |
20090077431 | DEVICES AND METHODS FOR BIT-LEVEL CODING AND DECODING OF TURBO CODES - A bit-level turbo code encoder is provided. The bit-level turbo code encoder is configured to receive a first input data sequence and generate a first output data sequence. The bit-level turbo code encoder includes a first non-binary convolutional code encoder, a bit-level interleaver, and a second non-binary convolutional code encoder. The first non-binary convolutional code encoder is configured to process the first input data sequence and generate a second output data sequence. The bit-level interleaver is configured to receive the first input data sequence as a first sequence and interleave the first sequence at bit level to generate a fourth sequence. The second non-binary convolutional code encoder is coupled with the bit-level interleaver and configured to receive the fourth sequence and process the fourth sequence to generate a third output data sequence. | 03-19-2009 |
20090132872 | Method and Application for Generating Interleaver or De-Interleaver - A method and application for generating an interleaver or a de-interleaver are described. The method for generating interleaver includes: setting interleaving information of a base interleaver and/or de-interleaving information of a base de-interleaver, and respectively performing a cyclic shift transform on the interleaving information of the base interleaver so as to generate a plurality of different interleavers. Alternatively, the method for generating interleaver includes: deducing from the de-interleaving information to obtain the interleaving information of the base interleaver and performing the cyclic shift on the interleaving information obtained by deduction so as to generate a plurality of different interleavers. The method for realizing interleaving includes: inputting a data frame of each subscriber needed to be interleaved to the base interleaver and performing the cyclic shift on the data frame output by the base interleaver so as to realize interleaving, in which different subscribers correspond to different cyclic shifts. Alternatively, the method for realizing interleaving includes: performing the cyclic shift on the data frame of each subscriber to be interleaved and inputting the data frame after the cyclic shift to the base interleaver so as to realize interleaving, in which different subscribers correspond to different cyclic shifts. | 05-21-2009 |
20090158101 | Adapting Word Line Pulse Widths in Memory Systems - Systems, circuits and methods for adapting word line (WL) pulse widths used in memory systems are disclosed. One embodiment of the invention is directed to an apparatus comprising a memory system. The memory system comprises: a memory operating according to a wordline (WL) pulse with an associated WL pulse width; a built-in self-test (BIST) unit that interfaces with the memory, the BIST unit being configured to run a self-test of the internal functionality of the memory and provide a signal indicating if the memory passed or failed the self-test; and an adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit being configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit. | 06-18-2009 |
20090193300 | SYSTEM AND METHOD FOR PSEUDORANDOM PERMUTATION FOR INTERLEAVING IN WIRELESS COMMUNICATIONS - A system and method for pseudorandom permutation for interleaving in wireless communication is disclosed. In one embodiment, the method comprises receiving a first ordered sequence of communication symbols having a first order, permuting the first ordered sequence of communication symbols to generate a second ordered sequence of communication symbols having a second order, and outputting the second ordered sequence of communication symbols, wherein the second order is based, at least in part, on a third order having a greater size than the second order, the third order being a pseudorandom permutation defined by the input-output relationship | 07-30-2009 |
20090199055 | Interleaver Design with Unequal Error Protection for Control Information - For transmission of a block of control information within a wireless network, the control information is interleaved to form an ordered set of control bits, wherein more important information bits of the control information are placed into a first portion of the ordered set of control bits, with less important information bits of the control information placed into a second portion of the ordered set of controls bits. The ordered set of control bits is encoded to form an encoded block of data. The encoded block of data is transmitted to a serving base station, wherein bits from the first portion of the ordered set of control bits will statistically have a lower bit error rate (BER) than bits from the second portion of the ordered set of control bits during transmission. | 08-06-2009 |
20090204859 | Systems, methods and computer program products including features for coding and/or recovering data - Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data streams from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data streams via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams. Further exemplary implementations may comprise a transformation process that includes producing an H-sized intermediary for each of the W inputs, combining the H-sized intermediaries into an H-sized result, and processing the H-sized result into the H output data streams. | 08-13-2009 |
20090249133 | SYSTEMS AND METHODS FOR PROTECTING DSL SYSTEMS AGAINST IMPULSE NOISE - Systems and methods for protecting DSL systems against impulse noise are provided. Disclosed herein are example embodiments of a retransmission technique located above the gamma interface (i.e., in the network processing layer). Such a retransmission technique can be combined with standard RS coding with standard erasure-decoding & triangular interleaving at the PMS-TC layer. Example embodiments of the technique involve using the RS code to protect against REIN noise, and using γ-layer retransmission for protecting against error events not corrected by the RS code, e.g. a SHINE noise in the presence of REIN. Both techniques are used jointly in the case of combined REIN and SHINE noise. | 10-01-2009 |
20090254783 | Information Signal Encoding - A very coarse quantization exceeding the measure determined by the masking threshold without or only very little quality losses is enabled by quantizing not immediately the prefiltered signal, but a prediction error obtained by forward-adaptive prediction of the prefiltered signal. Due to the forward adaptivity, the quantizing error has no negative effect on the prediction on the decoder side. | 10-08-2009 |
20090282298 | BIT ERROR MANAGEMENT METHODS FOR WIRELESS AUDIO COMMUNICATION CHANNELS - Systems and methods are described for managing bit errors present in an encoded bit stream representative of a portion of an audio signal, wherein the encoded bit stream is received via a channel in a wireless communications system. The channel may comprise, for example, a Synchronous Connection-Oriented (SCO) channel or an Extended SCO (eSCO) channel in a Bluetooth wireless communications system. | 11-12-2009 |
20090307540 | SYSTEM AND METHOD FOR APPLYING MULTI-TONE OFDM BASED COMMUNICATIONS WITHIN A PRESCRIBED FREQUENCY RANGE - According to one embodiment of the invention, an integrated circuit comprises an encoding module, a modulation module and a spectral shaped module. The encoding module includes an interleaver that adapted to operate in a plurality of modes including a first mode and a second mode. The interleaver performs repetitive encoding when placed in the second mode. The modulation module is adapted to compensate for attenuations that are to be realized during propagation of a transmitted signal over the power line. The spectral shaped module is adapted to compensate for amplitude distortion and further compensates for attenuations that will be realized during propagation of the transmitted signal over the power line. | 12-10-2009 |
20090307541 | BLOCK INTERLEAVING SCHEME WITH CONFIGURABLE SIZE TO ACHIEVE TIME AND FREQUENCY DIVERSITY - An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet. | 12-10-2009 |
20100037106 | VSB TRANSMISSION SYSTEM FOR PROCESSING SUPPLEMENTAL TRANSMISSION DATA - A VSB communication system or transmitter for processing supplemental data packets with MPEG-II data packets includes a VSB supplemental data processor and a VSB transmission system. The VSB supplemental data processor includes a Reed-Solomon coder for coding the supplemental data to be transmitted, a null sequence inserter for inserting a null sequence to an interleaved supplemental data for generating a predefined sequence, a header inserter for inserting an MPEG header to the supplemental data having the null sequence inserted therein, a multiplexer for multiplexing an MPEG data coded with the supplemental data having the MPEG header added thereto in a preset multiplexing ratio and units. The output of the multiplexer is provided to an 8T-VSB transmission system for modulating a data field from the multiplexer and transmitting the modulated data field to a VSB reception system. | 02-11-2010 |
20100050027 | NETWORK COMMUNICATION PROTOCOL FOR LARGE SCALE DISTRIBUTION OF STREAMING CONTENT - Forward error correction may be implemented in a network having first, second, third and fourth nodes. The second node receives streaming media message packets and one or more check packets from an upstream first node. The second node transmits the message packets and check packets to a downstream third node. The second node transmits a second set of one or more check packets to a fourth node that is downstream of the third node. | 02-25-2010 |
20100077264 | SERIALIZATION ALGORITHM FOR FUNCTIONAL ESD ROBUSTNESS - An apparatus and method are described for sending serialized command in an environment where ESD or other phenomenon might cause malfunctions. Commands are encoded where there are at least two bit changes between any two commands. In this example, each command code that is different from legal commands by only one bit is an illegal command, Illustratively, if six bits provide 64 codes for commands, and only eight codes are used for legal commands, there will be 56 illegal command codes. Illustratively, any command code, that is only one bit different from a legal command, will be an illegal command. In practice a illegal command may be detected, and the system may recover. An illegal command due to and ESD event may be defined, and when detected a recovery process may be entered. When data (not command) are being sent, error detecting and correcting bits may be employed. | 03-25-2010 |
20100077265 | Turbo interleaver for high data rates - Techniques for supporting high decoding throughput are described. A transmitter may encode a code block of data bits with a Turbo encoder. A receiver may perform decoding for the code block with a Turbo decoder having multiple soft-input soft-output (SISO) decoders. A contention-free Turbo interleaver may be used if the code block size is larger than a threshold size. A regular Turbo interleaver may be used if the code block size is equal to or smaller than the threshold size. The contention-free Turbo interleaver reorders the data bits in the code block such that information from the multiple SISO decoders, after interleaving or deinterleaving, can be written in parallel to multiple storage units in each write cycle without encountering memory access contention. The regular Turbo interleaver can reorder the data bits in the code block in any manner without regard to contention-free memory access. | 03-25-2010 |
20100115350 | DETERMINISTIC WAVELET THRESHOLDING FOR GENERAL-ERROR METRICS - Novel, computationally efficient schemes for deterministic wavelet thresholding with the objective of optimizing maximum-error metrics are provided. An optimal low polynomial-time algorithm for one-dimensional wavelet thresholding based on a new dynamic-programming (DP) formulation is provided that can be employed to minimize the maximum relative or absolute error in the data reconstruction. Directly extending a one-dimensional DP algorithm to multi-dimensional wavelets results in a super-exponential increase in time complexity with the data dimensionality. Thus, novel, polynomial-time approximation schemes (with tunable approximation guarantees for the target maximum-error metric) for deterministic wavelet thresholding in multiple dimensions are also provided. | 05-06-2010 |
20100122126 | VSB COMMUNICATION SYSTEM - A VSB communication system comprises a VSB transmission system and a VSB reception system. The VSB transmission system multiplexes a coded MPEG data and a coded supplemental data having a null sequence inserted therein, with required multiplexing information included in a field synchronization signal or in a supplemental data according to a number of the supplemental data packets being transmitted. The VSB reception system detects the required multiplexing information from the field synchronization signal or the supplemental data and decodes the multiplexed data by using the null sequence and the detected multiplexing information, as well as demultiplexes the multiplexed data into the MPEG data and the supplemental data. | 05-13-2010 |
20100169722 | Channel interleaver having a constellation-based unit-wise permuation module - A channel interleaver comprises a novel constellation-based permutation module. The channel interleaver first receives a plurality of sets of encoded bits generated from an FEC encoder. The encoded bits are distributed into multiple subblocks and each subblock comprises a plurality of adjacent bits. A subblock interleaver interleaves each subblock and outputs a plurality of interleaved bits. The constellation-based permutation module rearranges the interleaved bits and outputs a plurality of rearranged bits. The rearranged bits are supplied to a symbol mapper such that a plurality of consecutively encoded bits in the same set of the encoded bits generated from the FEC encoder is prevented to be mapped onto the same level of bit reliability of a modulation symbol. In addition, the plurality of adjacent bits of each subblock is also prevented to be mapped onto the same level of bit reliability to achieve constellation diversity and to improve decoding performance. | 07-01-2010 |
20100180165 | SYSTEM AND METHOD OF UNCORRELATED CODE HOPPING IN A COMMUNICATIONS SYSTEM - A system and method are used to provide uncorrelated code hopping in a communications system. A shift register receives data. The shift register is clocked to shift the data. A scaler performs a scaling operation on the data with a numerical value of active codes. A truncator truncates the scaled data to its seven most significant bits to produce a pseudo random hop number. A code matrix shifter circularly shifts the active codes in a code matrix based on the pseudo random hop number to produce a circularly shifted code. A transmitter transmits the circularly shifted code. | 07-15-2010 |
20100235689 | APPARATUS AND METHOD FOR EMPLOYING CODES FOR TELECOMMUNICATIONS - A transmitting apparatus generates a first bit stream from a second bit stream by encoding at least a portion of the bits from the second bit stream, generates a code for the second bit stream, and attaches the code to the first bit stream for transmission to a receiving apparatus. A receiving apparatus receive from a transmitting apparatus a first bit stream with a code, generates a second bit stream from the first bit stream by decoding at least a portion of the bits from the first bit stream, computes the code for the second bit stream, and compares the computed code with the code from the first bit stream. | 09-16-2010 |
20110004792 | BIT ERROR RATE REDUCTION IN CHAOTIC COMMUNICATIONS - A system for chaotic sequence spread spectrum communications includes a transmitter ( | 01-06-2011 |
20110029825 | APPARATUS AND METHOD FOR SYMBOL ERROR CORRECTABLE MODULATION AND DEMODULATION USING FREQUENCY SELECTIVE BASEBAND - Provided are symbol-error-correctable modulation and demodulation methods and apparatuses using a frequency selective baseband. The symbol-error-correctable frequency modulation method using a frequency selective baseband, includes: generating a plurality of subgroups by dividing 2N (N is a real number) spread codes or orthogonal codes used for frequency spreading into 2M (M02-03-2011 | |
20110047419 | Secure Method for Reconstructing a Reference Measurement of a Confidential Datum on the Basis of a Noisy Measurement of this Datum, Notably for the Generation of Cryptographic Keys - The present invention relates to a secure method for reconstructing a reference measurement of a confidential datum on the basis of a noisy measurement of this datum. The method proposes a phase of enrolling a reference datum w having n digits, comprising at least the following steps:
| 02-24-2011 |
20110113293 | DATA RECEPTION DEVICE, DATA RECEPTION METHOD, AND PROGRAM - A data reception device that receives scrambled and transmission data as received data and that descrambles and outputs the data after adjusting the timing with the transmitter has a descramble circuit | 05-12-2011 |
20110271154 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 11-03-2011 |
20110289367 | METHOD AND DEVICE FOR FLEXIBLE ERROR CORRECTION ENCODING AND CORRESPONDING COMPUTER PROGRAM - An error correction encoding device is provided that combines redundancy data with source data, said device including: at least three encoding stages and at least two permutation stages. Each encoding stage implements at least one set of three basic encoding modules, in which a first encoding stage receives said source data and a last encoding stage provides said redundancy data. Each encoding module implements a basic code and includes c inputs and c outputs, c being an integer. The permutation stages are inserted between two consecutive encoding stages and each permutation stage implements a c-cyclic permutation. | 11-24-2011 |
20130103991 | Method of Protecting a Configurable Memory Against Permanent and Transient Errors and Related Device - A method for protecting digital memory against permanent and transient errors and a related device, the digital data being stored in at least one storage matrix of memory cells in a given number of rows and columns, comprises: an encoding step generating code words from data organized in binary words by application of asymmetric code introducing at least two different levels of protection, the first level of protection said to be high being associated with a first sub-group of bits of the code word and a second level of protection said to be low being associated with a second sub-group of the same word; swapping positions of the bits of the code word making the bits with a high level of protection correspond for their storage to the columns of the storage area comprising defective memory cells and the bits with a low level of protection to the remaining columns. | 04-25-2013 |
20130151910 | SYMBOL ENCODING FOR TOLERANCE TO SINGLE BYTE ERRORS - The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol. | 06-13-2013 |
20140006884 | DATA CONVERTING METHOD, DATA CONVERTING APPARATUS, AND COMPUTER PRODUCT | 01-02-2014 |
20140281761 | Reversible corruption of a digital medium stream by multi-valued modification in accordance with an automatically generated mask - Methods and apparatus create a corruption mask from a sequence that is generated by an n-state sequence generator with n>2. A digital media stream containing n-state symbols is corrupted in accordance with the corruption mask. The corruption takes place by applying a one argument or a two argument n-state logic function. The corruption rate of the digital media stream is preferably less than 100% allowing it to be reviewed. Data related to the corruption mask and the corruption mask are transmitted to a processor based receiver, allowing the receiver to decorrupt the corrupted digital media stream and to display it in its uncorrupted state. | 09-18-2014 |
20150019921 | METHOD OF ENCODING DATA - Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four. | 01-15-2015 |
20150082103 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR TEST CONFIGURATION OPTIMIZED DECODING OF PROTOCOL MESSAGES IN A NETWORK DEVICE TEST SYSTEM - Methods, systems, and computer readable media for test configuration optimized decoding of protocol messages in a network device test system are provided. One exemplary network equipment device test system includes a message blueprint data structure for storing blueprint data for messages to be decoded. The network equipment test device further includes a message decoder for decoding received messages by accessing the message blueprint data structure and matching information elements in the received messages with information elements in the message blueprint data structure. The network equipment test device further includes a message blueprint data structure configurator for receiving, as input, test configuration data, and for configuring the message blueprint data structure for optimized decoding of messages based on the test configuration data. | 03-19-2015 |
20150149838 | REARRANGING PROGRAMMING DATA TO AVOID HARD ERRORS - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 05-28-2015 |
714702000 | Memory access (e.g., address permutation) | 13 |
20080222460 | Memory test circuit - A memory test circuit is provided, comprising: an output data selector configured to receive the plurality of read data bits and output a fraction of the plurality of read data bits as a plurality of fractional data bits; and a control circuit configured to select a set of bit positions in the plurality of read data bits whose corresponding values will form the plurality of fractional data bits, wherein the selected set of bit positions is selectable from a plurality of possible sets of bit positions, each actual bit position in the plurality of read data bits being contained in at least one of the possible sets of bit positions, and wherein a fractional length of the plurality of fractional data bits is smaller than a full length of the plurality of read data bits. | 09-11-2008 |
20080244338 | Soft bit data transmission for error correction control in non-volatile memory - Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data. | 10-02-2008 |
20090019325 | MEMORY DEVICE, SUPPORTING METHOD FOR ERROR CORRECTION THEREOF, SUPPORTING PROGRAM THEREOF, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A memory device (memory module) having one or a plurality of memory chips is disclosed. By including in a memory chip an error generation part to generate an error, an error is generated in a specific area of a memory in accordance with an address specification, thereby confirmation of an ECC function is facilitated. The error generation part includes an error code generation part that generates an error code. The memory chip is configured by one or a plurality of memory matrixes. | 01-15-2009 |
20090100300 | METHOD AND APPARATUS FOR INTERLEAVING DATA IN A MOBILE COMMUNICATION SYSTEM - An interleaving method to which time-first-mapping is applied for a plurality of channel-coded and rate-matched code blocks considering a modulation scheme in a mobile communication system is provided. The interleaving method includes determining sizes of a horizontal area and a vertical area of an interleaver memory, selecting a defined number of adjacent coded symbols in a same code block according to a modulation scheme, generating modulation groups in a vertical direction, sequentially writing the modulation groups in the horizontal area on a row-by-row basis, and sequentially reading the symbols written in the interleaver memory on a column-by-column basis. | 04-16-2009 |
20090144590 | INTERLEAVING REDUNDANCY APPARATUS AND METHOD - One embodiment of the invention relates to a network communication device. The network communication device includes a network interface configured to receive an initial data stream. The network communication device also includes an interleaving redundancy encoder that comprises a memory unit arranged in N columns and D rows. The interleaving redundancy encoder is configured to calculate at least one redundancy byte based on a series of equally spaced, non-consecutive bytes in the initial data stream, where a number of bytes between equally spaced bytes is approximately equal to D−1. Other systems and methods are also disclosed. | 06-04-2009 |
20090249134 | DE-INTERLEAVING MECHANISM INVOLVING A MULTI-BANKED LLR BUFFER - A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner. | 10-01-2009 |
20100241911 | ADDRESS GENERATOR OF COMMUNICATION DATA INTERLEAVER AND COMMUNICATION DATA DECODING CIRCUIT - An address generator of a communication data interleaver and a communication data decoding circuit are provided. The address generator includes a first operation unit and a second operation unit. The first operation unit receives a first parameter and a first operation result. The first operation unit performs a recursive operation according to the first parameter and the first operation result and outputs the first operation result. The second operation unit receives the first operation result, a second operation result, and a second parameter. According to a transmission mode signal, whether the second operation unit generates a second operation result is determined by performing a recursive operation according to the first operation result, the second parameter, and the second operation result, or by calculating the first operation result and the second parameter. | 09-23-2010 |
20100313083 | CHANNEL CONSTRAINED CODE AWARE INTERLEAVER - An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements. | 12-09-2010 |
20100332921 | Fast data eye retraining for a memory - A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge. | 12-30-2010 |
20110022903 | DEVICE ENABLING THE USE OF A PROGRAMMABLE COMPONENT IN A NATURAL RADIATIVE ENVIRONMENT - A device for using a programmable component carrying out at least one logical function in a radiative environment includes: a mechanism for error detection in a data-storing working memory space actually serving to carry out each logical function of the device through use of data stored in at least one reference memory space storing a data copy implemented by at least one logical function; a mechanism blocking at least one output of at least one logical function of the component for which an error in the data implemented by the logical function is detected by the mechanism for detection; and a mechanism correcting each error detected in the working space. | 01-27-2011 |
20110083049 | METHOD AND APPARATUS FOR DISPERSED STORAGE OF STREAMING DATA - A method begins by a processing module receiving streaming data and dispersed storage resource configuration information. The method continues with the processing module allocating a plurality of sets of dispersed storage resources, obtaining error coding dispersed storage function parameters, and partitioning the streaming data into a plurality of data streams in accordance with the dispersed storage resource configuration information when the dispersed storage resource configuration information requires a plurality of sets of dispersed storage resources. In addition, the method continues with the processing module converting, via the plurality of sets of dispersed storage resources, the plurality of data streams into pluralities of sets of error coded data slices in accordance with the error coding dispersed storage function parameters. | 04-07-2011 |
20120144252 | STORAGE CONTROL APPARATUS AND STORAGE CONTROL METHOD - A first memory area and a second memory area are provided. The first (second) memory area is provided with at least one first (second) memory module group, each of the first (second) memory module group is provided with at least one first (second) memory module, and each of the first (second) memory module is provided with a plurality of memory chip. In the case in which an error chip that is a memory chip that is provided with an error is in the first memory module, a first memory module group that is provided with the error chip is not managed as a memory module group that cannot be used even if there is a possibility that an error of the first data element is mis-corrected based on the error detecting code of the first kind. In the case in which an error chip is in the second memory module, a second memory module group that is provided with the error chip is not managed as a memory module group that cannot be used in such a manner that an error of the second data element is not mis-corrected based on the error detecting code of the second kind. | 06-07-2012 |
20130111279 | SYSTEMS AND METHODS OF GENERATING A REPLACEMENT DEFAULT READ THRESHOLD | 05-02-2013 |