| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714795000 | Viterbi decoding | 53 |
| 20080250303 | Viterbi Decoder and Method Thereof - The present invention relates to a decoder for tail-biting convolution codes and a method thereof. The decoder receives an encoding bit sequence in a convolutional encoding method from a channel, generates an expanded encoding bit sequence, Viterbi decodes the expanded encoding bit sequence, and generates decoded data. In addition, the decoder selects a central bit sequence of the decoded data, rearranges the central bit sequence, and generates final decoded data. Accordingly, the decoder has a simplified configuration for decoding the bit sequence encoded in the tail biting convolutional encoding method, and the decoder also decodes a bit sequence encoded in a zero-tail convolutional encoding method. | 10-09-2008 |
| 20080270874 | E2PR4 viterbi detector and method for adding a branch metric to the path metric of the surviving path after selecting the surviving path | 10-30-2008 |
| 20090049367 | VITERBI Traceback Initial State Index Initialization for Partial Cascade Processing - This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode. | 02-19-2009 |
| 20090070658 | DEFECT SENSING VITERBI BASED DETECTOR - During decoding using a Viterbi based detector, erasures are detected when surviving paths do not merge in an associated decoding window. | 03-12-2009 |
| 20090077451 | METHOD AND APPARATUS FOR IMPLEMENTING DECODE OPERATIONS IN A DATA PROCESSOR - An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed. | 03-19-2009 |
| 20090089648 | LOW POWER VITERBI DECODER USING SCARCE STATE TRANSITION AND PATH PRUNING - Low power Viterbi decoder techniques using Scarce State Transition (SST) and path pruning and related methods and systems are provided, which facilitate practical implementations that reduce the computational overhead and power consumption. In addition, the invention provides uneven-partitioned memory architectures for the survivor memory unit that advantageously exploits the characteristic of the maximum likelihood state probability distribution of the SST decoder facilitating further power reduction. The disclosed details enable various refinements and modifications according to decoder and system design considerations. | 04-02-2009 |
| 20090089649 | Programmable compute unit with internal register and bit FIFO for executing Viterbi code - A programmable compute unit with an internal register with a bit FIFO for executing Viterbi code is configured to accumulate in the forward path the best-path to each state in an internal register and store the survivor trace back information bit for each state in each stage in a bit FIFO; and in the trace back, selecting the optimal best-path through the Viterbi trellis by tracing through the bit trace back information survivor bits beginning with the survivor bit of the last stage path; and generating in response to the Viterbi constrain length and a current bit FIFO address, the next bit FIFO address and decoded output bit for the next previous stage. | 04-02-2009 |
| 20090125794 | ACS UNIT OF A VITERBI DECODER AND METHOD FOR CALCULATING A BIT ERROR RATE BEFORE A VITERBI DECODER - An ACS unit of a Viterbi decoder and a method for calculating the bit error rate (BER) before Viterbi decoder are provided. The ACS unit includes a state calculator and a BER calculator. The state calculator calculates the state metric of a corresponding target state in the trellis diagram and selects one of two candidate source states as the selected source state of the target state. The state calculator also provides a selection signal indicating the selected source state. The BER calculator is coupled to the state calculator for providing the sum of the BER of the selected source state and the bit error count (BEC) of the transition from the selected source state to the target state as the BER of the target state. | 05-14-2009 |
| 20090158131 | VITERBI DECODING APPARATUS AND METHOD - A Viterbi decoding apparatus receives a plurality of block data in time order, and transmits a block data group including the plurality of block data. Then, the Viterbi decoding apparatus applies a Viterbi decoding algorithm to the block data group and outputs some block data of the block data group. In this way, it is possible to provide a Viterbi decoding apparatus that can operate at a high speed and improve a data transmission rate. | 06-18-2009 |
| 20090172504 | MEMORY ARCHITECTURE FOR VITERBI DECODER AND OPERATING METHOD THEREFOR - The Viterbi decoder is an essential module in a communication system, in which the power and the decoding latency are restricted. In the present invention, a power efficient low latency survivor memory architecture and an operating method for the Viterbi decoder are disclosed by providing a plurality of trace-forward units, a plurality of first signal selecting units, a plurality of second signal selecting units and a third signal selecting unit to reduce the power consumption by decreasing the exchange times of contents in the trace-forward units. Thus, the present invention is suitable for use in mobile communication devices which require low power consumption. | 07-02-2009 |
| 20090187813 | Methods and Apparatus for Reduced Complexity Soft-Output Viterbi Detection - Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits. A sequence detector is provided that comprises a branch metrics unit for determining branch metrics having a first precision; a programmable precision conversion unit for converting the branch metrics having the first precision to branch metrics having a desired precision; and an add-compare select unit for computing path metrics based on the desired precision branch metrics. The Soft-Output Viterbi processor optionally processes a trellis having a reduced number of states relative to a trellis processed by the sequence detector. | 07-23-2009 |
| 20090193321 | VITERBI DECODER AND VITERBI DECODING METHOD - A Viterbi decoder and a Viterbi decoding method are provided for simplifying hardware and increasing an operation speed by using a decision feedback unit selecting one of at least two levels based on at least one survivor symbol fed back from a path memory unit. The Viterbi decoder includes a path memory unit (PMU) storing a survivor path, a decision feedback unit (DFU) selecting one of at least two levels based on at least one survivor symbol fed back from the PMU, a branch metric calculation unit (BMCU) calculating a branch metric by using the level selected by the DFU and the received symbol, and an add-compare-selection unit (ACSU) deciding the survivor path by using the branch metric calculated by the BMCU and a previously stored state metric and transmitting the decided survivor path to the PMU. | 07-30-2009 |
| 20100005372 | METHOD AND APPARATUS FOR IMPROVING TRELLIS DECODING - A digital signal processor for decoding Trellis based channel encoding stages based on radix-4 stages comprising means for rearranging the input and output data in Radix-4 Viterbi decoding to make inter-stage Trellis data movement suitable for use in the digital signal processor. | 01-07-2010 |
| 20100058152 | DECODING APPARATUS AND METHOD - A-decoding-apparatus includes first-equalization-unit configured to obtain an-equalized-bit-string subjected to hard-decision by equalizing the-input-signal, and to obtain reliability-value-data as soft-decision which is indicating reliability of the-hard-decision with respect to each bit of the-equalized-bit-string, second-equalization-unit configured to obtain a plurality of candidates of the-equalized-bit-string subjected to hard-decision by equalizing the-first-signal, conversion-unit configured to covert the-reliability-value-data corresponding to the-candidates of the-equalized-bit-string, decoding-unit configured to obtain a-bit-string by performing error-correction decoding by using the-converted-reliability-value-date as soft-decision on the-reliability-value-data, determination-unit configured to determine whether the-bit-string obtained by the-decoding-unit contains an-error, and control-unit configured to control the-conversion-unit and the-decoding-unit based on determination-result obtained by the-determination-unit to repeatedly execute processing of causing the-conversion-unit to convert the-reliability-value-data corresponding to the-candidate of the-equalized-bit-string and causing the-decoding-unit to decode the-reliability-value-data converted by the-conversion-unit, until a-bit-string without error is obtained. | 03-04-2010 |
| 20100064201 | APPARATUS AND METHOD OF GENERATING REFERENCE LEVEL OF VITERBI DECODER - An apparatus of generating the optimum reference level of a Viterbi decoder for an input signal includes: a first reference level detection unit detecting a first reference level using a delayed input signal from the Viterbi decoder and an output signal of the Viterbi decoder; a second reference level detection unit detecting a second reference level using input signals input after and before one clock cycle with respect to the delayed input signal and the output signal; and a control unit controlling one of the first reference level and the second reference level to be the reference level of the Viterbi decoder by using a result of comparison between a first square level error for the first reference level calculated in the first reference level detection unit and a second square level error for the second reference level calculated in the second reference level detection unit. | 03-11-2010 |
| 20100070834 | Soft output viterbi detector with error event output - Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associated with the decision, and defining a possible error event based at least in part on the second sequence of states. | 03-18-2010 |
| 20100070835 | Method and Apparatus for Error Compensation - Various approaches to recover data are described. An one example, an encoded data stream is processed in a first channel decoder producing a channel decoder output. The channel decoder output and the encoded data stream are processed in an error compensation unit to compensate the channel decoder output for low frequency noise and produce an error compensated data stream. The error compensated data stream is processed in a second channel decoder to produce a recovered data stream, wherein the recovered data stream has a reduction in the number of errors as compared to the encoded data stream. Systems to iteratively recover data from an encoded data stream are also described. | 03-18-2010 |
| 20100169749 | METHOD AND APPARATUS FOR CONCATENATED CONVOLUTIONAL ENCODING AND INTERLEAVING - A method and apparatus encode a source data stream via convolutional encoding or selected encoding scheme. Plural encoded data streams are interleaved and transmitted on a transmission channel. Data groups generated via convolutional or selected encoding are interleaved via time-interleaving functions to disperse selected bits within puncture groups of the data groups, bits in between data groups, and bits in selected sets of data groups to facilitate reconstruction of the source data stream from at least a portion of the interleaved data stream received on at least one transmission channel. The time-interleaving functions are selected to facilitate reconstruction of the source data stream from one transmission channel following continuous blockage. Subsets of bits of puncture groups are selected to allow reconstruction of the source data stream from more than one of plural transmission channels using a minimum number of subsets. Multiple combinations of subsets can be received on both transmission channels to reconstruct the source data stream following blockage of one channel. Decoding is performed via a Viterbi decoder. | 07-01-2010 |
| 20100223537 | Method and System for Decoding Video, Voice, and Speech Data Using Redundancy - A method and system for decoding video, voice, and/or speech data using redundancy and physical constraints are presented. Video, voice, and/or speech bit sequences may be decoded in a multilayer process based on a decoding algorithm and at least one physical constraint. For voice applications, the decoding algorithm may be based on the Viterbi algorithm. At least one estimated bit sequence may be selected by performing searches that start from trellis junctions determined during by the decoding algorithm. The estimated bit sequences may be selected based on corresponding redundancy verification parameters. At least one physical constraint test may be performed on the selected estimated bit sequences to select a decoded output bit sequence. | 09-02-2010 |
| 20100229076 | Decoding Apparatus and Decoding Method - Disclosed herein is a decoding apparatus including: with N and x each being a positive integer and k being a positive integer being equal to or greater than 1, a shift register of k stages configured to accumulate path select information for k inputs that is information about a survivor path of xN bits made up of radix-2 | 09-09-2010 |
| 20100299583 | OPTIMIZED VITERBI DECODER AND GNSS RECEIVER - A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design constraints specific to the SV navigation and analysis of the Viterbi algorithm an optimised architecture can be realised for embedding Viterbi acceleration logic efficiently into a GNSS chipset. | 11-25-2010 |
| 20100325525 | SOFT OUTPUT VITERBI DECODER ARCHITECTURE - A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states. | 12-23-2010 |
| 20110060972 | DECODING METHOD FOR TAIL-BITING CONVOLUTIONAL CODES USING A SEARCH DEPTH VITERBI ALGORITHM - A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output. | 03-10-2011 |
| 20110083063 | Continuous Parallel Viterbi Decoder - A continuous parallel Viterbi decoder comprises input means for computing Trellis paths from an input bitstream encoded with a convolutional code; output means for backtracking the Trellis paths to generate an output signal; a shared memory for storing said Trellis paths; and coordination means for coordinating simultaneous read/write operations from and to the shared memory. (FIG. | 04-07-2011 |
| 20110138260 | LDPC coding process with incremental redundancy - The invention relates to a coding method with incremental redundancy in which it is determined ( | 06-09-2011 |
| 20110161787 | POWER-REDUCED PRELIMINARY DECODED BITS IN VITERBI DECODERS - Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”. | 06-30-2011 |
| 20110167323 | Error-Correcting Apparatus and Method Thereof - The invention discloses an error-correcting apparatus for decoding an input signal by using a Viterbi algorithm to generate a Viterbi-decoded signal, including an erasure unit and a decoder. The erasure unit is configured to generate at least one logic signal according to at least one path metric difference of path metrics in the Viterbi algorithm, and generate erasure information, wherein the erasure information indicates data reliability of at least one location of the Viterbi-decoded signal. The decoder is configured to decode the Viterbi-decoded signal according to the erasure information. | 07-07-2011 |
| 20110231741 | SYSTEM AND METHOD FOR VITERBI DECODING USING APPLICATION SPECIFIC EXTENSIONS - A system and method for Viterbi decoding utilizes a general purpose processor with application specific extensions to perform Viterbi decoding operations specified in a Viterbi decoding algorithm stored in memory. | 09-22-2011 |
| 20110264988 | CONVOLUTIONAL CODE FOR USE IN A COMMUNICATION SYSTEM - In a communication system, a transmitter receives an input bit, and in response thereto, generates at least an n-bit codeword, each bit of which is generated by a respective one of n generators of which m are exactly the same, m being greater than n/2. A receiver comprises: m detectors, each adapted to receive the bit generated by a respective one of the m generators, and provide a respective one of m partial detection signals if a strength of the received bit exceeds a predetermined minimum threshold; and a majority logic element adapted to receive each of the m partial detection signals, and provide an output bit indicative of the input bit only if more than m/2 of the received m partial detection signals exceeds the minimum threshold. | 10-27-2011 |
| 20110283170 | Viterbi Decoder and Writing and Reading Method - A Viterbi decoder includes a survival memory unit, for storing a plurality of survivor metric into a writing column of a writing bank of a plurality of banks in alternating intervals of a clock according to a writing bank order and a writing column order, and a trace back unit, for reading a reading column of each bank not performing storing operations according to a reading bank order and a reading column order in every interval of the clock. | 11-17-2011 |
| 20110307767 | METHOD AND APPARATUS FOR SIGNAL-TO-NOISE RATIO ESTIMATION IN CONVOLUTIONAL CODES (VITERBI) DECODER - A method of estimating signal-to-noise ratio in a Viterbi decoder comprising: setting a threshold SNR value; determining a dependence on SNR of the average decoding path length; filling branch metrics matrix, minimal path metrics matrix, path metrics matrix and paths matrix with initial values; receiving packets from a communication channel; calculating the matrices that contains paths stored during operation of Viterbi algorithm in its rows, and a minimal path metrics matrix, including calculating an estimate of a decoding path length, where all the paths converge, based on the paths matrix; calculating current SNR estimate using an estimate of a decoding path length, based on results of previous steps; setting a decoder control signal to an active state if the current estimated SNR does not exceed the threshold, and to an inactive state otherwise; if the decoder control signal is in active state, the branch metrics matrix, the minimal path metrics matrix, the paths metrics matrix and the paths matrix are filled with the initial values; generating a decoded symbol; and repeating the steps on a next packet if one is available. | 12-15-2011 |
| 20120036416 | LIST VITERBI DECODING OF TAIL BITING CONVOLUTIONAL CODES - A low complexity List Viterbi algorithm (LVA) for decoding tail biting convolutional codes (TBCCs) has lower complexity than a solution of running the LVA algorithm for all states. In one aspect, a low complexity LVA-TBCC process includes finding a list of states from a single Viterbi algorithm and finding a list of potential codewords for each state in the state list using the LVA. A cyclic redundancy check may prune out false solutions. The disclosed method may be applied to many communication systems to improve error performance similar to LTE downlink PBCH decoding enhancements. | 02-09-2012 |
| 20120042229 | MULTI-STANDARD VITERBI PROCESSOR - Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently. | 02-16-2012 |
| 20120137198 | LOW COMPLEXITY DECODING ALGORITHM FOR TAIL-BITING CONVOLUTIONAL CODES - A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output. | 05-31-2012 |
| 20120192042 | Soft Decoding of CRC Component Codes - Methods and devices are disclosed for encoding and decoding convolutional codes in a communication system. In various embodiments of the disclosure, a codeword comprises message data and parity data. A convolutional codeword is generated by multiplying the message data and the parity data with a convolutional polynomial. The convolutional codeword may be decoded by a convolutional code decoder that uses the convolutional polynomial and a maximum likelihood divisor to obtain a maximum likelihood message from the convolutional codeword. | 07-26-2012 |
| 20120324317 | DATA CLASSIFICATION IN A WIRELESS COMMUNICATION SYSTEM - A method of data classification for use in a wireless communication system includes obtaining decoder metrics from a decoder. The decoder metrics correspond to data generated by the decoder. The decoder metrics include a first metric and a second metric. The method also includes classifying the data into a first category if the data fails an error detection check, into a second category if the data passes the error detection check and is determined to be unreliable, or into a third category if the data passes the error detection check and is determined to be reliable. A reliability of the data is determined based on at least one of the decoder metrics and a threshold. | 12-20-2012 |
| 20120324318 | Processor Instructions to Accelerate Viterbi Decoding - Viterbi decoding may be performed on a microcontroller by initializing a state-metric array by executing load instructions to load state-metric data from a memory module into a set of registers in the microcontroller. Butterfly processing on the state-metric array is performed by executing Viterbi processing instructions fetched from a program storage module to manipulate the state-metric (SM) data in the set of registers for each Viterbi butterfly in a stage of Viterbi decoding to form a final set of state-metric data and trace bits. After completing each stage, a final set of state-metric data may be stored in the memory module by executing store instructions. | 12-20-2012 |
| 20120331370 | Systems and Methods for Non-Binary Decoding - Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output. | 12-27-2012 |
| 20130007570 | Low Latency Multi-Detector Noise Cancellation - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period. | 01-03-2013 |
| 20130007571 | EARLY STOP METHOD AND APPARATUS FOR TURBO DECODING - In one embodiment, device for early stopping in turbo decoding includes a processor configured to receive a block of data to be decoded, compare hard decision bits resulting from decoding iterations and compare a minimum value of log likelihood ratio (LLR) of decoded bits against a threshold. The processor configured to match hard-decisions with previous iteration results. The processor may be configured to set an early stop rule after the matching hard-decisions with previous iteration results is matched. The processor may be configured to set an early stop rule when the minimum reliability of the output bits exceeds the threshold. | 01-03-2013 |
| 20130013984 | EXPLOITING KNOWN PADDING DATA TO IMPROVE BLOCK DECODE SUCCESS RATE - A method and system of decoding a ccnvolutionally encoded data block having known padding bits. A Viterbi decoder is constrained to a state corresponding to k−1 padding bits immediately adjacent to data bits of the data block, where k is a constraint length of a convolution encoder used to encode the data block. Symbols of the encoded data block that have influence only from the padding bits are discarded. | 01-10-2013 |
| 20130185615 | SOFT OUTPUT VITERBI DETECTOR WITH ERROR EVENT OUTPUT - A first sequence of states associated with a surviving path and a second sequence of states associated with a non-surviving path are determined. A possible error event is determined based at least in part on the first sequence of states and the second sequence of states. The first sequence of states is replaced with the second sequence of states by applying the possible error event to the first sequence of states. | 07-18-2013 |
| 20130185616 | METHOD AND DEVICE FOR IMPLEMENTING VITERBI DECODING - The disclosure provides a method and device for implementing Viterbi decoding. The method comprises the following steps: calculating branch path measurement values of received code words and reference code words; parallel accumulating the branch path measurement values and measurement values corresponding to states to obtain accumulated values according to a state transition diagram, selecting a maximum accumulated value as a new measurement value of a next state, and saving all survival path selection results until data for decoding ends; and starting traceback from a final state to obtain decoded data according to the survival path selection results. In the disclosure, by modifying the traditional serial or serial-parallel mixed mode for calculating accumulated path measurement values to a multi-path fully-parallel calculation mode, the throughput rate of the system data is improved, and the decoding delay is merely in us level. In the disclosure, the traditional mode of sliding window traceback is also changed, traceback whose depth is tow times of the encoding length is only once, but the second section traceback data in the traceback depth is only valid. The accumulated values and state measurement values needn't to be stored, the method is simple and efficient, and the performance of the system is also improved. | 07-18-2013 |
| 20130238962 | SYSTEMS AND METHODS FOR NETWORK CODING USING CONVOLUTIONAL CODES - A network coding method includes receiving a plurality of message packets each having a packet length. Encoding the plurality of message packets by applying a convolutional code across symbols in corresponding positions of the plurality of message packets obtaining a number of encoded packets. The number of encoded packets obtained being more than the number of message packets. | 09-12-2013 |
| 20140068394 | SYSTEMS AND METHODS FOR SECTOR QUALITY DETERMINATION IN A DATA PROCESSING SYSTEM - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination. | 03-06-2014 |
| 20140115430 | Systems and Methods for Iterative Data Processing Using Negative Feedback Iteration - Systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing. | 04-24-2014 |
| 20140129908 | VITERBI BUTTERFLY OPERATIONS - A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length. | 05-08-2014 |
| 20140143641 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D | 05-22-2014 |
| 20140237326 | METHOD AND APPARATUS FOR READING DATA FROM NON-VOLATILE MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC). | 08-21-2014 |
| 20140250352 | Systems and Methods for Signal Reduction Based Data Processor Marginalization - Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability, and/or operational improvement capability. | 09-04-2014 |
| 20150074501 | Cascaded Viterbi Bitstream Generator - A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal. | 03-12-2015 |
| 20160013812 | SYSTEMS AND METHODS FOR NETWORK CODING USING CONVOLUTIONAL CODES | 01-14-2016 |
| 20160065245 | ELECTRONIC SYSTEM WITH VITERBI DECODER MECHANISM AND METHOD OF OPERATION THEREOF - A electronic system includes: a support chip configured to receive an input code stream; a circular Viterbi mechanism, coupled to the support chip, configured to: generate a final path metric for the input code stream, store intermediate path metrics at the repetition depth, generate a repetition path metric for the input code stream, and calculate a soft correlation metric based on the final path metric, the repetition path metric, and the intermediate path metrics. | 03-03-2016 |
