| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714792000 | Trellis code | 43 |
| 20090044083 | Downstream transmitter and cable modem receiver for 1024 QAM - A headend transmitter that transmits 1024 QAM including a 256 QAM modulator which has been modified to have more aggressive forward error correction processing. The 256 QAM modulator outputs 256 QAM points to a summer. Another data modulator receives additional data to be transmitted in a separate, substantially less complex constellation. This modulator processes the additional data to do forward error correction thereon and then maps the encoded data into a less complex constellation such as QPSK, 16 QAM etc. The additional data constellation points are then amplified in a variable gain amplifier and fed to a summer where each additional data point is added by vector summation to one 256 QAM point. The output 1024 QAM point is filtered and shifted to the desired transmission frequency. Legacy cable modem receivers can still receive the 256 QAM point since the addition of the new data just appears to be noise which they can overcome using the parity bits encoded in the transmitted symbols. 1024 QAM cable modem receivers receive both the 256 QAM points and the new data points and output both. | 02-12-2009 |
| 20090063939 | ACS (ADD COMPARE SELECT) IMPLEMENTATION FOR RADIX-4 SOVA (SOFT-OUTPUT VITERBI ALGORITHM) - ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, the ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operable to generate the updated state metric for the state at the current trellis stage as well. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage. | 03-05-2009 |
| 20090063940 | REGISTER EXCHANGE NETWORK FOR RADIX-4 SOVA (SOFT-OUTPUT VITERBI ALGORITHM) - A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within a REX module can be implemented using a radix-4 architecture to increase data throughput. For example, any or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) can be implemented in accordance with the principles of radix-4 decoding processing. | 03-05-2009 |
| 20090100318 | Four-Stage Pipeline Based VDSL2 Viterbi Decoder - A novel method to divide the whole decoding process of the Viterbi decoder into four pipeline stages and the Viterbi decoder therefore. With an appropriate choice on the system clock, the invention trade-off the decoding speed with the hardware cost so that the designed Viterbi decoder is able to satisfy the decoding speed requirement for the highest speed profile in VDSL2 systems, 30 MHz profile. At the same time, with four-stage pipeline to just enough to meet the speed requirement, the hardware cost for the new designed Viterbi decoder is reduced compared with single-staged decoding. | 04-16-2009 |
| 20090100319 | Decoder using a memory for storing state metrics implementing a decoder trellis - A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit. | 04-16-2009 |
| 20090119570 | LOW COMPLEXITY BLIND TRANSPORT FORMAT DETECTION - The present invention relates to a method, apparatus and computer program product for detecting a transport format of a multiplexed transport channel used for transferring binary data, wherein a path metric value which estimates likelihood for a hypothetical trellis path to end at a predetermined state is determined for every state of a trellis stage of a possible end bit position of a data block of the transport channel. Then, for each possible end bit position a number of path metric values which indicate higher likelihood for the hypothetical trellis path to end at said predetermined state than an initial state is calculated, and the best end bit positions which lead to highest values of the calculated number are selected and error checking is performed for the selected best end bit positions to detect the transport format. The proposed selection of best end bit positions leads to a reduced number of decoding operations and thus to a reduced processing complexity. | 05-07-2009 |
| 20090132896 | METRIC CALCULATIONS FOR MAP DECODING USING THE BUTTERFLY STRUCTURE OF THE TRELLIS - A method of calculating backward computations branch metrics for a butterfly in a trellis of a MAP-genre decoding algorithm, the method comprising providing initialised branch metrics for the transitions in the butterfly and incrementing the branch metrics with a group of data values corresponding to said transitions in accordance with control signals derived from the butterfly index and one or more polynomials describing tap positions of the encoding equipment to whose operation the trellis relates, wherein said group comprises systematic bit and parity bit values. | 05-21-2009 |
| 20090172502 | METHOD AND APPARATUS FOR TURBO CODE DECODING - A method and apparatus for turbo code decoding are provided to reduce memory consumption during calculation of state metrics. In an embodiment of a turbo code decoder, a natural recursion unit comprises a plurality of add-compare-select (ACS) units performing natural recursion operations to generate a state metric. The original state metric is then converted to a differential metric before being stored into a memory device. The differential metric contains less data than the state metric so that memory consumption is reduced. To restore the original state metric from the differential metric, a plurality of revival units operating in parallel is provided. Thereby, the state metric is reacquired from the differential metric, and a Log Likelihood Recursion (LLR) operation is accordingly performed by an LLR unit. | 07-02-2009 |
| 20090172503 | DECODING APPARATUS AND DECODING METHOD - The decoding apparatus includes an ACS unit to execute an add-compare-select operation on encoded received data, and an error detector to detect whether there is an error in decoded data calculated based on the executed add-compare-select operation, and if there is an error in the decoded data, the ACS unit additionally executes the add-compare-select operation on the received data. | 07-02-2009 |
| 20090313530 | Error correcting viterbi decoder - Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths. | 12-17-2009 |
| 20090313531 | Methods and Apparatus for Processing a Received Signal Using a Multiple-Step Trellis and Selection Signals for Multiple Trellis Paths - Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle). | 12-17-2009 |
| 20090319874 | Reliability Unit For Determining A Reliability Value For At Least One Bit Decision - A reliability unit is disclosed for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis. | 12-24-2009 |
| 20090319875 | Path Metric Difference Computation Unit For Computing Path Differences Through A Multiple-Step Trellis - A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. The disclosed path metric difference computation unit computes differences between paths through a multiple-step trellis, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of the plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of the plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle. The disclosed path metric difference computation unit comprises one or more path metric difference generators for generating a path metric difference Δ | 12-24-2009 |
| 20100017689 | VSB TRANSMISSION SYSTEM - A vestigial sideband (VSB) modulation transmission system and a method for encoding an input signal in the system are disclosed. According to the present invention, the VSB transmission system includes a convolutional encoder for encoding an input signal, a trellis-coded modulation (TCM) encoder for encoding the convolutionally encoded signal, and a signal mapper mapping the trellis-coded signal to generate a corresponding output signal. Different types of the convolutional encoders are explored, and the experimental results showing the performances of the VSB systems incorporating each type of encoders reveals that a reliable data transmission can be achieved even at a lower input signal to noise ratio when a convolutional encoder is used as an error-correcting encoder in a VSB system. | 01-21-2010 |
| 20100050060 | Path Comparison Unit For Determining Paths In A Trellis That Compete With A Survivor Path - A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path. | 02-25-2010 |
| 20100185925 | Differential Locally Updating Viterbi Decoder - The present invention relates to differential, locally updating Viterbi decoder characterized in that it contains connection management block ( | 07-22-2010 |
| 20100211858 | Scalable VLIW Processor For High-Speed Viterbi and Trellis Coded Modulation Decoding - An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions. | 08-19-2010 |
| 20100251080 | BIT PROBABILITY ESTIMATION METHOD FOR NOISY MODULATION CODE - The present techniques provide systems and methods for decoding an optical data signal returned from an optical disc to retrieve source information. The decoding method is based on a 16 state trellis diagram, and may decode an optical data signal encoded through a modulation code where the input-to-output relationship is not convolutional, such as the 17 Parity Preserve/Prohibit (17pp) modulation code. A trellis diagram may enable non-convolutional trellis-modulated data to be more efficiently decoded. Further, the 16 state trellis diagram of the present techniques provides a unique path for each input-to-output bit pair, such that no information about input bits may be lost on parallel paths in a trellis diagram. | 09-30-2010 |
| 20100262896 | Signal mapper for reducing error coefficient - An improved mapping policy, signal mapper, transmitter, receiver, and communication system are introduced. The improved signal mapping policy alternates between standard and inverted bit mapping functions at selected phase states to reduce the error coefficient of MSK and other types of CPFSK signals. The proposed policy can more generally be applied to other types of signals with memory as well. Simulations show that the mapping policy can significantly improve performance particularly at lower to moderate SNR values. | 10-14-2010 |
| 20100269026 | ERROR PATTERN GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING - The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths. | 10-21-2010 |
| 20100293442 | MULTI-TAP FREQUENCY DOMAIN EQUALIZATION WITH DECISION FEEDBACK AND TRELLIS DECODING - An input estimator is based on a combined MFDQ-DF and trellis for use in, for example, an ADSL environment. In particular, for an ADSL implementation, the system will have one feedback tap for the decision feedback. However, it should be appreciated that the idea and basic concept of using the structure of a trellis to aid in determining the feedback point can be extended to any system using a feedback equalizer to estimate input to a trellis decoder. | 11-18-2010 |
| 20100299582 | MULTI-TAP FREQUENCY DOMAIN EQUALIZATION WITH DECISION FEEDBACK AND TRELLIS DECODING - An input estimator is based on a combined MFDQ-DF and trellis for use in, for example, an ADSL environment. In particular, for an ADSL implementation, the system will have one feedback tap for the decision feedback. However, it should be appreciated that the idea and basic concept of using the structure of a trellis to aid in determining the feedback point can be extended to any system using a feedback equalizer to estimate input to a trellis decoder. | 11-25-2010 |
| 20110087952 | RECOVERY OF TRANSMISSION ERRORS - A method for recovering transmission errors, comprising: receiving a data packet ( | 04-14-2011 |
| 20110113309 | SYSTEM AND METHOD FOR DECODING A MESSAGE USING A PRIORI INFORMATION - Methods and systems are disclosed for decoding digital data received by a correspondent device over a communication channel. The data includes a component corresponding to a plurality of values unknown to the correspondent device and a component corresponding to one or more values known a priori by the correspondent device. To perform decoding, the correspondent device retrieves from memory at least one of the one or more known values. The correspondent device then applies a statistical measure using the known value(s) to estimate the location of the component corresponding to the one or more known values. The one or more known values and the estimated location of the component corresponding to the one or more known values are then used to assist in decoding the data. | 05-12-2011 |
| 20110138259 | High Performance Digital Signal Processing In Software Radios - An extensive use of look-up table (LUT) and single instruction multiple data (SIMD) in different algorithms in a software-defined radio (SDR) system is described. In particular, the LUT is used during spreading modulation, mapping and spreading, scrambling, de-scrambling, soft demapping, and the like. The SIMD is executed by a multi-core processor during implementation of a “min” operation to find an optimal path in a Trellis diagram for a Viterbi decoder. | 06-09-2011 |
| 20110167322 | Methods to improve ACS performance - In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree. | 07-07-2011 |
| 20120144274 | RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING - A method for forward error correction decoding is disclosed. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword. | 06-07-2012 |
| 20120159288 | Soft Output Viterbi Algorithm Method and Decoder - A method of decoding a block with a Soft Output Viterbi Algorithm (SOVA) using a trellis representation and a sliding window wherein each position of the sliding window has a path determination stage at one end of the sliding window and a symbol decision stage at another end of the sliding window is disclosed. The method comprises determining, for each path determination stage and for each node of the path determination stage, a surviving path (including a surviving path input symbol and a surviving decision stage node) and a concurrent path (including a concurrent path input symbol and a concurrent decision stage node) based on path metrics. A path metric disparity value is calculated and stored for each node. Based on decision criteria, a soft output value of the surviving decision stage node is determined as either of the path metric disparity value of the node of the path determination stage, a function of the path metric disparity value of the node of the path determination stage and the stored path metric disparity value of the concurrent decision stage node, and the stored path metric disparity value of the surviving decision stage node. Corresponding computer program product, decoder and communication apparatus are also disclosed. | 06-21-2012 |
| 20120198316 | METHOD AND APPARATUS FOR STORING SURVIVOR PATHS IN A VITERBI DETECTOR USING SYSTEMATIC POINTER EXCHANGE - A survivor path memory is provided for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state. The input processor generates a control signal that exchanges one or more pointers based on a trellis structure, wherein each of the pointers points to one of the flip flops. | 08-02-2012 |
| 20130111306 | Detector with Soft Pruning | 05-02-2013 |
| 20130139041 | METHOD AND SYSTEM FOR CYCLIC REDUNDANCY CHECK - The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described. | 05-30-2013 |
| 20130151933 | RECEIVING/TRANSMITTING SYSTEM AND DATA PROCESSING METHOD IN THE RECEIVING/TRANSMITTING SYSTEM - According to one embodiment, a transmitting system includes: a randomizer for randomizing mobile service data; a processor for Serial Concatenated Convolutional Coding (SCCC) outer-encoding the randomized mobile service data; a first formatter for forming a first data group including the SCCC outer-encoded mobile service data; a deinterleaver for deinterleaving data of the first data group to output a second data group comprising data packets including a portion of the deinterleaved data, wherein the data packets are spaced at least one data packet apart; and a trellis encoder for trellis encoding the deinterleaved data. | 06-13-2013 |
| 20130198594 | Methods for Viterbi Decoder Implementation - Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget. | 08-01-2013 |
| 20130246894 | DECODING METHOD AND APPARATUS FOR NON-BINARY, LOW-DENSITY, PARITY CHECK CODES - Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute d | 09-19-2013 |
| 20130275841 | DECODING METHOD AND DECODER - The method according to the invention relates to the decoding of a sequence of symbols, the sequence of symbols having been generated by: calculating a CRC value for an initial message; combining the initial message and the CRC value so as to produce a transformed message; and, encoding the transformed message. The decoding comprises: generating a number of path hypotheses via a trellis diagram corresponding to the trellis diagram of a finite-state machine comprising the encoder and the CRC generator, in which the encoder and the CRC generator are supplied with the same input. According to a preferred embodiment of the method, the trellis diagram is adapted to take into account bit stuffing possibly inserted in the transformed message before encoding. | 10-17-2013 |
| 20130290817 | Method for correcting messages containing bit stuffing - The invention relates to a method for correcting a message the generation of which involves transforming an initial message and inserting bit stuffing into the transformed message, which method comprises providing an observation sequence containing the message to be corrected. A number of path hypotheses are generated via a trellis diagram associated with the transformation. The nodes of the trellis diagram each represent a state of a finite-state machine capable of transforming the initial message and the branches represent the possible transitions between nodes. Among the branches of the trellis diagram, certain represent conditional transitions that may be made only when bit stuffing is present. During the generation of a path hypothesis, bit stuffing is detected and the branches taken are those associated with the detected bit stuffing. The most likely path hypothesis relative to the observation sequence is finally retained. | 10-31-2013 |
| 20140173387 | APPARATUS AND METHOD FOR DETECTING BIT SEQUENCE ROBUSTLY TO CHANGE OF DC OFFSET IN OOK RECEIVER - A method of detecting a bit sequence, includes estimating parameters to be used to determine a probability distribution of a present signal in each of states of a present time, and calculating metrics of the respective states based on the parameters. The method further includes selecting survivor states from the states based on the metrics, and detecting the bit sequence based on a path to each of the survivor states. | 06-19-2014 |
| 20140181625 | READ CHANNEL DATA SIGNAL DETECTION WITH REDUCED-STATE TRELLIS - An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to determine a first set of soft outputs, hard decisions and reliability indicators for a read channel data signal, to determine a second set of soft outputs, hard decisions and reliability indicators based at least in part on the first set of soft outputs, hard decisions and reliability indicators, and to perform an iterative decoding process to decode the read channel data signal based at least in part on the second set of soft outputs, hard decisions and reliability indicators. The first set of soft outputs, hard decisions and reliability indicators are used to determine a reduced-state trellis for determining the second set of soft outputs, hard decisions and reliability indicators. | 06-26-2014 |
| 20140223267 | RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING - A method for forward error correction decoding. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword. | 08-07-2014 |
| 20150333768 | CONVOLUTION-ENCODED HYPER-SPEED CHANNEL WITH ROBUST TRELLIS ERROR-CORRECTION - A method, system, and computer program product for performing robust, parallel data transfer by a processor device. Data is segmented into k-bit segments, where k≧1. The k-bit segments are convolution encoded, using m≧1 stages of delay. The n output streams are transmitted in parallel for increased effective data rate, where n>k. The n output streams are received. The n output streams are exclusive-or'ed with pathing allowed by the convolution encoding, in a trellis-decoding diagram. Error-corrected data is identified as an overall path in the trellis-decoding diagram with zero Hamming radius. | 11-19-2015 |
| 20160036465 | DECODER AND METHOD FOR DECODING AN ENCODED SEQUENCE OF BITS - A decoder including an input, a branch metric unit, a path metric unit, a starting state unit, and a tail path forcing unit, or alternatively, a state consistency unit. The input is configured to receive a encoded sequence of bits. The branch metric unit is configured to determine a plurality of branch metrics for a plurality of respective transitions between a plurality of states in a trellis representation of a code used to generate the encoded sequence of bits. The path metric unit is configured to determine, based on the plurality of branch metrics, path metrics corresponding to a plurality of maximum likelihood survival paths reaching the plurality of respective states in the trellis representation. The starting state unit is configured to store a plurality of starting states for the respective maximum likelihood survival paths. The tail path forcing unit is configured to select a tail path of a maximum likelihood survival path at a w number of states prior to this maximum likelihood survival path's ending state in the trellis representation to result in this maximum likelihood survival path's stored starting and ending states being the same, wherein w is equal to a constraint length of the decoder minus one. The state consistency unit is configured to determine whether a maximum likelihood survival path has an ending state in the trellis representation that is equivalent to its stored starting state, wherein if the state consistency unit's determination is positive, the branch metric unit and path metric unit are configured to end the determinations of the branch and path metrics. | 02-04-2016 |
| 20160191083 | Data Detector With Extended States - A data detector includes a branch metric calculator operable to calculate branch metrics for transitions between states in a trellis for the data detector, and a pruning circuit operable to prune prohibited states from the trellis. The states in the trellis comprise basic states and extended states, where the extended states have a greater number of bits than the basic states. | 06-30-2016 |
| 20160204803 | DECODING METHOD FOR CONVOLUTIONALLY CODED SIGNAL | 07-14-2016 |
