| Entries |
| Document | Title | Date |
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| 20080201624 | Sequential semiconductor device tester - A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command. | 08-21-2008 |
| 20080222472 | METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAINT AT A TIME - A method for automatically generating test patterns for an IC device includes initially generating a subset of available test patterns according to each of a plurality of test constraints for the IC device, determining an incremental amount of total test coverage of the IC device attributable to each of the test constraints as a result of the initially generated subset of test patterns therefor; determining the test constraint initially providing the largest amount of incremental test coverage, and thereafter generating another subset of test patterns therefor; and iteratively determining the current test constraint providing the largest amount of incremental test coverage, and continuing to generate additional test patterns therefor until one or more test exit criteria is reached. | 09-11-2008 |
| 20080222473 | TEST PATTERN GENERATING DEVICE AND TEST PATTERN GENERATING METHOD - An apparatus for LSI test has a risk place extraction unit supplied with a design information of the LSI to specify a place by estimating an error in LSI operation based on the design information of the LSI to write the place on a risk place list, and a pattern generator unit coupled to the risk extraction unit to generate a test pattern responsive to the risk place list, wherein the pattern generator unit generates the test pattern with an operation of the LSI being controlled to be lower than a predetermined threshold to prevent the error in LSI operation from occurring. | 09-11-2008 |
| 20080235548 | TEST APPARATUS, AND ELECTRONIC DEVICE - A test apparatus is provided. The test apparatus includes: a main memory that stores pattern data including at least one pattern bit defining a test signal provided to each of a plurality of terminals of the device under test; a pattern cache memory that caches the pattern data read from the main memory; a pattern generation control section that reads pattern data from the main memory and writes the same to the pattern cache memory; a pattern generating section that sequentially reads the pattern data stored in each cache entry of the pattern cache memory and outputs the same; and a channel circuit that generates a test signal corresponding to each of the plurality of terminals based on the pattern data outputted from the pattern generating section and provides the same to the device under test. | 09-25-2008 |
| 20080235549 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus that tests a device under test. The test apparatus includes a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test, an interval register that stores a repeated interval in response to the fact that the repeated interval showing at least one instruction to be repeatedly executed in the test instruction stream has been specified, an instruction cache that caches the test instruction stream read from the pattern memory, a memory control section that reads the test instruction stream from the pattern memory and writes the read stream into the instruction cache, a pattern generating section that sequentially reads and executes instructions included in the test instruction stream from the instruction cache and generates a test pattern corresponding to the executed instruction, and a signal output section that generates a test signal based on the test pattern and supplies the generated signal to the device under test. The pattern generating section repeatedly executes an instruction stream within the repeated interval in the test instruction stream when the repeated interval is stored on the interval register. | 09-25-2008 |
| 20080235550 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus for testing a device under test. The test apparatus includes a main instruction storing section that stores thereon a main test instruction sequence, a sub instruction storing section that stores thereon a sub test instruction sequence which is executed when a subroutine call instruction included in the main test instruction sequence is executed, a pattern generating section that (i) sequentially reads and executes an instruction from the main test instruction sequence and outputs (I) a test pattern associated with the executed instruction and (II) timing set information designating a combination of timings for output of the test pattern, (ii) under a condition of executing the subroutine call instruction, sequentially reads and executes an instruction from the sub test instruction sequence designated by the executed subroutine call instruction and outputs (1) a test pattern associated with the executed instruction and (2) timing set information for a test pattern associated with the subroutine call instruction or an instruction which precedes the subroutine call instruction in the main test instruction sequence, and a test signal output section that generates a test signal in accordance with the test pattern, and supplies the test signal to the device under test at a timing designated by the timing set information. | 09-25-2008 |
| 20080250291 | TEST APPARATUS AND ELECTRONIC DEVICE - A test apparatus that tests a device under test is provided. | 10-09-2008 |
| 20080263423 | System and Method for Nonlinear Statistical Encoding in Test Data Compression - A method for test data compression includes generating a plurality of test cubes, each test cube comprising test cube data. Each test cube is compared with at least one other test cube, as test cube pairs, to generate a compatibility rating for each compared test cube pair. The compared test cube pair with the highest compatibility rating is determined. The compared test cube pair with the highest compatibility rating is grouped into a test cube set. The remaining test cubes are grouped into test cube sets, as test cube pairs, based on the compatibility ratings of the compared test cube pairs. | 10-23-2008 |
| 20080270865 | Vendor Independent Method to Merge Coverage Results for Different Designs - A method, computer program product, and data processing system for combining results regarding test sequences' coverage of events in testing a plurality of related semiconductor designs are disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to the designs under test are transmitted to a “backend” computer in the form of an ordered dictionary of events and bitmap and/or countmap data structures. The backend computer combines results from each test sequence in a cumulative fashion to measure the overall coverage of the set of test sequences over the plurality of designs. | 10-30-2008 |
| 20080313516 | Signal Generator and User Interface for Setting Test Sequences and Parameters of a Test Signal - A signal generator generates a WiMedia ultra wideband test signal with a user interface for setting test sequences and parameters of the test signal. Parameters are set for Presentation Protocol Data Units associated with Packet Groups of the test signal. A signal processing unit compiles the Groups containing the Presentation Protocol Data units to generate digital data representative of the test signal. A waveform generator receives the digital data and generating a test signal output having Packet Groups containing Presentation Protocol Data Units. A method is describes for setting test sequences and parameters of an ultra wideband test signal test signal with a user interface of the signal generator. | 12-18-2008 |
| 20090006917 | TEST CIRCUIT FOR SUPPORTING CONCURRENT TEST MODE IN A SEMICONDUCTOR MEMORY - A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving test mode input signals while test modes are being activated, and simultaneously providing the decoding signals if predetermined concurrent test mode signals are received. | 01-01-2009 |
| 20090013230 | CIRCUIT ARRANGEMENT AND METHOD OF TESTING AND/OR DIAGNOSING THE SAME - To further develop a circuit arrangement ( | 01-08-2009 |
| 20090024891 | System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation - A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units. | 01-22-2009 |
| 20090024892 | System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation - A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking. | 01-22-2009 |
| 20090024893 | INTEGRATED CIRCUIT ARRANGEMENT AND DESIGN METHOD - An integrated circuit (IC) arrangement ( | 01-22-2009 |
| 20090049354 | Single-pass, concurrent-validation methods for generating test patterns for sequential circuits - A single-pass, concurrent validation method for generating test pattern sequences for sequential circuits maps fault objects arriving at circuit next-state lines into good next-state fault objects, and passes these mapped results to a next time-frame by placing the good next-state fault objects on present-state lines corresponding to the next-state lines at which to fault objects arrived. Path-enabling functions created during an initial time-frame are reused for all subsequent time-frames, permitting a fault-propagation size and a path-enabling function size to be bounded by a function size established during the initial time-frame. A valid test pattern sequence is found when a primary output line has a good output level that is a complement of a faulty output level for the line. In one embodiment, the determination and comparison of output levels is carried out concurrently. | 02-19-2009 |
| 20090125772 | WIRELESS EMBEDDED TEST SIGNAL GENERATION - An RF/Microwave on-chip signal source for testing an integrated circuit embedded in a substrate is provided. The signal source includes an on-chip antenna embedded in the substrate to receive a signal from a signal source external to the substrate. The signal source also includes a frequency divider circuit also embedded in the substrate. The frequency divider converts one or more frequencies of the signal into an operating frequency of the integrated circuit, the signal at the operating frequency of the integrated circuit defining an on-chip test signal. The signal source further includes one or more output buffers embedded in the substrate to provide a signal interface with the integrated circuit. | 05-14-2009 |
| 20090183045 | TESTING SYSTEM FOR A DEVICE UNDER TEST - A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so as to execute a test algorithm, so as to generate a transmission signal upon execution of the test algorithm, and so as to generate a test environment with reference to the transmission signal. The platform module is operable so as to conduct testing of the DUT using the test information stored in the test parameter-generating device under the test environment generated by the test parameter-generating device. | 07-16-2009 |
| 20090265597 | SIGNAL OUTPUT DEVICE, SIGNAL DETECTION DEVICE, TESTER, ELECTRON DEVICE, AND PROGRAM - There is provided a signal output apparatus for outputting a pattern signal. The signal output apparatus includes a pattern generating section that generates waveform data of the pattern signal to be generated, a timing generating section that generates timing signals in accordance with an expected pattern cycle time of the pattern signal, a timing control section that receives the waveform data output from the pattern generating section, and controls output timings of the timing signals to be output from the timing generating section, in accordance with the waveform data, and a waveform shaping section that generates the pattern signal corresponding to data values of the waveform data output from the pattern generating section, in accordance with the timing signals output from the timing generating section. | 10-22-2009 |
| 20090271677 | Data Transformation Method and Related Device for a Testing System - A data transformation method for a testing system includes receiving a test signal comprising a test data and a timing information corresponding to the test data, and transforming the test data according to the timing information, so as to generate a test pattern. | 10-29-2009 |
| 20090282307 | Optimizing test code generation for verification environment - A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets. | 11-12-2009 |
| 20090319842 | GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM - Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device | 12-24-2009 |
| 20100017668 | SYSTEM AND METHOD FOR DIGITAL LOGIC TESTING - Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided. | 01-21-2010 |
| 20100023824 | METHODS FOR GENERATING TEST PATTERNS FOR SEQUENTIAL CIRCUITS - A single-pass method for test pattern generation for sequential circuits employs a local-fault at each time-frame. The result is that a fault arriving at circuit primary output lines unambiguously signals the discovery of a valid test pattern sequence for the fault. The valid test pattern sequence is reconstructed from stored history and is used to test a sequential circuit. | 01-28-2010 |
| 20100023825 | SELF-TEST CIRCUIT FOR HIGH-DEFINITION MULTIMEDIA INTERFACE INTEGRATED CIRCUITS - A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder. | 01-28-2010 |
| 20100058131 | TEST APPARATUS, TEST VECTOR GENERATE UNIT, TEST METHOD, PROGRAM, AND RECORDING MEDIUM - Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a vector selecting section that selects test vectors that cause a prescribed characteristic of the device under test, which is to be measured when test signals that are each based on one of the test vectors are supplied to the device under test, to fulfill a preset condition; and a judging section that judges pass/fail of the device under test based on measured values of the prescribed characteristic of the device under test supplied with the test signal based on the test vectors selected by the vector selecting section. | 03-04-2010 |
| 20100095179 | TEST PATTERN GENERATION METHOD FOR AVOIDING FALSE TESTING IN TWO-PATTERN TESTING FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A test pattern generation method for determining if a combinational portion | 04-15-2010 |
| 20100100786 | SERIAL TEST MODE OF AN INTEGRATED CIRCUIT (IC) - A methodology to perform testing of integrated circuits (IC) wherein a reduced number of Input/Output (IO) pins may used to load testing patterns and capture test results from test structures after an IC has been installed in its intended application is provided. This methodology utilizes a software engine that receives and translates a parallel test pattern into serial data patterns operable to be provided on the reduced number of I/O pins. A serial process loader then loads the serial data patterns to the test structures within the IC. The IC receives the serial patterns and in turn translates them into parallel test patterns in order to apply the test patterns to the appropriate test structures. The results are captured and then translated into a serial format for communication from the IC to a test unit for analysis. | 04-22-2010 |
| 20100146350 | TEST GENERATION METHODS FOR REDUCING POWER DISSIPATION AND SUPPLY CURRENTS - Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored. | 06-10-2010 |
| 20100153801 | METHOD FOR AT SPEED TESTING OF DEVICES - A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module. | 06-17-2010 |
| 20100162064 | METHOD AND APPARATUS FOR COVERING A MULTILAYER PROCESS SPACE DURING AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths. | 06-24-2010 |
| 20100218063 | DON'T-CARE-BIT IDENTIFICATION METHOD AND DON'T-CARE-BIT IDENTIFICATION PROGRAM - The provided are a don't-care-bit identification method and program for identifying don't-care-bits from the first and the second input vectors in an input-vector pair while keeping the sensitization status of paths, in a combinational circuit, sensitized by applying the first and the second input vectors in serial to input lines of combinational circuit. The method identifies an unspecified bit from the first and the second input vectors V | 08-26-2010 |
| 20100229060 | Compression Based On Deterministic Vector Clustering Of Incompatible Test Cubes - The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data. | 09-09-2010 |
| 20100287432 | METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns. | 11-11-2010 |
| 20100332931 | Method for Speeding Up Serial Data Tolerance Testing - A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount. | 12-30-2010 |
| 20110022910 | ARITHMETIC LOGIC UNIT FOR USE WITHIN A FLIGHT CONTROL SYSTEM - An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand. | 01-27-2011 |
| 20110055650 | Hold Transition Fault Model and Test Generation Method - A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0. | 03-03-2011 |
| 20110055651 | High-speed serial transfer device test method, program, and device - A test pattern generating unit generates a test pattern in which unconverted data is arranged such that same values of 0 or 1 bits in converted data according to a code conversion table are successively transferred to each of a plurality of serial transfer channels that a high-speed serial transfer device has. A basic pattern setting unit sets a basic pattern while considering a byte order method and an RD value of code conversion in the high-speed serial transfer device. A basic pattern resetting unit resets the basic pattern in accordance with a channel usage method of a bit transfer order in the high-speed serial transfer device. A basic pattern rearranging unit performs rearrangement such that the basic pattern is transferred to each of the channels in accordance with the number of used channels and a channel usage method such as bit transfer order in the high-speed serial transfer device. | 03-03-2011 |
| 20110087942 | Programmable Protocol Generator - A semiconductor device tester includes programmable hardware configured to test a semiconductor device under test. The programmable hardware is programmed with two or more pattern generators to control a flow of data to and from the semiconductor device under test. | 04-14-2011 |
| 20110209024 | GENERATION DEVICE, CLASSIFICATION METHOD, GENERATION METHOD, AND PROGRAM - Provided are a generation device and the like for generating a new vector whose volume can be reduced rapidly when an output pattern derived from a decompressor of a logic circuit under test includes an unspecified bit in relation to the logic circuit under test. | 08-25-2011 |
| 20110219278 | Panel Driving Circuit That Generates Panel Test Pattern and Panel Test Method Thereof - A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device. | 09-08-2011 |
| 20120089879 | METHOD AND SYSTEM FOR IDENTIFYING POWER DEFECTS USING TEST PATTERN SWITCHING ACTIVITY - A method and system for identifying power defects using test pattern switching activity is disclosed. In one embodiment, a plurality of test patterns is applied to a circuit under test, and failure test patterns are identified from the plurality of test patterns by comparing the test result with the predicted test result. A switching activity count is obtained for each of the plurality of test patterns. Based on the switching activity count, ranks for each of the plurality of test patterns are provided. A correlation analysis is performed between the failure test patterns and the ranks of the switching activities. When there is a high correlation between the failure test pattern and the ranks of the switching activities, it is determined that the circuit likely contains a power defect. A power defect analysis is performed under the presence of the high correlation. | 04-12-2012 |
| 20120117436 | METHOD AND APPARATUS FOR DEFERRED SCHEDULING FOR JTAG SYSTEMS - A deferred scheduling capability supports deferred scheduling when performing testing via a scan chain of a unit under test. A processing module is configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP). A reordering buffer module is configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test. A vector transformation module is configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector. | 05-10-2012 |
| 20120144256 | System and Method for Analyzing an Electronics Device Including a Logic Analyzer - A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device. | 06-07-2012 |
| 20120151289 | ELECTRICAL CONNECTIVITY TEST APPARATUS AND METHODS - Methods and apparatus are provided related to testing electrical connectivity. A sequence of distinct test data signal patterns is issued. The test data signals are propagated by way of respective pathways and electrical connectors. A feedback signal is generated in accordance with a test function for each of the test data signal patterns. A test results message is generated in accordance with the feedback signals, which can include specific diagnostic or identifying information. | 06-14-2012 |
| 20120221911 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 08-30-2012 |
| 20120297264 | Root Cause Distribution Determination Based On Layout Aware Scan Diagnosis Results - Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting. | 11-22-2012 |
| 20120311392 | AUTOMATED REGRESSION TESTING INTERMEDIARY - An automated regression testing intermediary configured to accept a first set of automated test instructions from an application testing tool. A data structure comprising predefined fields is configured so when a test instruction is received from the application testing tool, a command will be used to identify at least one field of the data structure that will be populated with a parameter test instruction. A library of generic target automated test instructions is provided. Each generic test instruction has a form and format different from the received test instruction. The intermediary is configured to select generic target automated test instructions from the library and populate selected generic target automated test instructions with parameters obtained from the data structure such that the resulting created target-specific automated test instructions can be used to regression test the application under test. | 12-06-2012 |
| 20130007548 | AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING - An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode. | 01-03-2013 |
| 20130311844 | Test Card for Testing One or More Devices Under Test and Tester - A test card for testing one or more devices under test includes a plurality of test resources configured to communicate with the one or more devices under test. The test card further includes a matching circuit configured to receive a test sequence of at least two matching instructions followed by one or more processing instructions. The matching instructions define a group of resources which are to operate in accordance with the processing instructions. The matching circuit is configured to determine based on the at least two matching instructions whether a given test resource out of a plurality of test resources belongs to the group or not and to forward the processing instructions to the given test resource if the given test resource belongs to the group and to not forward the processing instructions to the given test resource if the given test resource does not belong to the group. | 11-21-2013 |
| 20130346820 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 12-26-2013 |
| 20140089752 | METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER CIRCUITRY - Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round. | 03-27-2014 |
| 20140089753 | PANEL DRIVING CIRCUIT THAT GENERATES PANEL TEST PATTERN AND PANEL TEST METHOD THEREOF - A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device. | 03-27-2014 |
| 20140122955 | PRBS TEST MEMORY INTERFACE CONSIDERING DDR BURST OPERATION - A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The multiple cycles are transmitted through the interconnect to the external memory one after another such that a value of the data bit being transmitted is switched for each cycle. In another embodiment, an electronic component comprises an interface, a translation unit, and a test module. The translation module is configured to receive a burst from the external memory through the interface and is configured to translate the burst into a data word. The test module is configured to receive the data word from the translation module and is configured to compare the data word to a test pattern to detect an interconnect defect. | 05-01-2014 |
| 20140129890 | Test Pattern Optimization for LDPC Based Flawscan - A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length constraints of the data pattern, and written to a storage medium. | 05-08-2014 |
| 20140129891 | METHODS AND DEVICES TO INCREASE MEMORY DEVICE DATA RELIABILITY - A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits. | 05-08-2014 |
| 20140289579 | Reordering or Removal of Test Patterns for Detecting Faults in Integrated Circuit - A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped. | 09-25-2014 |
| 20140344637 | SEQUENTIAL LOGIC SENSITIZATION FROM STRUCTURAL DESCRIPTION - A method of sensitizing a sequential circuit is described. This sensitizing generates stimuli to drive any circuit output to a predetermined value or transition. The method includes creating a directed graph of the sequential circuit. Nodes of the graphs can be topologically sorted. In one embodiment, feedback loops in the directed graph can be removed before topologically sorting the nodes. Final vectors for the sequential circuit can be generated based on the sorted nodes. Notably, the final vectors are expressed only by primary inputs to the sequential circuit. Using only primary inputs in the final vectors accurately replicates the sequential circuit under test, thereby ensuring accurate timing, power, and noise arcs are measured. | 11-20-2014 |
| 20150113349 | SELECTIVE TEST PATTERN PROCESSOR - A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device. | 04-23-2015 |
| 20150113350 | SELECTIVE TEST PATTERN PROCESSOR - A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device. | 04-23-2015 |
| 20150149847 | Channel Sharing For Testing Circuits Having Non-Identical Cores - Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks. | 05-28-2015 |
| 20160003907 | CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES - A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. | 01-07-2016 |
| 20160011257 | SYSTEM FOR AND METHOD OF SEMICONDUCTOR FAULT DETECTION | 01-14-2016 |
| 20160025810 | DIAGNOSIS AND DEBUG WITH TRUNCATED SIMULATION - Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip. | 01-28-2016 |
| 20160154060 | Automated Test Equipment, Instruction Provider for Providing a Sequence of Instructions, Method of Providing Signal to a Device Under Test, Method for Providing a Sequence of Instructions and Test System | 06-02-2016 |
| 20160202314 | TEST CIRCUIT AND METHOD OF SEMICONDUCTOR DEVICE | 07-14-2016 |
| 20180024192 | TEST PATTERN COUNT REDUCTION FOR TESTING DELAY FAULTS | 01-25-2018 |
