| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714739000 | Random pattern generation (includes pseudorandom pattern) | 12 |
| 20080215945 | System and method for system-on-chip interconnect verification - A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare. | 09-04-2008 |
| 20080222474 | Pseudorandom number generator, semiconductor integrated circuit, pseudorandom number generator control apparatus, pseudorandom number generator control method, and computer product - In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log | 09-11-2008 |
| 20080320352 | METHODS FOR DISTRIBUTION OF TEST GENERATION PROGRAMS - As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm. | 12-25-2008 |
| 20090024894 | SYSTEM AND METHOD FOR PREDICTING IWARX AND STWCX INSTRUCTIONS IN TEST PATTERN GENERATION AND SIMULATION FOR PROCESSOR DESIGN VERIFICATION/VALIDATION IN INTERRUPT MODE - During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address. | 01-22-2009 |
| 20090037787 | Apparatus and methods for autonomous testing of random number generators - Apparatus for testing a random number generator includes a random number generating unit that generates and outputs random numbers, and a switching unit that receives the random numbers from the random number generating unit and selectively transmits the random numbers in response to a switching control signal. A test unit performs a basic test on the random numbers to determine whether the transmitted random numbers are within a statistical range, controls the generation of random numbers according to a result of the basic test, and outputs the switching control signal based on whether a test suite is finished. Methods include performing a basic test on generated random numbers to determine whether the random numbers are within a statistical range, controlling the generation of random numbers in response to a result of the basic test and whether the basic test is finished, determining upon completion of the basic test if a test suite is finished, and if the test suite is finished, outputting the random numbers as final random numbers. | 02-05-2009 |
| 20090106615 | TEST METHOD OF INTEGRATED CIRCUIT WITH RANDOM-NUMBER GENERATION CIRCUIT AND INTEGRATED CIRCUIT WITH RANDOM-NUMBER GENERATION CIRCUIT - Random numbers output from a random-number generation circuit, for which an optimized control parameter is set, at a predetermined timing after power-on reset are obtained after each power-on reset, by repeating the power-on reset with respect to a system LSI for a preset number of times, and a test of the obtained predetermined number of random numbers is performed by using a test circuit incorporated in the system LSI to determine the quality of the random-number generation circuit incorporated in the system LSI. | 04-23-2009 |
| 20090119563 | METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS - Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs. | 05-07-2009 |
| 20090164861 | METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction sequences that preserve instruction order dependencies and randomly selecting data values from a valid range of data values. Multiple instruction streamers may be employed to simulate interrupt handlers and other functional design units sharing a control command bus. A priority scheduler sequences the instruction sequences generated by multiple instruction streamers based on a specified priority scheme. | 06-25-2009 |
| 20100031105 | RANDOM ERROR SIGNAL GENERATOR - In a random error signal generator, an M-sequence generation circuit outputs, in parallel, pieces of bit data stored in each register, a first generation circuit sequentially outputs first reference values C which are changed by a predetermined value in response to clocks, a second generation circuit outputs a second reference value D which is shifted from the first reference value C by a range value E which is determined depending on an error rate p. A comparison and determination unit outputs random error signals to be error bits when a numeric value A of the bit data output exists between the first and second reference values C, D. The random error signal has the error rate p, the number of times of error occurrences follows Poisson distribution, and a distribution of adjacent error occurrence intervals follows a geometric distribution. | 02-04-2010 |
| 20110022911 | SYSTEM PERFORMANCE TEST METHOD, PROGRAM AND APPARATUS - A system performance test method for testing performance of a server system includes: (A) a step of issuing a plurality of types of request sequences with a specified issuance ratio to the server system; and (B) a step of measuring performance of the server system during processing of the plurality of types of request sequences. Each of the plurality of types of request sequences is comprised of a sequence of requests to the server system. | 01-27-2011 |
| 20120278675 | METHOD AND APPARATUS FOR PERFORMING IMPLICATION AND DECISION MAKING USING MULTIPLE VALUE SYSTEMS DURING CONSTRAINT SOLVING - Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. An embodiment can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. Next, the embodiment can generate a circuit model based on the set of constraints, wherein assignable values for at least one node in the circuit model are represented in multiple value systems. The embodiment can then assign random values to the set of random variables based on the circuit model. | 11-01-2012 |
| 20120317454 | MULTI-TARGETING BOOLEAN SATISFIABILITY-BASED TEST PATTERN GENERATION - Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults. | 12-13-2012 |
