| Entries |
| Document | Title | Date |
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| 20080209287 | Method and Apparatus for Performing Equivalence Checking on Circuit Designs Having Differing Clocking and Latching Schemes - A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical “1” to verify the sequential equivalence of the transformed netlist. | 08-28-2008 |
| 20080209288 | APPARATUS FOR LOCATING A DEFECT IN A SCAN CHAIN WHILE TESTING DIGITAL LOGIC - An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns. | 08-28-2008 |
| 20080209289 | PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME - An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank. | 08-28-2008 |
| 20080215940 | Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test - As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference has a predetermined relationship to a stored value, the stored value is overwritten using the reference. The stored value is then used to estimate the position of a stuck-at defect in the scan chain. | 09-04-2008 |
| 20080215941 | Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications - A design structure embodied in a machine readable medium used in a design process, includes a circuit for data storage. The circuit includes a double edge clock generation circuit for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock; a scan clock generation circuit for generating first and second scan clock signals; a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, the scannable pulse flip-flop circuit including a scan input and a scan output connected with the internal storage node, and receptive to the pulse clock signal and the scan clock signals. The scannable pulse flip-flop circuit is configured to be operable in a function mode of operation and a scan mode of operation. | 09-04-2008 |
| 20080222468 | Method and Dual Interlocked Storage Cell Latch for Implementing Enhanced Testability - A method and a Dual Interlocked Storage Cell (DICE) latch implementing enhanced testability includes an L1 latch and an L2 latch coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode. | 09-11-2008 |
| 20080222469 | Method and Dual Interlocked Storage Cell Latch for Implementing Enhanced Testability - A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch includes an L1 latch and an L2 latch are coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode. | 09-11-2008 |
| 20080222470 | SCAN TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND SCAN ENABLE SIGNAL TIME CONTROL CIRCUIT - A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a practical operation speed, and a controller configured to control the clock generator based on the scan enable signals. | 09-11-2008 |
| 20080244341 | METHODS AND APPARATUS FOR COMMUNICATING WITH A TARGET CIRCUIT - A system and method are disclosed which may include establishing a stored test vector, including a plurality of data bits, within a vector data engine; transmitting the stored test vector to a memory array; performing at least one arithmetic or logical operation upon the stored test vector by a vector data generator within the vector data engine to update the stored test vector; and repeating the steps of transmitting and performing so as to continuously transmit continuously changing stored test vectors to the memory array. | 10-02-2008 |
| 20080244342 | SCAN STRING SEGMENTATION FOR DIGITAL TEST COMPRESSION - One may use a new technique to determine the placement of exclusive-ors in each scan string of a chip to achieve improved test vector compression, and one may combine this technique with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, to minimize the changes to existing test logic insertion and scan string reordering, and to minimize the test vector compression computation time. | 10-02-2008 |
| 20080250283 | POWER SAVING FLIP-FLOP - A scannable flip-flop and method are provided. The flip-flop includes a clock input, a normal data input, a test data input, a normal data output and a scan data output. The flip-flop has a normal operating mode during which the normal data output is enabled and the scan data output disabled and has a scan-shift mode during which the normal data output is disabled and the scan data output is enabled. | 10-09-2008 |
| 20080250284 | Fault dictionary-based scan chain failure diagnosis - A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified. | 10-09-2008 |
| 20080250285 | Circuit Arrangement, Electronic Mechanism, Electrical Turn out and Procedures for the Operation of One Circuit Arrangement - A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage. | 10-09-2008 |
| 20080250286 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 10-09-2008 |
| 20080256405 | COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS - A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip. | 10-16-2008 |
| 20080270856 | SEMICONDUCTOR MEMORY DEVICE - Malfunction of burn-in test caused by a failure of setting a determined test mode due to a “line defect” of the test is prevented. A semiconductor memory device having a logic unit including a control circuit C | 10-30-2008 |
| 20080276140 | SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP - A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains. | 11-06-2008 |
| 20080276141 | Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit - A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor. | 11-06-2008 |
| 20080288837 | Testing of a Circuit That has an Asynchronous Timing Circuit - Special test measures are required to test an asynchronous timing circuit. The asynchronous timing circuit ( | 11-20-2008 |
| 20080288838 | NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, an electrical package includes: an external input portion; an external output portion; a plurality of integrated circuits that is compatible with a compressed deterministic pattern test, each of the integrated circuits including: an input portion; a decompressor that is connected to the input portion; scan chains that are connected to the decompressor; a compactor that is connected to the scan chains; a selector that is connected to the compactor and the input portion to selectively output an output of the compactor or an output of the input portion; and an output portion that is connected to the selector. | 11-20-2008 |
| 20080294953 | Removing the effects of unknown test values from compacted test responses - Methods, apparatus, and systems for filtering compacted test responses are disclosed. The methods, apparatus, and systems can be used, for example, to remove the effects of unknown test values. For instance, in one embodiment, a compacted test response from a compactor of a circuit-under-test is received. In this embodiment, the compacted test response includes one or more compacted test response values that are dependent on one or more respective unknown values. The compacted test response is filtered to remove the dependency of at least some of the compacted test response values on the one or more respective unknown values, and a filtered test response is output. Various filtering circuits and testing systems are also disclosed. | 11-27-2008 |
| 20080307277 | DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING - Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value. | 12-11-2008 |
| 20080307278 | APPARATUS FOR EFFICIENTLY LOADING SCAN AND NON-SCAN MEMORY ELEMENTS - The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory elements is cleared. Second, the desired values are loaded into the scan memory elements. Third, the values from the scan memory elements are propagated to the non-scan memory elements. | 12-11-2008 |
| 20080313512 | MULTIPLE USES FOR BIST TEST LATCHES - A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST. | 12-18-2008 |
| 20080320348 | Launch-On-Shift Support for On-Chip-Clocking - A method to perform launch-on-shift scanning for integrated circuits having multiple clock domains is presented. An integrated circuit includes both capture clock domains and non-capture clock domains. The portions of the test vectors for non-capture clock domains are shifted into the scan chains of the non-capture clock domains and allowed to settle prior to the last shift launch cycle and the capture cycle of the capture clock domains. Thus, the ambiguity of the timing between the non-capture domains and the capture domains caused by asynchronous clock signals is eliminated. | 12-25-2008 |
| 20080320349 | eFuse Programming Data Alignment Verification Apparatus and Method - An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses. | 12-25-2008 |
| 20090013226 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 01-08-2009 |
| 20090019327 | GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM - A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus | 01-15-2009 |
| 20090063919 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 03-05-2009 |
| 20090070645 | INTEGRATED CIRCUIT TESTING METHOD AND RELATED CIRCUIT THEREOF - An integrated circuit testing method includes: respectively connecting a plurality of pads in a chip to generate a plurality of scan chains, wherein each scan chain connects two pads and at least one flip-flop in the chip; providing at least a selecting unit, wherein the selecting unit determines a mode according to a plurality of available scan chains after the chip is packaged; and determining a target scan chain to be connected with a target flip-flop corresponding to the selecting unit according to the mode determined by the selecting unit. | 03-12-2009 |
| 20090077437 | Method and system for routing scan chains in an array of processor resources - The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip. | 03-19-2009 |
| 20090083593 | Test Method and Test Program of Semiconductor Logic Circuit Device - The number of output switching scan flip-flops in a capture operation is decreased, which decreases the capture power consumption, so that the reduction of the power supply voltage can be decreased to decrease generation of an erroneous test. For this purpose, 0 or 1 is filled in unspecified bits within a test cube to decrease the output switching scan flip-flops, to convert the test cube into a test vector with no unspecified bit X. In a combinational portion | 03-26-2009 |
| 20090089634 | SCAN TESTING SYSTEM, METHOD AND APPARATUS - Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. | 04-02-2009 |
| 20090106608 | APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING - An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain. | 04-23-2009 |
| 20090106609 | Semiconductor integrated circuit and debug mode determination method - A semiconductor integrated circuit has a terminal to input a debug signal which specifies a debug mode, a reset circuit to generate a reset signal when a power is turned ON, and a debug mode control circuit to output a control signal which causes a shift to the debug mode based on the debug signal and the reset signal. The debug mode control circuit includes a latch circuit to generate a first signal by latching the debug signal, and a register circuit to generate a second signal when written with a permit code, and the control signal is generated based on the first signal and the second signal. | 04-23-2009 |
| 20090106610 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit having a low maximum allowable operating frequency such as an analog circuit can be prevented from being destroyed during a scan test. When a scan test mode signal is “1”, output signals of a first AND circuit and a second AND circuit are fixed to a low level and an output of an OR circuit is fixed to a high level. Therefore, output signals of fourth through sixth flip-flops FF | 04-23-2009 |
| 20090106611 | Microelectronic device and pin arrangement method thereof - The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced. | 04-23-2009 |
| 20090113262 | SYSTEM AND METHOD FOR CONDITIONING AND IDENTIFYING BAD BLOCKS IN INTEGRATED CIRCUITS - An electronic system of an Integrated circuit (IC) for conditioning and identification of bad blocks in the IC is disclosed. The electronic system includes at least one cyclic scan chain and at least one multiplexer. A cyclic scan chain includes a plurality of flip-flops, which are connected in a cascaded manner. A multiplexer is connected between two adjacent flip-flops of the cyclic shift register. The multiplexer has a first input pin connected to output of a first flip-flop, a second input pin connected to a user pin and an output pin connected to an input of a second flip-flop. The multiplexer is configured to condition the plurality of flip-flops through the user pin by programming logic bits in the plurality of flip-flop. The output of the first flip-flop is configured to read the logic bits in the plurality of flip-flops to identify a bad block in the IC. | 04-30-2009 |
| 20090113263 | METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR LOCATIONS OF HOLD TIME FAULTS IN SCAN CHAINS - In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined. | 04-30-2009 |
| 20090119556 | METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS - Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs. | 05-07-2009 |
| 20090144592 | Method and Apparatus for Describing Components Adapted for Dynamically Modifying a Scan Path for System-on-Chip Testing - The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips. | 06-04-2009 |
| 20090144593 | Method and apparatus for describing parallel access to a system-on-chip - The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing. | 06-04-2009 |
| 20090164858 | PROTECTING AN INTEGRATED CIRCUIT TEST MODE - An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit. | 06-25-2009 |
| 20090193303 | TEST ACCESS MECHANISM FOR MULTI-CORE PROCESSOR OR OTHER INTEGRATED CIRCUIT - A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data. | 07-30-2009 |
| 20090193304 | Apparatus and Method for Isolating Portions of a Scan Path of a System-on-Chip - The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level. In one embodiment, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level. In one embodiment, the second hierarchical level may be used for independent, parallel testing while data continues to be propagated through the first hierarchical level. | 07-30-2009 |
| 20090210759 | Scalable Scan-Based Test Architecture With Reduced Test Time And Test Power - A scalable scan-based architecture with reduced test time, test power and test pin-count in scan based testing of ICs. In an embodiment, a test vector is scanned serially into a functional memory element at a first frequency, which then de-multiplexes the bits in the test vector to multiple sub-chains at a lower frequency. Due to the use of lower frequency to scan-in, the power dissipation is reduced. Due to the use of the higher frequency to scan-in the test vector as well as multiple sub-chains, the test time is reduced. Due to the use of the functional memory elements for scanning in the test vector at higher frequency, any number of chains can potentially be supported. | 08-20-2009 |
| 20090210760 | Analog Testing of Ring Oscillators Using Built-In Self Test Apparatus - System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed. Test interrogations are distributed on-chip through an LSSD shift register chain to individually evaluate each of a plurality of the oscillators. | 08-20-2009 |
| 20090228750 | CONTROLLER APPLYING STIMULUS DATA WHILE CONTINUOUSLY RECEIVING SERIAL STIMULUS DATA - An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for transferring serial data between the emulation controller and the emulator. The serial scanning circuitry includes a first state machine having plural states controlling the transfer of serial data. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller. The control circuitry, when connected to the emulation controller, effects the providing and receiving of signals and the transferring of serial data between the emulation controller and the emulator continuously without interruption while the first state machine remains in one state. | 09-10-2009 |
| 20090235132 | METHOD AND APPARATUS FOR BROADCASTING SCAN PATTERNS IN A SCAN-BASED INTEGRATED CIRCUIT - A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. | 09-17-2009 |
| 20090235133 | SLACK-BASED TRANSITION-FAULT TESTING - A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault. | 09-17-2009 |
| 20090235134 | TEST PATTERN GENERATION FOR DIAGNOSING SCAN CHAIN FAILURES - Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. At least some embodiments can be used to locate faults over multiple capture cycles in the scan chain. | 09-17-2009 |
| 20090240995 | METHOD AND APPARATUS FOR IMPROVING RANDOM PATTERN TESTING OF LOGIC STRUCTURES - A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure. | 09-24-2009 |
| 20090249142 | METHOD FOR RACE PREVENTION AND A DEVICE HAVING RACE PREVENTION CAPABILITIES - A method for race prevention and a device that has race prevention capabilities. The method includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. The device includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and between a start point of a second scan mode activation period of the output latching logic. | 10-01-2009 |
| 20090249143 | SCAN CONTROL METHOD, SCAN CONTROL CIRCUIT AND APPARATUS - A scan control method for a circuit device connected with a first bus and having a test access port controller, including setting information indicating a register to be scanned in the circuit device, a number of scan shifts and a scan start via a second bus different from the first bus, and generating based on the information set, by using a sequencer, a signal replacing a test mode signal and a test reset signal transferred via the first bus during testing of the circuit device, and supplying the signal to the test access port controller. | 10-01-2009 |
| 20090259898 | Test vector generating method and test vector generating program of semiconductor logic circuit device - The X-type of each bit permutation is determined (step | 10-15-2009 |
| 20090259899 | METHOD AND APPARATUS FOR AUTOMATIC SCAN COMPLETION IN THE EVENT OF A SYSTEM CHECKSTOP - A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred. | 10-15-2009 |
| 20090259900 | TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT - A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern. | 10-15-2009 |
| 20090265593 | METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR VERIFYING DESIGN RULES - Not only defects in DC characteristics and a degeneracy fault but defects in AC characteristics such as SI faults (a crosstalk faults and an IR-DROP fault) and a delay fault, which tend to increase as design rules become finer in recent years, are detected as a measure used when the finished quality of a semiconductor integrated circuit is evaluated. The defects in the AC characteristics are detected by utilizing a scan path circuit provided to detect the degeneracy fault in the semiconductor integrated circuit, bringing scan chains to states in which shift resistor operations can be effected for the input of patterns by which a glitch fault and the IR-DROP fault between the scan chains can be detected, and not only utilizing variations in power supply voltage fed to the semiconductor integrated circuit and in signal voltage inputted to scan-in terminals but also varying the frequency of the test patterns. | 10-22-2009 |
| 20090271671 | APPARATUS AND METHOD FOR IMPROVED TEST CONTROLLABILITY AND OBSERVABILITY OF RANDOM RESISTANT LOGIC - A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design includes configuring a multiplexer device to pass, to a preexisting storage latch within the design, one of: a signal from one or more observation points within the random resistant logic and an output of first preexisting combinational logic; and selecting a preexisting net within the IC design to generate a randomized logic signal that, in a test mode, is passed to the multiplexer device to serve as a control signal thereto; wherein, in the test mode, the existing storage latch captures data randomly selected from either the existing combinational logic and the one or more observation points and in a normal mode, the existing storage latch captures data from only the existing combinational logic, facilitating random testing of the random resistant logic in a manner that avoids adding latches to the design. | 10-29-2009 |
| 20090271672 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 10-29-2009 |
| 20090271673 | Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time. | 10-29-2009 |
| 20090276668 | SCAN DRIVER - A scan driver includes a voltage setting circuit, a counter circuit, a logic circuit, a dynamic decoder, N level shift circuits and N output stage circuits, wherein N is a natural number. The voltage setting circuit sets N voltage signals to a first level. The counter circuit provides count data to the logic circuit, which generates M control signals according to the count data, wherein M is a natural number. The dynamic decoder includes multiple transistors, arranged in N rows, for receiving the respective N voltage signals. The transistors are further arranged in M columns and are controlled by the respective M control signals to determine levels of the N voltage signals. The N level shift circuits lift the levels of the respective N voltage signals, and the N output stage circuits output respective N gate signals based on the N voltage signals whose levels are shifted. | 11-05-2009 |
| 20090300446 | Selective Per-Cycle Masking Of Scan Chains For System Level Test - Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon. | 12-03-2009 |
| 20090307545 | TESTABLE MULTIPROCESSOR SYSTEM AND A METHOD FOR TESTING A PROCESSOR SYSTEM - A testable processor system ( | 12-10-2009 |
| 20090307546 | PROVIDING TRUSTED ACCESS TO A JTAG SCAN INTERFACE IN A MICROPROCESSOR - A method for securing a scan chain architecture by performing an authentication operation through a trusted software layer to authorize use of a protected scan chain. | 12-10-2009 |
| 20090313514 | Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time. | 12-17-2009 |
| 20100017666 | FAULTY SITE IDENTIFICATION APPARATUS, FAULTY SITE IDENTIFICATION METHOD, AND INTEGRATED CIRCUIT - A faulty site identification apparatus for identifying a faulty site in an integrated circuit, the faulty site identification apparatus including a scan chain constituted by coupling a plurality of sequential circuit elements and adapted to output a scan data by shifting out setting data that is set to each of the plurality of sequential circuits, a setting section that sets the setting data to at least one sequential circuit element of the plurality of sequential circuit elements and an identification section that identifies a faulty site in the scan chain on the basis of the scan data from the scan chain to which the setting data is set to the at least one sequential circuit element by the setting section. | 01-21-2010 |
| 20100031099 | Scan Topology Discovery in Target Systems - Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values. | 02-04-2010 |
| 20100031100 | Series Equivalent Scans Across Multiple Scan Topologies - Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and performing capture and update operations in parallel while scan topology connectivity of two or more of the plurality of scan technologies is enabled. | 02-04-2010 |
| 20100031101 | Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time. | 02-04-2010 |
| 20100064190 | System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits - A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description. | 03-11-2010 |
| 20100083063 | PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY - A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity. | 04-01-2010 |
| 20100095169 | Implementing Isolation of VLSI Scan Chain Using ABIST Test Patterns - A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system. | 04-15-2010 |
| 20100095170 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DELAY FAULT TESTING METHOD THEREOF - A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops. | 04-15-2010 |
| 20100095171 | SCAN TESTING SYSTEM, METHOD AND APPARATUS - Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. | 04-15-2010 |
| 20100115353 | SYSTEM AND METHOD FOR TESTING APPLICATION-SPECIFIC BLOCKS EMBEDDED IN RECONFIGURABLE ARRAYS - A method and apparatus for testing an application-specific functional block embedded in a user programmable fabric, the user programmable fabric comprising configuration data control means having an inputs and an outputs and the application-specific functional block having inputs and an outputs. The method comprising the steps of routing the outputs of the configuration data control means of the user programmable fabric to the inputs of the application-specific functional block, sending configuration data to configure the application-specific functional block to the configuration control means of the user programmable fabric, transferring the configuration data to the configuration memory means of the application-specific functional block, sending test data to test the application-specific functional block to the configuration control means of the user programmable fabric and routing the outputs of the configuration data control means of the user programmable fabric to the inputs of the application-specific functional block. The method also includes the steps of testing, using the test data, the application-specific functional block, routing the outputs of the application-specific functional block to the inputs of the configuration data control means of the user programmable fabric and receiving the test output data from the configuration control means of the user programmable fabric. | 05-06-2010 |
| 20100115354 | SCAN RESPONSE REUSE METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure. | 05-06-2010 |
| 20100115355 | METHOD AND APPARATUS FOR IMPROVING UPLINK TRANSMISSION IN A WIRELESS COMMUNICATION SYSTEM - A method of improving uplink transmission for a MAC layer of a UE in a wireless communication system includes monitoring a transmission buffer and controlling a periodic buffer status report (BSR) timer to expire when lower priority data arrives at the transmission buffer in the condition that a periodic BSR is configured and running. | 05-06-2010 |
| 20100122132 | METHOD AND SYSTEM FOR DEBUGGING USING REPLICATED LOGIC AND TRIGGER LOGIC - A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded. | 05-13-2010 |
| 20100138707 | PROCESSOR AND METHOD FOR CONTROLLING STORAGE-DEVICE TEST UNIT - A processor includes an arithmetic device, a storage device that holds arithmetic data, a data generator that generates test data, an address generator that generates an address at which the test data is to be written, a test data number counter that counts a number of test data, an error information holder that holds mismatch error information, an error occurrence bit position holder that holds a position of a bit at which a mismatch error has occurred, an error occurrence test data number holder that holds number of test data counted by the test data number counter, and a comparator that compares test data written to the storage device with test data read from the storage device and stores error information in the error information holder and a position of a bit and number of the test data in which the mismatch error has occurred. | 06-03-2010 |
| 20100153795 | METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS - A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults. | 06-17-2010 |
| 20100162058 | SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION - Disclosed herein is a sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes: (1) an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and (2) a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply. | 06-24-2010 |
| 20100162059 | CORE CIRCUIT TEST ARCHITECTURE - A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate. | 06-24-2010 |
| 20100169727 | EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD - There is provided a technique for avoiding test-time IR drops which occur when the frequency that adjacent FFs in a scan chain have different logical values increases. An expected value derivation module derives the expected value of each FF by calculating probability propagation or performing logic simulation. A grouping module groups each FF subject to a test into a number of groups by referring to the obtained expected value. A scan chain configuration module pairs two groups whose logical-value-1 intake frequencies are opposite to each other, performs logic reversal on one group, and configures one scan chain. | 07-01-2010 |
| 20100174956 | Semiconductor integrated circuit and method of saving and restoring internal state of the same - A semiconductor integrated circuit includes a scan chain which includes: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein the first flip-flops and the second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register, and a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of the first flip-flops and read from a memory circuit in a restoring operation in a normal mode to the series connection. The semiconductor integrated circuit further includes a backup control circuit configured to control the scan chain in a saving operation in the normal mode such that the internal state data is stored in the memory circuit without passing through the second flip-flops, in the restoring operation in the normal mode such that the internal state data from the first selecting circuit is set in the first flip-flops without passing through the second flip-flops, and in the scan path test mode such that the test data is shifted in the series connection. | 07-08-2010 |
| 20100180168 | SCAN CHAIN FAIL DIAGNOSTICS - A method comprises generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs). The plurality of faults detected by a first MISR and by a second MISR are identified. In the event the plurality of faults detected by the first MISR does not include any of the plurality of faults detected by the second MISR and the plurality of faults detected by the second MISR does not include any of the plurality of faults detected by the first MISR, the first MISR and the second MISR are coupled as an independent MISR pair. The test pattern is applied to the DUT to generate a scan chain output. The independent MISR pair captures the scan chain output to generate a test signature. The test signature is compared with a known good signature. | 07-15-2010 |
| 20100185908 | Speed-Path Debug Using At-Speed Scan Test Patterns - Speed-path debug techniques based on at-speed scan test patterns. Potential speed paths are identified based upon detected at-speed scan pattern failures and unknown X-value simulation. When the number of identified speed paths is large, the suspect speed paths are ranked. | 07-22-2010 |
| 20100185909 | Asynchronous Scan Chain Circuit - Disclosed is a dual-rail asynchronous insensitive scan chain circuit designed for test. This scan chain does not require any clock even in scan mode, so it is truly an asynchronous design for testability. The normal function of the asynchronous scan chain can not be affected when removing any clock controls. The handshake protocols between two sequential elements used in the asynchronous scan chain become the scan chain transmission structure, rather than the timing control used in synchronous scan chain in the prior arts. Therefore, both in the function mode and scan mode, the scan chain always operates under the asynchronous condition. It not only can reach a complete test scanning, achieve high fault detection coverage and consume lower power, but also avoid the clock skew problem. | 07-22-2010 |
| 20100192030 | METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TEST SOLUTION - Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module. | 07-29-2010 |
| 20100192031 | Tap time division multiplexing with scan test - An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode. | 07-29-2010 |
| 20100223515 | TESTING OF AN INTEGRATED CIRCUIT THAT CONTAINS SECRET INFORMATION - An integrated circuit ( | 09-02-2010 |
| 20100229057 | Semiconductor device test circuit, semiconductor device, and its manufacturing method - The test circuit can apply a stress to each node of each object combinational circuit in the semiconductor device and suppress the semiconductor circuit overhead when in burn-in or leak test operations for the semiconductor device while it has been impossible to apply such a stress to any of such nodes only with use of an F/F circuit in any conventional environments. The test circuit is disposed in the semiconductor and combined with first and second combinational circuits therein. In the semiconductor device, a transfer gate switch is connected between first and second nodes and a first transistor is connected between the second node and a power supply. The second transistor is connected between the second node and a ground. Each of the transfer gate switch and the first and second transistors operates according to at least one of the control signals supplied from outside the semiconductor device. | 09-09-2010 |
| 20100251046 | FAILURE PREDICTION CIRCUIT AND METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT - Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs. | 09-30-2010 |
| 20100251047 | CIRCUIT MODULE, SEMICONDUCTOR INTEGRATED CIRCUIT, AND INSPECTION APPARATUS AND METHOD THEREOF - A circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted. | 09-30-2010 |
| 20100262876 | TEST CIRCUIT AND METHOD FOR TESTING OF INFANT MORTALITY RELATED DEFECTS - The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node. | 10-14-2010 |
| 20100275075 | Deterministic Logic Built-In Self-Test Stimuli Generation - Techniques for storing and using compressed restrict values for selected scan chains and flip-flops, such that the states that need to be applied to those flip flops need not be solved by a linear equation system solver, such as a linear equation system solver provided by an automatic test pattern generation (ATPG) tool. Selected restrict values can then be injected into test patterns for those flip-flop combinations that need to be set in a certain shift cycle or those flip-flops that need to be initialized one after another (e.g., for serial settings in one scan chain). | 10-28-2010 |
| 20100275076 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD FOR THE SAME - A semiconductor integrated circuit includes: a memory; a logic circuit configured to output an address signal for an address of the memory; and an address control circuit connected with the logic circuit and an address terminal of the memory, and configured to receive a test signal to output one of the address signal from the logic circuit and an output signal having a preset logical value to the address terminal of the memory based on the test signal. The test signal indicates one of a user mode in which a transfer delay fault test is not performed and a test mode in which the transfer delay fault test is performed on a path from the logic circuit to the address terminal of the memory. | 10-28-2010 |
| 20100281316 | SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS, OUTPUT DATA DIFFUSION METHOD, AND PROGRAM - A semiconductor integrated circuit includes a scan chain configured to serve as a connection path used for testing the semiconductor integrated circuit and connect a plurality of flip-flops and an interleave circuit provided at an output portion of the scan chain. The interleave circuit includes a plurality of branches including different numbers of stages of storage elements, a selector configured to select one of the plurality of branches serving as an input/output branch that performs input of data from the scan chain and output of data from the interleave circuit, and a selector controller configured to execute a process of switching among the plurality of branches to select the input/output branch at every predetermined timing. | 11-04-2010 |
| 20100281317 | CONTROLLER APPLYING STIMULUS DATA WHILE CONTINUOUSLY RECEIVING SERIAL STIMULUS DATA - An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for transferring serial data between the emulation controller and the emulator. The serial scanning circuitry includes a first state machine having plural states controlling the transfer of serial data. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller. The control circuitry, when connected to the emulation controller, effects the providing and receiving of signals and the transferring of serial data between the emulation controller and the emulator continuously without interruption while the first state machine remains in one state. | 11-04-2010 |
| 20100293422 | Method And System For Scan Chain Diagnosis - Scan chain diagnosis techniques are disclosed. Faulty scan chains are modeled and scan patterns are masked to filter out loading-caused failures. By simulating the masked scan patterns, failing probabilities are determined for cells on a faulty scan chain. One or more defective cells are identified based upon the failing probability information. A noise filtering system such as the one based upon adaptive feedback may be adopted for the identification process. | 11-18-2010 |
| 20100293423 | METHOD AND APPARATUS FOR VIRTUAL IN-CIRCUIT EMULATION - A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches). The Virtual ICE Driver is configured for receiving a plurality of scan segment operations generated by a plurality of target ICE controllers of at least one ICE host, scheduling the received scan segment operations, based at least in part on a scan chain of the target hardware, to form thereby a scheduled set of scan segment operations, and providing the scheduled set of scan segment operations to a processor configured for executing the scheduled set of scan segment operations for testing the target hardware. | 11-18-2010 |
| 20100299566 | DEBUGGING MODULE FOR ELECTRONIC DEVICE AND METHOD THEREOF - A debugging module for connecting an IC to a JTAG debugger device includes a JTAG interface, an earphone circuit, a USB interface, a switching unit, and a reset circuit. The earphone circuit is electrically connected to the JTAG interface via the switching unit. The USB interface and the reset circuit are electrically connected to the JTAG interface. When a JTAG debugger device is connected to the earphone circuit and the USB interface, the earphone circuit and the USB interface, respectively, can establish a connection between the JTAG debugger device and the JTAG interface. | 11-25-2010 |
| 20100299567 | On-Chip Logic To Support Compressed X-Masking For BIST - Techniques are provided for X-masking using at least some masking information provided by on-chip logic, in lieu of masking information provided from off of the integrated circuit being tested. The masking information is provided by a masking information source on the integrated circuit being tested, such as, for example, a read-only memory (ROM) circuit, that feeds the masking information to the X-masking logic. With these implementations of the invention, it is possible to perform X-masking independent from any external data, thus enabling X-masking for a logic built-in self-test without requiring an external testing device. | 11-25-2010 |
| 20100306606 | COMPACTOR INDEPENDENT DIRECT DIAGNOSIS OF TEST HARDWARE - Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided. | 12-02-2010 |
| 20100306607 | Semiconductor integrated circuit and method of testing the same - A semiconductor integrated circuit includes: a plurality of scan flip-flops configured to form a scan chain in a scan test; and a plurality of clock gating circuits connected between a clock input and corresponding portions of the plurality of scan flip-flops, respectively. The plurality of clock gating circuits are connected in serial to form a chain and gating setting data is inputted in serial through the chain connection. Each of the plurality of clock gating circuits controls a connection between the clock input and a corresponding portion of the plurality of scan flip-flops based on the gating setting data. | 12-02-2010 |
| 20100318862 | SCAN TEST CIRCUIT, AND METHOD AND PROGRAM FOR DESIGNING SAME - Flip-flops | 12-16-2010 |
| 20100318863 | PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES - The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure. | 12-16-2010 |
| 20100318864 | Fault location estimation device, fault location estimation method, and program - A fault location estimation device includes: a faulty scan chain identification unit that identifies a faulty scan chain and its fault type based on result of operation verification test; a faulty scan FF narrowing unit that compares test result of the faulty scan chain with simulation result for determining a faulty scan FF range beginning at the location of a scan FF where both results differ; and a path trace narrowing unit that references logic circuit configuration information, signal line expected value, a failure-observed scan FF, and test result of a defective circuit to extract a scan FF on the faulty scan chain, which may be reached from a failure-observed scan FF observed on a normal scan chain by tracing back a failure propagation path while performing implication procedure for an input side, and thereby further narrows the faulty scan FF range determined by the faulty scan FF narrowing unit. | 12-16-2010 |
| 20110016364 | SCAN-ENABLED METHOD AND SYSTEM FOR TESTING A SYSTEM-ON-CHIP - Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each core includes input ports and output ports. The method also includes selecting flip-flops for each port if the slack does not exceed a slack threshold. Further, the method includes integrating a wrapper cell to each port for which the slack exceeds the slack threshold. Moreover, the method includes coupling integrated wrapper cells and selected flip-flops corresponding to the input ports to form at least one input scan chain for the core, and corresponding to the output ports to form at least one output scan chain for the core. The method also includes testing the SoC using the at least one input scan chain and the at least one output scan chain of each core. | 01-20-2011 |
| 20110022908 | ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS - A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level. | 01-27-2011 |
| 20110022909 | APPARATUS AND METHOD FOR PROTECTING SOFT ERRORS - An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance. | 01-27-2011 |
| 20110035638 | Timing Failure Debug - A debug flow that uses debug-friendly test patterns and logic fault diagnosis techniques to help physical fault isolation of timing failures. | 02-10-2011 |
| 20110041018 | MULTI-MODE PROGRAMMABLE SCAN FLOP - A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input, and a data output, a scan flop having a scan data input and a scan data output, and a latch circuit coupled between the functional flop and the scan flop. The latch circuit includes one or more mode signal inputs to enable selection of an operating mode. In a first mode, the latch circuit is configured to enable the functional flop to provide a data signal to the scan flop. In a second mode, the latch circuit is configured to enable the scan flop to provide a data signal to the functional flop. In a third mode, the latch circuit is configured to provide a feedback path in order to feed back to the functional flop a signal generated by the functional flop. | 02-17-2011 |
| 20110041019 | SCAN TESTING SYSTEM, METHOD AND APPARATUS - Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. | 02-17-2011 |
| 20110047425 | On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis - On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature. | 02-24-2011 |
| 20110066904 | AVOIDING RACE CONDITIONS AT CLOCK DOMAIN CROSSINGS IN AN EDGE BASED SCAN DESIGN - A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the computer) by only observing latches that receive signals from sources within the clock domains. The structure, system, and method also unblock the clock inputs to the clock domains (using the computer). While the clock domain inputs are unblocked, the structure, system, and method perform a second timing test only of signals that are transmitted between the clock domains by only observing latches that receive signals from other clock domains. | 03-17-2011 |
| 20110066905 | Test Pin Gating for Dynamic Optimization - An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced. | 03-17-2011 |
| 20110072324 | METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits. | 03-24-2011 |
| 20110078523 | OUTPUT CONTROL SCAN FLIP-FLOP, SCAN TEST CIRCUIT USING THE SAME, AND TEST DESIGN METHOD - An output control scan flip-flop according to an exemplary aspect of the present invention can control an output value to be held and inverted irrespective of an input value. The output control scan flip-flop includes a scan flip-flop; a storage element that operates in synchronization with a clock signal and stores first input data externally supplied; an exclusive-OR logic circuit that receives an output signal from the storage element and an output signal from the scan flip-flop; and a selector that receives second input date externally supplied, an output signal from the exclusive-OR logic circuit, and a select signal externally supplied, and supplies an output signal to the scan flip-flop. | 03-31-2011 |
| 20110087937 | CORE CIRCUIT TEST ARCHITECTURE - A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate. | 04-14-2011 |
| 20110099440 | SYSTEMS AND METHODS FOR MEASURING SOFT ERRORS AND SOFT ERROR RATES IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT - A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains application software that when executed by the computer quantifies soft errors and soft error rates (SER) in storage elements on the ASIC. The interface device receives commands and data from the computer, translates the commands and data from a first protocol to a second protocol and communicates the commands and data in the second protocol to the ASIC. A method for measuring SER in the ASIC includes baseline, comparison, and latch up accesses of data in a scan chain in the ASIC. Between accesses, the ASIC is exposed to a neutron flux that accelerates the occurrence of soft errors due to ionizing radiation upon the ASIC. | 04-28-2011 |
| 20110113297 | DISTRIBUTED JOINT TEST ACCESS GROUP TEST BUS CONTROLLER ARCHITECTURE - Apparatus and other embodiments associated with a distributed Joint Test Access Group (JTAG) test bus controller (TBC) architecture are described. One example method includes providing first on-board scan programming (OSP) data to a first circuit board configured with a first TBC and located in a computer. The example method also includes providing second OSP data to a second circuit board configured with a second test bus controller and located in the same computer. The example method also includes controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board. | 05-12-2011 |
| 20110119540 | OPTIMIZING JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 05-19-2011 |
| 20110119541 | BDX DATA IN STABLE STATES - A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while the test access port remains in a predefined state. The predefined state comprises a state in which no scans occur. | 05-19-2011 |
| 20110126064 | ENHANCED DIAGNOSIS WITH LIMITED FAILURE CYCLES - Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data. | 05-26-2011 |
| 20110154139 | COMPUTER PRODUCT AND APPARATUS FOR FAILURE DIAGNOSIS SUPPORT - A recording medium stores a program causing a computer to execute determining, for each test pattern measuring operation frequency of a circuit and based on a predicted delay of each path in the circuit, a path candidate determining a measured value obtained via the test pattern and activated by the test pattern; building, for each test pattern yielding a measured value determined by a given path candidate determined at the determining, a model equation expressing discrepancy between the measured value obtained via the test pattern and the predicted delay of the given path candidate, the model equation including parameters representing effects of each path activated by the test pattern on the discrepancy; calculating values of the parameters by using the model equations; determining based on the calculated values, a path determining the measured value obtained via the test pattern and activated by the test pattern; and outputting the determined path. | 06-23-2011 |
| 20110161756 | INTEGRATED CIRCUIT AND DIAGNOSIS CIRCUIT - A integrated circuit include: a first selection circuit selecting first data from input-data or scan-data, scan-data being for performing a diagnosis of a combinational circuit, input-data being received from a combinational circuit; a first latch circuit holding first data as first output-data in accordance with a first signal; a second latch circuit holding first output-data as second output-data in accordance with which of the first signal and a second signal, the second signal being used to force the second latch circuit to hold first output-data; a third latch circuit holding first output-data as third output-data in accordance with which of the first signal and a third signal, the third signal being used to force the third latch circuit to hold first output-data; and a second selection circuit selecting second data from among the data which include second output-data and third output-data. | 06-30-2011 |
| 20110167309 | DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS - A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns. | 07-07-2011 |
| 20110202803 | METHOD FOR TESTING AN ADDRESS BUS IN A LOGIC MODULE - A method for testing an address bus ( | 08-18-2011 |
| 20110202804 | Circuit And Method For Simultaneously Measuring Multiple Changes In Delay - A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple paths, and may be implemented in digital boundary scan to test I/O pin delays. Synchronous to a first frequency, the circuit applies an alternating signal to the paths and samples the paths' output logic values synchronous with a second frequency that is asynchronous and coherent to the first clock frequency. The shift register conveys the samples to a modulo counter that counts the number of samples between consecutive rising or consecutive falling edges in the signal samples from a selected path. Between the two edges, the path or a path characteristic is changed, and the resulting modulo count after the second edge is proportional to the change in delay. The circuit can compare the count, or the difference between counts, to test limits. | 08-18-2011 |
| 20110202805 | Pulse Dynamic Logic Gates With Mux-D Scan Functionality - A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The resultant state of the dynamic node may be stored within an output storage element. When the evaluate pulse is deasserted, the dynamic node may be precharged. During a scan mode of operation, the dynamic node may remain precharged. Scan data may be transferred to the output storage element under the control of scan-related control signals. | 08-18-2011 |
| 20110202806 | TAM CONTROLLER CONNECTED WITH TAM AND FUNCTIONAL CORE WRAPPER CIRCUIT - A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed. | 08-18-2011 |
| 20110202807 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 08-18-2011 |
| 20110209013 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 08-25-2011 |
| 20110214026 | CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES - A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. | 09-01-2011 |
| 20110219277 | System and Method of Test Mode Gate Operation - A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a method includes, after a layout phase of generating a design of a circuit, receiving timing information related to the design of the circuit. The method also includes selectively identifying at least one gate of a combinational logic portion of the design of the circuit to be modified to respond to a test enable signal, the at least one gate identified at least partially based on the timing information. The method also includes modifying the at least one gate. The at least one modified gate is fixed at a constant level during a test mode and is dynamically changeable during a functional mode of operation of the circuit. | 09-08-2011 |
| 20110239067 | VERIFICATION OF DESIGN INFORMATION FOR CONTROLLING MANUFACTURE OF A SYSTEM ON A CHIP - A system on a chip comprises a plurality of circuit blocks ( | 09-29-2011 |
| 20110258498 | Test Architecture Including Cyclical Cache Chains, Selective Bypass Scan Chain Segments, And Blocking Circuitry - A test architecture is described that adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values. | 10-20-2011 |
| 20110258499 | SYSTEM FOR PERFORMING THE TEST OF DIGITAL CIRCUITS - A system performs the test of a digital circuit. The system comprises a controller configured for executing the test of the digital circuit, a memory configured for storing a status of the digital circuit, and a state machine configured for controlling, before the execution of the test, the storage into the memory of the status of the digital circuit and configured for controlling, after the execution of the test, the restore into the digital circuit of the status stored into the memory. | 10-20-2011 |
| 20110258500 | ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 10-20-2011 |
| 20110258501 | METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION - A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step. | 10-20-2011 |
| 20110289369 | INTEGRATED CIRCUIT FOR COMPRESSION MODE SCAN TEST - An integrated circuit for performing a design for testability (DFT) scan test is provided. The integrated circuit includes at least one scan chain including a plurality of flip-flops, at least one interface scan chain including a plurality of flip-flops, a decompressor configured to be connected with an input terminal of the at least one interface scan chain and to decompress a first input signal and then transmit it to the at least one scan chain, a compressor configured to be connected with an output terminal of the at least one scan chain and to compress an output signal of the at least one scan chain, and at least one multiplexer configured to be connected with the decompressor and to selectively output an output signal of the decompressor or a second input signal in response to a control signal. | 11-24-2011 |
| 20110296262 | Scan driver and display device using the same - A scan driver includes a first decoder generating a plurality of output signals through a plurality of first logic gates, and a second decoder including a plurality of first logic circuits connected to a first terminal of a plurality of scan lines and a plurality of second logic circuits connected to a second terminal of the plurality of scan lines. The plurality of first logic circuits supply a source current to a corresponding scan line according to the corresponding output signal among the plurality of output signals. The plurality of second logic circuits sinks a sink current to the corresponding scan line according to the corresponding output signal among the plurality of output signals. | 12-01-2011 |
| 20110296263 | SEMICONDUCTOR TEST SYSTEM AND METHOD - A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test. | 12-01-2011 |
| 20110307748 | TECHNIQUES FOR ERROR DIAGNOSIS IN VLSI SYSTEMS - Techniques for designing and storing test input and output data vectors to diagnose bit errors in a testing sequence. In an aspect, test input vectors may be chosen such that the corresponding correct output vectors form codewords of a forward error-correcting code. In another aspect, the correct test output vectors may be compressed to reduce the memory requirements of the testing system. In yet another aspect, test input vectors may be sorted such that the test output vectors are monotonically increasing or decreasing in sequence, and corresponding delta's between output vectors in the sequence may be stored to reduce the memory requirements. Further aspects provide for storing information relating to the correct output vectors in various efficient formats, including storing base value-referenced offsets, and storing relative operations and output vector segments to allow derivation of correct output vectors from memory when required. | 12-15-2011 |
| 20110320896 | Integrated Circuit Devices Having Selectively Enabled Scan Paths With Power Saving Circuitry - An integrated circuit device includes first and second latches (e.g, D-type flip flops) responsive to a clock signal. Each of the first and second latches respectively includes a data input terminal, a scan input terminal, a scan enable terminal and an output terminal. A combinational logic circuit may be provided, which is configured to receive the signal from the output terminal of the first latch and configured to generate a signal at the data input terminal of the second latch. A scan path is also provided, which is responsive to a scan enable signal. The scan path is configured to selectively pass a signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is active. A power saving switch is also provided. This switch, which is responsive to the scan enable signal, includes a first current carrying terminal electrically coupled to the scan path. The switch is configured to disable the scan path from passing the signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is in an inactive state. | 12-29-2011 |
| 20120030532 | STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING - A scannable integrated circuit ( | 02-02-2012 |
| 20120079332 | DEVICE FOR SECURING A JTAG TYPE BUS - A device to secure a JTAG type bus in its “scan chain” component chaining mode functionality, when several components are connected in series on the JTAG bus, includes a first interface for receiving JTAG signals and a second interface for the JTAG signals originating from a chain of components. The device includes the following modules: a JTAG frame generator module for verifying the continuity of operation of said Bus and components; a module for monitoring the electrical activity of said Bus and components; an alarm module for sending back an alarm detected by the above modules; an alarm module for managing the operating mode of the device; and a security functions activation module AFS. | 03-29-2012 |
| 20120079333 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 03-29-2012 |
| 20120084613 | SCAN RESPONSE REUSE METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure. | 04-05-2012 |
| 20120117434 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 05-10-2012 |
| 20120124434 | CONFIGURABLE MUX-D SCAN FLIP-FLOP DESIGN - A method, computer program storage device and apparatus are provided for flexible observability during a scan. In one aspect of the present invention, a method is provided. The method includes providing a selector load input to at least a portion of a scan chain, selecting an observe-only scan mode for the at least a portion of the scan chain based at least upon the selector load input, and providing a data input to a storage element in the scan chain based at least upon the observe-only scan mode. The apparatus includes a first scan chain multiplexor comprising a selector input, a first input terminal, a second input terminal and an output terminal. The apparatus also includes a first scan chain storage element comprising an input terminal and an output terminal, where the input terminal of the first scan chain storage element is communicatively coupled to the output terminal of the first scan chain multiplexor. The apparatus further recites that the output terminal of the first scan chain storage element is communicatively coupled to the first input terminal of the first scan chain multiplexor. The computer program storage device adapts a manufacturing facility to create the apparatus. | 05-17-2012 |
| 20120124435 | AVOIDING BIST AND MBIST INTRUSION LOGIC IN CRITICAL TIMING PATHS - Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths. | 05-17-2012 |
| 20120124436 | SEMICONDUCTOR MEMORY DEVICE PERFORMING PARALLEL TEST OPERATION - A semiconductor memory device includes: first test circuits each of which operates in a first test mode in which the first test circuit receives a plurality of comparison result signals each indicating a comparison result of storage contents of a plurality of memory cells included in a memory cell array in parallel and generates a first output signal by converting the comparison result signals into serial signals or a second test mode in which the first test circuit generates a second output signal by compressing the data amount of the plurality of comparison result signals. Each of the first test circuits outputs the first and second output signals to a common bus. | 05-17-2012 |
| 20120124437 | INTEGRATED CIRCUIT HAVING A SCAN CHAIN AND TESTING METHOD FOR A CHIP - An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group. | 05-17-2012 |
| 20120131402 | TEST MODE SETTING CIRCUIT - Provided is a test mode setting circuit with a smaller number of terminals. A detector having a low threshold voltage and a detector having a high threshold voltage are provided to a test terminal for controlling a test mode of a semiconductor device, and the detector having the low threshold voltage releases a reset of a logic circuit while the detector having the high threshold voltage controls switching of the test mode. This configuration uses the test terminal, a reset terminal, and test mode control terminals in common between a normal state and a test state, thus reducing a large number of the terminals. | 05-24-2012 |
| 20120166899 | FAULT TOLERANT SCANNABLE GLITCH LATCH - A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault. | 06-28-2012 |
| 20120166900 | TESTING CIRCUITS - A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit. | 06-28-2012 |
| 20120166901 | INTEGRATED CIRCUIT FOR TESTING SMART CARD AND DRIVING METHOD OF THE CIRCUIT - An integrated circuit (IC) is provided. The IC includes a scan controller and a target logic circuit configured to receive a scan input pattern in response to a control of the scan controller, to execute an operation according to the scan input pattern, and to output an execution result. The scan controller compares the execution result with a scan output pattern and outputs a comparison result. The IC can perform a scan test on a particular block that is not controlled by a CPU in a smart card without an additional pad. | 06-28-2012 |
| 20120173938 | SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA - A scan cell includes first, second and third data inputs and a control input. The first, second and third data inputs are configured to receive respective first, second and third data bits. The control input is configured to receive a control signal. Latching logic is configured to latch an input value to a scan cell output. Selection logic is configured to select the input value from between the first, second and third data bits, depending on a state of the control signal. | 07-05-2012 |
| 20120173939 | SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA - A scan cell is configured to receive first, second and third data bits at respective first, second and third data inputs. A control input is configured to receive a control signal. Latching logic is configured to latch data received at the first and second latch inputs to a scan cell output. The first latch input is configured to receive the first data bit. Selection logic is configured to select between the second and third data bits depending on a state of the control signal, and to provide the selected bit to the second latch input. | 07-05-2012 |
| 20120173940 | ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS - A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level. | 07-05-2012 |
| 20120204072 | LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS - Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures. | 08-09-2012 |
| 20120210181 | SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST - Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon. | 08-16-2012 |
| 20120216087 | CORE CIRCUIT TEST ARCHITECTURE - A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate. | 08-23-2012 |
| 20120216088 | GENERATING TEST SETS FOR DIAGNOSING SCAN CHAIN FAILURES - Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell. | 08-23-2012 |
| 20120226952 | AUTOMATIC IDENTIFICATION OF INFORMATION USEFUL FOR GENERATION-BASED FUNCTIONAL VERIFICATION - a computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes. | 09-06-2012 |
| 20120226953 | SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN APPARATUS AND DESIGN METHOD - A semiconductor integrated circuit has one or more of scan chains each having series-connected flip-flops that exist in an internal circuit. Each scan chain is divided into a plurality of segments. Each segment is controllable a timing of a clock signal. The semiconductor integrated circuit has a clock gating circuit capable of being shared by the scan chains and configured to generate a plurality of clock signals for driving each segment, the clock gating circuit being provided for each scan chain, and a segment control signal generator configured to generate a control signal to be used when the clock gating circuit generates the clock signals so that an effect of a fault of the internal circuit is transferred through one of the segments and care bits corresponding to a next fault are captured in a corresponding segment. | 09-06-2012 |
| 20120233511 | SEMICONDUCTOR DEVICE AND TEST SYSTEM FOR TESTING THE SAME - A semiconductor device includes a test pattern decoding unit and a scan chain unit. The test pattern receives a scan-in pattern from an external test device and generates a test pattern based on the scan-in pattern and a scan-out pattern. The scan-in pattern is decoded based on a seed pattern and an expectation pattern. The scan chain unit performs logical operation based on the test pattern and feedbacks the scan-out pattern to the test pattern decoding unit. | 09-13-2012 |
| 20120246528 | Circuit for Securing Scan Chain Data - Methods, devices and circuits are provided for protecting secure data from being read during a scan chain output. A plurality of scan flip-flops is coupled in a scan chain, and an input circuit is configured to shift input data to the scan flip-flops. A protection circuit is coupled to the scan flip-flops, and the protection circuit configured to detect scan-in of data from the input circuit to a designated one of the scan flip-flops. Scan-out of data from the designated scan flip-flop is enabled in response to detection of a scan-in of data from the input circuit to the designated scan flip-flop. Scan-out of data from the designated scan flip-flop is prevented in response to no detection of scan-in of data from the input circuit to the designated scan flip-flop. | 09-27-2012 |
| 20120246529 | LOW-POWER AND AREA-EFFICIENT SCAN CELL FOR INTEGRATED CIRCUIT TESTING - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation. | 09-27-2012 |
| 20120272110 | Test Generator For Low Power Built-In Self-Test - Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains. | 10-25-2012 |
| 20120278671 | CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES - A method includes shifting a first logic sequence into a first scan chain having a first plurality of scan blocks coupled together, outputting a second logic sequence from each of the plurality of scan blocks in the first scan chain to a respective scan block in a second scan chain, and shifting a third logic sequence out of the second scan chain. At least one improperly functioning scan block of the first scan chain is identified based on the third logic sequence shifted out of the second scan chain. | 11-01-2012 |
| 20120278672 | ARCHITECTURE, SYSTEM, METHOD, AND COMPUTER-ACCESSIBLE MEDIUM FOR TOGGLE-BASED MASKING - Exemplary embodiments of the present disclosure include apparatus, methods, and computer-accessible medium for a toggle-masking procedure configured to mask, e.g., most or all the unknown x's and minimizing the over-masked known bits for clustered distribution of unknown bits. According to certain exemplary embodiments, it is possible to obtain previous masking information regarding the scan chain(s) associated with a previous cycle, and mask the scan chain(s) for a present cycle based on the previous masking information. | 11-01-2012 |
| 20120284577 | ARCHITECTURE, SYSTEM, METHOD, AND COMPUTER-ACCESSIBLE MEDIUM FOR ELIMINATING SCAN PERFORMANCE PENALTY - Exemplary apparatus, methods, and computer-accessible medium can be provided for transforming a circuit. For example, it is possible to select, from the circuit, at least one scan cell which includes a first multiplexer coupled to a first flip-flop. A second flip-flop and a second multiplexer can be inserted in the circuit. The first multiplexer can be coupled as an input to the second flip-flop, and the second multiplexer can be coupled to the output of the first flip-flop and the second flip-flop. | 11-08-2012 |
| 20120297259 | SOFT ERROR RATE DETECTOR - The soft error rate (SER) detector circuit presented here can be used to measure SER in combinatorial logic devices caused by radiation. The SER detector circuit includes a plurality of detector arrays coupled in series, and each having a plurality of SER test structures coupled in series. Each of the SER test structures includes a plurality of detector elements coupled in series. Each of the SER test structures is configured to detect single event transients (SETs) in a first operating mode and single event upsets (SEUs) in a second operating mode. The SER detector circuit also has control logic elements to control operation of the plurality of detector arrays. | 11-22-2012 |
| 20120297260 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 11-22-2012 |
| 20120304028 | SCAN RESPONSE REUSE METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure. | 11-29-2012 |
| 20120317450 | SEMICONDUCTOR DEVICE - A semiconductor device, comprising: a user circuit having a plurality of flip-flops; and a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, wherein the connection path has a logic operation circuit which performs a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, or, an inverted value connection path which outputs to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops. | 12-13-2012 |
| 20120317451 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 12-13-2012 |
| 20120331358 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF RETRIEVING SIGNAL TO SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit is configured so that a transition scan test can be performed thereon. The semiconductor integrated circuit includes a plurality of logic circuit blocks having different operation frequencies; a clock supply unit for supplying a plurality of clock signals having frequencies corresponding to the operation frequencies of the logic circuit blocks from a clock supply source; a compression scan circuit including a plurality of scan chains formed of a plurality of flip-flop circuits, a pattern deployment circuit connected to the scan chains on an input side thereof, and a pattern compression circuit; and a clock control unit for controlling the clock supply unit to stop supplying the clock signals to specific ones of the flip-flop circuits of the scan chains when a capture operation is performed during a transition scan test. | 12-27-2012 |
| 20130007546 | INTEGRATED CIRCUIT TEST OPTIMIZATION USING ADAPTIVE TEST PATTERN SAMPLING ALGORITHM - A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips. | 01-03-2013 |
| 20130007547 | EFFICIENT WRAPPER CELL DESIGN FOR SCAN TESTING OF INTEGRATED CIRCUITS - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip. | 01-03-2013 |
| 20130019134 | APPARATUS AND METHOD FOR DESIGNING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICEAANM IWATA; HiroyukiAACI KanagawaAACO JPAAGP IWATA; Hiroyuki Kanagawa JPAANM MATSUSHIMA; JunAACI KanagawaAACO JPAAGP MATSUSHIMA; Jun Kanagawa JP - An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced. | 01-17-2013 |
| 20130031433 | METHOD FOR PARTITIONING SCAN CHAIN - A system and method for scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device is provided. One or more scan partitions in the embedded logic circuit are identified. Each scan partition includes one or more scan chains of scan registers. One or more interacting registers connecting scan registers of a first scan partition and scan registers of a second scan partition are identified and combined to form an interacting scan chain. The embedded logic circuit is tested by selectively activating the scan chains of the first and second scan partitions and the interacting scan chain. | 01-31-2013 |
| 20130031434 | SCAN TEST CIRCUIT WITH SCAN CLOCK - A scan test circuit includes: a functional path, including: a D-type latch, for receiving an input and generating an output, the D-type latch including a feedback node; and a test path, including: a scan latch, for receiving a test input and generating an output. The scan test circuit also includes a tri-state inverter. The output of the test path is input to the feedback node of the D-type latch and also input to the tri-state inverter. The functional path is clocked by pulses generated by a pulse generator according to a system clock. The test path is clocked by a test clock generated according to a test enable signal and the system clock. When the test enable signal is enabled, the generation of the pulses is disabled. | 01-31-2013 |
| 20130036337 | Clock Control of Pipelined Memory for Improved Delay Fault Testing - In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank. | 02-07-2013 |
| 20130042158 | SCAN FLIP-FLOP CIRCUIT HAVING FAST SETUP TIME - A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode. | 02-14-2013 |
| 20130055040 | OUTPUT CONTROL SCAN FLIP-FLOP, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME, AND DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - An output control scan flip-flop according to the present invention includes a first scan flip-flop that captures first data in a first mode and second data in a second mode in synchronization with a clock signal to output the data that is captured, a second scan flip-flop that captures the data output from the first scan flip-flop in the second mode in synchronization with a clock signal to output the data that is captured, and a gating circuit that generates the data output from the first scan flip-flop in the first mode as output data, and generates output data having a change rate of a logic value lower than a change rate of a logic value of the data output from the first scan flip-flop based on the data output from each of the first scan flip-flop and the second scan flip-flop in the second mode. | 02-28-2013 |
| 20130061103 | Scan Chain Fault Diagnosis - Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell. | 03-07-2013 |
| 20130067290 | INTEGRATED CIRCUIT WITH TRANSITION CONTROL CIRCUITRY FOR LIMITING SCAN TEST SIGNAL TRANSITIONS DURING SCAN TESTING - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises transition control circuitry configured to detect transitions between binary logic levels in a scan test signal, and responsive to a number of detected transitions reaching a threshold, to limit further transitions associated with a remaining portion of the scan test signal. In an illustrative embodiment, the transition control circuitry limits further transitions associated with the remaining portion of the scan test signal by replacing at least part of the remaining portion of the scan test signal with a limited transition signal. The limited transition signal may be maintained at a constant binary logic level such that it has no transitions. By limiting the number of transitions associated with the scan test signal, the transition control circuitry serves to reduce integrated circuit power consumption during scan testing. | 03-14-2013 |
| 20130080848 | SYSTEM AND METHOD OF TEST MODE GATE OPERATION - A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a circuit includes a combinational logic portion including a logic path including a test isolation gate between a starting element and an ending element. The logic path includes at least a first gate element between the starting element and the test isolation gate. The logic path also includes at least a second gate element between the test isolation gate and the ending element. The starting element and the ending element are coupled to be tested via a scan chain test process during a test mode. In the test mode, an output of the second gate element is fixed at a constant logic level. | 03-28-2013 |
| 20130080849 | TEST PATTERN GENERATION FOR DIAGNOSING SCAN CHAIN FAILURES - Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. At least some embodiments can be used to locate faults over multiple capture cycles in the scan chain. | 03-28-2013 |
| 20130091395 | CIRCUIT TO REDUCE PEAK POWER DURING TRANSITION FAULT TESTING OF INTEGRATED CIRCUIT - A circuit for reducing peak power during transition fault testing of an integrated circuit (IC) includes a programmable register that receives scan shift and SDI (scan data in) signals. Input and output ports of the programmable register are connected together. A multiplexer is provided that has a first input port that is maintained asserted, and a second input port connected to the output port of the programmable register. A scan shift signal, which remains asserted during a scan shift operation and de-asserted during a scan capture operation, is provided at a select input port of the multiplexer. The output of the multiplexer is provided as an input to a clock gating cell. The clock gating cell selectively provides the clock signal to the scan-chain flip-flops in the IC based on the scan shift signal and a functional enable signal, and reduces peak power during transition fault testing. | 04-11-2013 |
| 20130103994 | DYNAMIC CLOCK DOMAIN BYPASS FOR SCAN CHAINS - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode. By selectively bypassing portions of the scan chain associated with particular clock domains, the clock domain bypass circuitry serves to reduce test time and power consumption during scan testing. | 04-25-2013 |
| 20130111285 | SCAN TEST CIRCUITRY COMPRISING SCAN CELLS WITH FUNCTIONAL OUTPUT MULTIPLEXING | 05-02-2013 |
| 20130111286 | SCAN ENABLE TIMING CONTROL FOR TESTING OF SCAN CELLS | 05-02-2013 |
| 20130117618 | SCAN TESTING OF INTEGRATED CIRCUIT WITH CLOCK GATING CELLS - An integrated circuit includes a set of cells for operation in a functional mode and in a scan testing mode, and a spare cell. The cells are connected in a scan chain with scan data inputs connected to the outputs of preceding cells in the scan chain and respond to assertion of a scan enable signal. A clock gating element applies a functional clock signal to clock inputs of the cells in response to a gating enable signal in functional mode and a test clock signal in response to a test mode signal in scan testing mode. A functional data input of the spare cell latches the gating enable signal during the scan testing mode in response to de-assertion of the scan enable signal. The output of the spare cell is connected to the scan data input of one of the cells in response to the scan enable signal. | 05-09-2013 |
| 20130117619 | LOGIC CORRUPTION VERIFICATION - A computer-implemented method of verifying logic in a simulation-based behavioral latch model by performing actions including: inserting a value checking module in the behavioral latch model, the value checking module connected to one of a set of latches outside of a scan chain within the behavioral latch model; comparing a value of the one of the set of latches outside of the scan chain with a delta value for the one of the set of latches outside of the scan chain; and providing an error message in response to determining the value and the delta value are distinct. | 05-09-2013 |
| 20130139013 | LOW LEAKAGE CURRENT OPERATION OF INTEGRATED CIRCUIT USING SCAN CHAIN - An integrated circuit (IC) having a low leakage current mode of operation has a number of modules for running respective applications. The modules have respective cells and respective test scan chain elements. The IC also has a controller for configuring an active module to operate in a functional mode and a selected inactive module to operate in a low leakage current mode. Configuring the selected inactive module to operate in low leakage current mode includes enabling scan mode of the selected inactive module, and applying a low leakage vector of input signals from the controller to the cells of the inactive module using the scan chain. Functional data outputs of the inactive module are disabled during low leakage current mode. In the meantime, the active modules continue to operate in the functional mode. | 05-30-2013 |
| 20130151915 | EFFICIENCY OF COMPRESSION OF DATA PAGES - A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied. | 06-13-2013 |
| 20130159799 | MULTI-CORE PROCESSOR WITH INTERNAL VOTING-BASED BUILT IN SELF TEST (BIST) - A method and circuit arrangement utilize scan logic disposed on a multi-core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing. | 06-20-2013 |
| 20130173976 | Scan Test Circuitry with Delay Defect Bypass Functionality - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift configuration of the scan cells responsive to a delay defect associated with that scan cell. A delay defect bypass controller may be used to generate a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed. | 07-04-2013 |
| 20130173977 | HIGH DENSITY FLIP-FLOP WITH ASYNCHRONOUS RESET - A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted. | 07-04-2013 |
| 20130179742 | SCAN CHAIN LOCKUP LATCH WITH DATA INPUT CONTROL RESPONSIVE TO SCAN ENABLE SIGNAL - A scan chain lockup latch comprises at least one latching element and data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal. The lockup latch is configured for coupling between first and second scan cells of a scan chain. The scan chain may be controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal. The data input control circuitry may be configured to maintain the data input of the latching element at a constant logic value when the scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed. The scan chain lockup latch and the associated scan chain may be implemented in scan test circuitry of an integrated circuit, for testing additional circuitry of that integrated circuit. | 07-11-2013 |
| 20130185607 | SCAN TEST CIRCUITRY CONFIGURED FOR BYPASSING SELECTED SEGMENTS OF A MULTI-SEGMENT SCAN CHAIN - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller. | 07-18-2013 |
| 20130219236 | Controlling Scan Access to a Scan Chain - A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied. | 08-22-2013 |
| 20130246869 | ENHANCED DIAGNOSIS WITH LIMITED FAILURE CYCLES - Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data. | 09-19-2013 |
| 20130246870 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed. | 09-19-2013 |
| 20130262943 | OPTIMIZED SYNCHRONOUS SCAN FLIP FLOP CIRCUIT - According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input. | 10-03-2013 |
| 20130275824 | SCAN-BASED CAPTURE AND SHIFT OF INTERFACE FUNCTIONAL SIGNAL VALUES IN CONJUNCTION WITH BUILT-IN SELF-TEST - An integrated circuit comprises a memory or other type of circuit core having an input interface and an output interface, built-in self-test circuitry configured for testing of the circuit core between its input and output interfaces in a built-in self-test mode of operation, and at least one scan chain having a plurality of scan cells. The scan cells of the scan chain are coupled to respective signal lines at the input and output interfaces and configured to allow capture of functional signal values from those signal lines in a functional mode of operation and shifting out of the captured functional signal values in a scan shift mode of operation. This allows detection of faults associated with functional paths of the interface that would otherwise not be detectable using the built-in self-test circuitry. | 10-17-2013 |
| 20130275825 | SEMICONDUCTOR TEST SYSTEM AND METHOD - A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test. | 10-17-2013 |
| 20130297980 | Method of Diagnosable Scan Chain - Embodiments of the present invention relate to a method and apparatus for diagnosing a scan chain. Specifically, a method for a scan chain according to one embodiment of the present invention comprises: obtaining an initial structure of the scan chain; determining at least one scan register pair with backward dependency, according to function modules corresponding to scan registers on the scan chain; and adjusting the structure of the scan chain such that the at least one scan register pair with backward dependency becomes a scan register pair with forward dependency. By means of the solution according to embodiments of the present invention, the diagnosability of a scan chain may be enhanced. | 11-07-2013 |
| 20130305106 | INTEGRATED CIRCUITS CAPABLE OF GENERATING TEST MODE CONTROL SIGNALS FOR SCAN TESTS - Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern. | 11-14-2013 |
| 20130305107 | ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES - Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits. | 11-14-2013 |
| 20130318409 | CORE CIRCUIT TEST ARCHITECTURE - A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate. | 11-28-2013 |
| 20140013173 | Apparatus and Method for Clock Glitch Detection During At-Speed Testing - A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test. | 01-09-2014 |
| 20140032985 | SCAN TEST CIRCUITRY CONFIGURED TO PREVENT CAPTURE OF POTENTIALLY NON-DETERMINISTIC VALUES - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent the scan cell from capturing a potentially non-deterministic value from a portion of the additional circuitry. The portion of the additional circuitry that provides the potentially non-deterministic value may comprise, for example, at least one of a mixed signal logic block and a memory block of the additional circuitry. The given scan cell may be controlled by configuring the scan cell such that it is unable to capture data in a scan capture mode of operation in which it would otherwise normally be able to capture data. | 01-30-2014 |
| 20140047292 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 02-13-2014 |
| 20140059399 | TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES - Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design. | 02-27-2014 |
| 20140075254 | SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS - Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation. | 03-13-2014 |
| 20140122949 | EFFICIENT SCAN LATCH SYSTEMS AND METHODS - Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component. | 05-01-2014 |
| 20140122950 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes first and second semiconductor chips incorporated in one package. The first semiconductor chip is subjected to a scan test. The second semiconductor chip is connected to an input-output terminal of the first semiconductor chip inside the package. The first semiconductor chip includes an input-output circuit, an output state maintaining circuit, and an input switch circuit. The input-output circuit performs input and output of data through the input-output terminal. The output state maintaining circuit maintains an output state of the input-output circuit during execution of the scan test. The input switch circuit inputs the data supplied through the input-output terminal into the input-output circuit during a normal operation. The input switch circuit inputs any data into the input-output circuit during execution of the scan test. | 05-01-2014 |
| 20140129885 | SCAN CLOCK GENERATOR AND RELATED METHOD THEREOF - An exemplary scan clock generator for providing a plurality of on-chip scan clocks to a plurality of cells under test includes: a receiving circuit, arranged for receiving an off-chip scan clock; and a clock processing circuit, coupled to the receiving circuit and arranged for generating the on-chip scan clocks according to the received off-chip scan clock; wherein clock edges of the on-chip scan clocks are staggered from each other, and the scan clock generator and the cells under test are set in a same chip. | 05-08-2014 |
| 20140136912 | COMBO DYNAMIC FLOP WITH SCAN - A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit. | 05-15-2014 |
| 20140136913 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead. | 05-15-2014 |
| 20140164858 | TESTING APPARATUS AND TESTING METHOD OF ELECTRONIC DEVICE - A testing apparatus and a testing method of an electronic device are provided. The testing apparatus includes at least two device transfer plates and a testing circuit. The device transfer plates are electrically and respectively connected to corresponding electronic devices and at least two sockets corresponding to the electronic devices. The testing circuit is electrically connected to the device transfer plates respectively through at least two sets of serial signal wire pairs. According to types of the electronic devices, the testing circuit provides a serial signal to one of the device transfer plates through the corresponding serial signal wire pair and receives a response from another one of the device transfer plates through the corresponding serial signal wire pair, so as to test whether an open circuit is occurred to a bus between the electronic devices respectively corresponding to the device transfer plates. | 06-12-2014 |
| 20140195869 | SERIAL I/O USING JTAG TCK AND TMS SIGNALS - The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. | 07-10-2014 |
| 20140201582 | SCAN CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD FOR TESTING SEMICONDUCTOR DEVICE - A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain. | 07-17-2014 |
| 20140223247 | SCAN-BASED TEST ARCHITECTURE FOR INTERCONNECTS IN STACKED DESIGNS - Aspects of the invention relate to scan-based test architecture for interconnects in stacked designs. The disclosed scan-based test architecture comprises a scan chain. Scan cells on the scan chain are configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. The scan-based test architecture can be used to identify single or multiple defective through-silicon vias. | 08-07-2014 |
| 20140223248 | ASICS HAVING PROGRAMMABLE BYPASS OF DESIGN FAULTS - A relatively small amount of programmable logic may be included in a mostly ASIC device such that the programmable logic can be used as a substitute for a fault-infected ASIC block. This substitution may occur permanently or temporarily. When an ASIC block is temporarily substituted, faulty outputs of the ASIC block are disabled just at the time they would otherwise propagate an error. The operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed programmable logic. Thus, a fault-infected ASIC block that operates improperly 1% of the time can continue to be gainfully used for the 99% of the time when its operations are fault free. This substitution can be activated in various stages of the ASIC block's life including after: initial design; pilot production; and mass production. This provides for cost saving and faster time-to-market, repair, and maintenance even years after installation and use. | 08-07-2014 |
| 20140237308 | TEST CONTROL USING EXISTING IC CHIP PINS - An apparatus and method are provided for testing normal circuitry in an integrated circuit, the method including writing test protocols into a plurality of test registers using an enable pin and a switch pin in a first mode, storing a logic high signal in one of the plurality of test registers once the writing is completed, switching from the first mode to a second mode if the one of the plurality of test registers stores the logic high signal, and testing the normal circuitry using the enable pin and the switch pin in the second mode. | 08-21-2014 |
| 20140237309 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores.—The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 08-21-2014 |
| 20140281773 | METHOD AND APPARATUS FOR INTERCONNECT TEST - A method of testing interconnected dies can include forming a cell for the interconnected dies, applying at least a first input to the cell to perform an open or short defects test, and applying at least a second input to the cell to perform one or more of a resistive defects test or a burn-in-test. Test circuitry for testing an interconnection between interconnected dies can include a wrapper cell embedded within a die where the wrapper cell includes a scannable data storage element, a hold data module, a selection logic, a transition generation module, and one or more additional input ports for receiving inputs causing the wrapper cell to perform an open or short defects test in a first mode and causing the wrapper cell to perform one or more of a resistive defects test in a second mode or a burn-in-test in a third mode. | 09-18-2014 |
| 20140298123 | Scan Chain Reconfiguration and Repair - A system includes an integrated circuit. The integrated circuit includes at least one scan chain group. A particular scan chain group of the at least one scan chain group includes at least one scan chain and at least one spare scan chain. The at least one scan chain of the particular scan chain group includes a particular scan chain. The at least one spare scan chain of the particular scan chain group includes a particular spare scan chain. The particular spare scan chain is configured to bypass the particular scan chain. | 10-02-2014 |
| 20140298124 | SCAN CHAIN PROCESSING IN A PARTIALLY FUNCTIONAL CHIP - A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons. | 10-02-2014 |
| 20140298125 | System and method for optimized board test and configuration - The present invention, system and method for optimized board test and configuration, comprises a method for splitting test data into dynamic and static parts, a system for optimized test access using variable-length shift register (VLSR) that uses the latter method, a system for optimized test application using VLSR with accumulating buffer (VLSRB) and a method for switching between BS-based test and VLSR/VLSRB-based test. | 10-02-2014 |
| 20140298126 | LATCH CIRCUIT, SCAN TEST CIRCUIT AND LATCH CIRCUIT CONTROL METHOD - A latch circuit includes: a data latch that holds data that has been input according to a first control signal or a second control signal; and a latch controller that includes a first input terminal to which a first operation signal is input, the first operation signal operating the data latch in a first scan method, and a second input terminal to which a second operation signal is input, the second operation signal operating the data latch in a second scan method; wherein when a prescribed value is input to the first input terminal, the latch controller outputs the second control signal to control the data latch, and when a prescribed value is input to the second input terminal, the latch controller outputs the first control signal to control the data latch. | 10-02-2014 |
| 20140298127 | SEMICONDUCTOR DEVICE, PHYSICAL QUANTITY SENSOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - A semiconductor device includes a digital circuit having a scan test mode. The digital circuit includes a first flip-flop forming a part of a scan chain when in the scan test mode, and a first selector provided on an input side of the first flip-flop. The first selector is capable of selecting a first signal when not in the scan test mode, and selecting a second signal that is different from the first signal when in the scan test mode. | 10-02-2014 |
| 20140304562 | Method for Testing Paths to Pull-Up and Pull-Down of Input/Output Pads - A SCAN chain architecture for each path in a circuit having combinational paths includes a control mechanism to control one or more flip flops and multiplexers to direct operational or test signals. Operational signals are sent along at least one combinational path to a pull-up/pull-down for at least one input/output pad and an operational voltage is recorded. Test signals are sent along at least one alternative path to an alternative input/output and a test voltage is recorded. The operational voltage is compared to the test voltage to identify a combinational path fault. | 10-09-2014 |
| 20140317462 | SCANNABLE SEQUENTIAL ELEMENTS - A scannable sequential element is provided. The scannable sequential element includes a master stage that includes a data path configured to receive a data input. The master stage also includes a pass gate located on the data path and configured to selectively pass the data input, in which the data path has only one pass gate. The master stage also includes a test path coupled to the data path and configured to receive a test input. The master stage also includes pass gates located on the test path and configured to selectively pass the test input. | 10-23-2014 |
| 20140325298 | TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION - A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference. | 10-30-2014 |
| 20140359385 | CIRCUIT AND LAYOUT TECHNIQUES FOR FLOP TRAY AREA AND POWER OTIMIZATION - Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode. | 12-04-2014 |
| 20140365838 | INTEGRATED CIRCUIT COMPRISING TEST CIRCUITRY FOR TESTING FAN-OUT PATHS OF A TEST CONTROL PRIMARY INPUT - An integrated circuit comprises a primary input adapted to receive a test control signal, a primary output, and logic circuits having inputs coupled to the primary input via respective fan-out paths of the primary input. The integrated circuit further includes first test circuitry configured for testing a designated portion of the integrated circuit in a first test mode of operation with the test control signal at a first logic value, and second test circuitry coupled between the inputs of the logic circuits and the primary output and configured for testing of the fan-out paths in a second test mode of operation in which the test control signal takes on both the first logic value and a second logic value associated with a functional mode of operation. The primary input, primary output, logic circuits and test circuitry may be associated with a particular circuit core of the integrated circuit. | 12-11-2014 |
| 20140372818 | Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan Chains - Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli. | 12-18-2014 |
| 20140380110 | TEST APPARATUS AND OPERATING METHOD THEREOF - A test apparatus includes a test apparatus may include a core suitable for accommodating a semiconductor device to be tested, a wrapper data register suitable for storing data used for testing the semiconductor device, and a bandwidth controller suitable for adaptively controlling a data bandwidth between the core and the wrapper data register according to the semiconductor device to be tested. | 12-25-2014 |
| 20150012788 | OPTIMIZATION OF A STORAGE SYSTEM CONTAINING ECC AND SCRAMBLE ENGINES - A method for selecting the scrambling and descrambling data transmitted in a storage system containing ECC and scramble engines with a seed table is disclosed and the steps comprises: encoding a data sent from a HOST interface by an ECC encoding engine and transmitting the data to a LFSR scramble engine; scrambling the data by the LFSR scramble engine and transmitting to a storage device; creating a seed value and transmitting the seed value to a seed table by the LFSR scramble engine; receiving the seed value from the seed table and the scrambled data from the storage device by a LFSR descramble engine, and descrambling the scrambled data based on the seed value and transmitting to an ECC decoding engine; and decoding the descrambled data received from the LFSR descramble engine and then acquiring the original data sent from the HOST interface. | 01-08-2015 |
| 20150012789 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 01-08-2015 |
| 20150026531 | POWER SUPPLY MONITOR FOR DETECTING FAULTS DURING SCAN TESTING - Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. The first result indicates whether a voltage provided to the circuit block(s) is below a voltage threshold. | 01-22-2015 |
| 20150026532 | METHOD AND APPARATUS FOR PROVIDING CLOCK SIGNALS FOR A SCAN CHAIN - An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals. | 01-22-2015 |
| 20150039954 | Adaptive Electrical Testing of Wafers - Methods and systems for determining one or more parameters for electrical testing of a wafer are provided. One method includes determining electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the electrical test paths. The method also includes determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the electrical test paths. In addition, the method includes acquiring information for one or more characteristics of a physical version of the wafer. The information is generated by performing an inline process on the physical version of the wafer. The method further includes altering at least one of the one or more parameters of the electrical testing for the wafer based on the acquired information. | 02-05-2015 |
| 20150058686 | RECONFIGURABLE MEMORY INTERFACE CIRCUIT TO SUPPORT A BUILT-IN MEMORY SCAN CHAIN - A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit. | 02-26-2015 |
| 20150058687 | MICRO-GRANULAR DELAY TESTING OF CONFIGURABLE ICs - A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits. | 02-26-2015 |
| 20150067423 | A Q-GATING CELL ARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT (LOS) TESTING AND AN ALGORITHM TO IDENTIFY BEST Q-GATING CANDIDATES - A method for creating an architecture to support Q-gating for launch-off-shift (LOS) scan testing using a plurality of flip-flops is provided. The method may include applying a common clock signal to each clock input of the plurality of flip-flops and applying a gated scan enable signal to each scan enable input of the plurality of flip-flops. The method may further include applying a global scan enable signal directly to each of a plurality of Q-gates corresponding to each of the plurality of flip-flops, wherein the global scan enable signal traverses a signal path that bypasses combinational logic located between any two flip-flops of the plurality of flip-flops. | 03-05-2015 |
| 20150067424 | PROCESSOR TAP SUPPORT FOR REMOTE SERVICES - An apparatus can include a circuit board; a processor chip mounted to the circuit board that includes a Test Access Port (TAP); a controller mounted to the circuit board that includes a port operatively coupled to the Test Access Port (TAP) of the processor chip; and a network interface operatively coupled to the controller. Various other apparatuses, systems, methods, etc., are also disclosed. | 03-05-2015 |
| 20150082108 | Circuit and Method for Monolithic Stacked Integrated Circuit Testing - A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the IC may be conducted on a layer-by-layer basis. | 03-19-2015 |
| 20150089311 | CHIP TESTING WITH EXCLUSIVE OR - A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel. | 03-26-2015 |
| 20150089312 | CHIP TESTING WITH EXCLUSIVE OR - A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel. | 03-26-2015 |
| 20150095729 | Circuit And Method For Monolithic Stacked Integrated Circuit Testing - A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its upper layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis. | 04-02-2015 |
| 20150100840 | SCAN SYSTEMS AND METHODS - Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row. | 04-09-2015 |
| 20150121158 | FUNCTIONAL PATH FAILURE MONITOR - System circuitry includes a logic circuit having an input and an output that is a functional element of the system circuitry. Pattern application circuitry is coupled to the input of the logic circuit and provides an input pattern to the input of the logic circuit. The input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly. A logic comparator is coupled to the input and the output of the logic circuit and generates pulses in response to the input pattern. A counter is coupled to the logic comparator that obtains a count of the pulses generated by the logic comparator in response to the input pattern. A signature comparator is coupled to the counter and generates a warning signal if the valid signature is different from the count. | 04-30-2015 |
| 20150128001 | Efficient Apparatus and Method for Testing Digital Shadow Logic Around Non-Logic Design Structures - A circuit for efficiently testing digital shadow logic ( | 05-07-2015 |
| 20150143189 | COVERAGE ENHANCEMENT AND POWER AWARE CLOCK SYSTEM FOR STRUCTURAL DELAY-FAULT TEST - Methods and devices applying to a clock system of scan circuits to enhance the test coverage for structural delay-fault tests are provided. According to an aspect, a method applying to a clock system of a scan circuit of a scan test containing one or more clock gating cells includes at any stage of the scan test outputting a controllable waveform of a clock signal at each clock gating cell, and eliminating a partially enabled clock signal during a capture cycle at each clock gating cell. | 05-21-2015 |
| 20150149843 | INTEGRATED CIRCUIT WITH A HIGH-SPEED DEBUG ACCESS PORT - An integrated circuit with a high-speed debug access port includes interface circuitry and a dedicated debug port in the interface circuitry. The interface circuitry includes a function circuit block that is used to receive a data packet from external circuitry coupled to the integrated circuit. The dedicated debug port is coupled to the function circuit block and is used to transmit the received data packet to debug circuitry on the integrated circuit. The interface circuitry may include a peripheral component interconnect express (PCIe) interface circuit. | 05-28-2015 |
| 20150293174 | API-BASED PATTERN-CONTROLLED TEST ON AN ATE - Method and apparatus for performing Pattern-Controlled tests on an automatic test equipment (ATE). The ATE includes a diagnostic instrument and a control device. An application programming interface (API) is installed in the control device and operates to interact with a test program and thereby automatically controls the diagnostic instrument to perform a test. The test program is coded in a high-level programming language and defines a plurality of operation events for the test based on user input. The API identifies the operational events and determines respective operational types associated therewith. Events of an operational type are assigned to a respective pattern label. The pattern labels are then aggregated into a pattern burst which is downloaded to the diagnostic instrument. | 10-15-2015 |
| 20150316608 | DEBUGGING SYSTEM AND METHOD - A debugging system for debugging an automated test process used on an automated test platform. The debugging system includes a debugging subsystem and a debugging coupler electrically coupled to the debugging subsystem. The debugging coupler is configured to be releasably electrically coupleable to a test head of the automated test platform. | 11-05-2015 |
| 20160003900 | SELF-TEST METHODS AND SYSTEMS FOR DIGITAL CIRCUITS - Circuits and methods for performing self-test of digital circuits are disclosed. In an embodiment, a method includes applying a set of test patterns for performing scan testing of a digital circuit to generate scan outputs from the digital circuit. The set of test patterns includes one or more sets of base test patterns already stored in a memory and one or more sets of derived test patterns temporarily generated from the one or more sets of base test patterns. The method further includes comparing the scan outputs received from the digital circuit with reference scan outputs corresponding to the digital circuit for fault detection in the digital circuit to thereby achieve a target fault coverage of the scan testing of the digital circuit. The reference scan outputs corresponding to the digital circuit are stored in the memory. | 01-07-2016 |
| 20160018465 | ARRANGEMENT FOR SELECTIVE ENABLING OF A DEBUGGING INTERFACE - An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled. | 01-21-2016 |
| 20160069954 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may include a first normal circuit configured to generate a normal signal while operating in a normal operation, and a test signal generation unit configured to generate a test signal in response to a test control signal. The semiconductor apparatus may include a signal transfer unit configured to transfer one of either the normal signal or the test signal, as an internal signal, to a signal line, and a second normal circuit configured to perform the normal operation in response to receiving the internal signal from the signal line. The semiconductor apparatus may include a test operation circuit configured to perform a test operation in response to receiving the internal signal from the signal line. | 03-10-2016 |
| 20160097809 | SEMICONDUCTOR DEVICE AND MULTI-SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor device includes a built-in self-test controller suitable for generating a test command and test data, and generating a test result signal in response to test result data, in a built-in self-test mode, an internal circuit suitable for performing a test operation in response to the test command and the test data and generating the test result data as a result of the test operation, and a signal transfer controller suitable for outputting the test command, the test data, and the test result signal through a set probe pad and a set bump pad in the built-in self-test mode. | 04-07-2016 |
| 20160097811 | SCAN FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME - A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop os configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other. | 04-07-2016 |
| 20160109516 | Portable and Modular Logic Design Testing Module - A portable logic design testing module detachably integrates with a breadboard, and connects with other logic design modules on the breadboard to form larger testing systems. The logic design module provides input signals through at least one input module, and displays output signals through at least one output module. The module utilizes interconnecting circuits for modularizing adjacent modules, logic switches for controlling logic binary numbers, counters for incrementally manipulating the binary numbers, LEDs for displaying the binary numbers, and a display for displaying the binary numbers. The module detachably connects to the breadboard through a six-pin header to enable facilitated displacement between different regions of the breadboard. Additionally, the logic design module possesses modular characteristics, operatively connecting with adjacent logic design modules to increase bit size and testing capacity. The relatively small size, modular configuration, and cascadable capacity of the module enables replacement of logic design training kits. | 04-21-2016 |
| 20160109517 | Test Point Insertion For Low Test Pattern Counts - Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both. | 04-21-2016 |
| 20160116533 | DIAGNOSTIC APPARATUS - A diagnostic apparatus is disclosed, which includes a processor configured to extract, from a plurality of components included in an integrated circuit to be diagnosed, a failure candidate based on test results obtained from actual operations of the integrated circuit, the actual operations being implemented by individually applying a plurality of types of test patterns to the integrated circuit, extract, from a plurality of pass patterns of the test patterns, a pass pattern with which a signal is transmitted to the failure candidate, based on log data obtained from simulations with the test patterns, the test results of the plurality of pass patterns being normal, and execute, using a fail pattern of the test patterns and the extracted pass patterns, a failure simulation assuming that the failure candidate is failed, the test result of the fail pattern being abnormal. | 04-28-2016 |
| 20160154056 | CIRCUIT DIVISION METHOD FOR TEST PATTERN GENERATION AND CIRCUIT DIVISION DEVICE FOR TEST PATTERN GENERATION | 06-02-2016 |
| 20160169967 | INSERTING BYPASS STRUCTURES AT TAP POINTS TO REDUCE LATCH DEPENDENCY DURING SCAN TESTING | 06-16-2016 |
| 20160169971 | Design-for-Test Techniques for a Digital Electronic Circuit | 06-16-2016 |
| 20160169972 | INSERTING BYPASS STRUCTURES AT TAP POINTS TO REDUCE LATCH DEPENDENCY DURING SCAN TESTING | 06-16-2016 |
| 20160202320 | LOW-OVERHEAD DEBUG ARCHITECTURE USING A SPECULATIVE, CONCURRENT & DISTRIBUTED DATA CAPTURE AND PROPAGATION SCHEME | 07-14-2016 |
| 20160377678 | METHOD AND APPARATUS FOR GENERATING FEATURED TEST PATTERN - An method of generating a featured scan pattern for test includes: providing a plurality of predetermined test patterns to perform test on a plurality of devices under test (DUT) under a stress condition to generate a plurality of test responses of each DUT; grouping a plurality of specific test responses of each DUT from the test responses of each DUT to determine a feature value corresponding to a failure feature for each DUT; and generating at least one featured test pattern according to the feature value of each DUT. | 12-29-2016 |
| 20170234927 | EFFICIENT SCAN LATCH SYSTEMS AND METHODS | 08-17-2017 |
| 20220137133 | DEVICE AND METHOD FOR MONITORING DATA AND TIMING SIGNALS IN INTEGRATED CIRCUITS - An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data. | 05-05-2022 |
