| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714728000 | Random pattern generation (includes pseudorandom pattern) | 20 |
| 20090013227 | Method Using Non-Linear Compression to Generate a Set of Test Vectors for Use in Scan Testing an Integrated Circuit - A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to at least one of a plurality of decoders, wherein each decoder is adapted to recognize the coding scheme represented by one of the bit patterns. A decoder is operated to generate one of the test vectors, when the decoder receives the block corresponding to the generated test vector, and recognizes the coding scheme that is encoded by the received data block. | 01-08-2009 |
| 20090070646 | Multiple-Capture DFT system for scan-based integrated circuits - A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks. | 03-12-2009 |
| 20090089636 | Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors - A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and pseudo-random pattern generator (PRPG) circuitry, are tested. Controlled by the LBIST control logic, PRPG inputs a test pattern into scan chains within the cores of each device. A new test pattern is generated and executed during the scan shift phase of each LBIST loop. Logic output generated by each scan chain in the core is compared to other core logic output. Failures within the multi-core processors are determined by whether the logic output generated from a core, within a latch sequence, does not match the logic output of the other cores. If logic output, from a core within a latch sequence, does not match, then the latch number, loop number, and latch values are recorded as failed. | 04-02-2009 |
| 20090177933 | DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS - A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns. | 07-09-2009 |
| 20090187800 | PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY - A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity. | 07-23-2009 |
| 20090217115 | Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy - A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned. | 08-27-2009 |
| 20090259902 | Semiconductor device - Provided is a semiconductor device that can be reduced in size while variation in shape among circuit patterns is reduced. The semiconductor device includes multiple circuit patterns and first dummy patterns. The multiple circuit patterns are disposed at regular intervals, and are used as part of the circuit. The multiple circuit patterns consist of two outermost circuit patterns and the other inner circuit patterns. The first dummy patterns are disposed on outer sides of the two outermost circuit patterns, respectively. The distance between each of the outermost circuit patterns and the corresponding first dummy pattern is equal to a distance between any adjacent two of the circuit patterns. A width of each of the first dummy patterns is smaller than a width of any of the circuit patterns, and is equal to a minimum design rule width, for example. | 10-15-2009 |
| 20100100781 | Fully X-Tolerant, Very High Scan Compression Scan Test Systems And Techniques - Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods. | 04-22-2010 |
| 20100107023 | PROTECTING DATA ON INTEGRATED CIRCUIT - Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode. | 04-29-2010 |
| 20100218059 | On-Chip Seed Generation Using Boolean Functions for LFSR Re-Seeding Based Logic BIST Techniques for Low Cost Field Testability - This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip. | 08-26-2010 |
| 20100269002 | Pseudo-Random Balanced Scan Burnin - According to various illustrative embodiments, a method and system for toggling a scan enable signal are described. In one aspect, the method comprises setting a scanin seed and resetting a monitor, generating random shift patterns, and resetting the monitor a second time. The method also comprises generating the random shift patterns a second time and strobing an activity flag. The method also comprises resetting the monitor a third time and enabling the scan enable signal toggling mechanism, and generating random shift/capture patterns repeatedly at least a predetermined number of times. | 10-21-2010 |
| 20100287429 | Test pattern generating method , device , and program - A test pattern generating device generates a test pattern with respect to a semiconductor circuit having first and second common circuits and a non-common circuit other than the first and second common circuits, wherein each of the first and second common circuits has a scan chain for checking an operation of the circuit by applying a test pattern from the outside of the circuit. A set of scan chains and a set of assumed faults are created for each of the first and second common circuits. Any of the first and second common circuits is determined as the common circuit of a first test target. After the determined common circuit of the first test target is subjected to ATPG and detection of circuit fault, a test pattern generated in successful ATPG about the common circuit of the first test target is diverted to the common circuit determined as the second test target, and ATPG and detection of a circuit fault of the non-common circuit part is carried out. | 11-11-2010 |
| 20100293424 | SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS AND METHOD, AND PROGRAM - A semiconductor integrated circuit includes: a plurality of flip-flops connected to a scan chain set as a test path of an integrated circuit; and a data-collection section inputting setting values of the plurality of flip-flops connected to the scan chain through the scan chain or an independent connection path, wherein the data-collection section inputs the setting values of the flip-flops at the time the power has been turned on to the plurality of flip-flops, and performs generation processing of random numbers, or random-number generation data, or fixed data on the basis of the input values. | 11-18-2010 |
| 20110179326 | The Performance Of Signature-Based Diagnosis For Logic BIST - Techniques are disclosed for reducing the set of initial candidates in signature based diagnosis methodology. These techniques are based on a unique way of making optimum use of information from logic back-cone tracing along with equations that describe the test response compactor. | 07-21-2011 |
| 20110258503 | Fully X-tolerant, Very High Scan Compression Scan Test Systems And Techniques - Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods. | 10-20-2011 |
| 20120304030 | SEMICONDUCTOR-BASED TEST DEVICE THAT IMPLEMENTS RANDOM LOGIC FUNCTIONS - A semiconductor-based test device includes a plurality of testing clusters and a pseudorandom global stimulus source coupled to the testing clusters. Each testing cluster includes a plurality of data registers and logic elements configured to perform random logic functions for generating test data for the plurality of data registers. The pseudorandom global stimulus source generates a pseudorandom binary stimulus for the logic elements. At least some of the plurality of testing clusters are coupled together to support inter-cluster fan-out and fan-in of data register output. | 11-29-2012 |
| 20130268818 | Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein. | 10-10-2013 |
| 20140143623 | METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION - A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step. | 05-22-2014 |
| 20150323600 | TIMING-AWARE TEST GENERATION AND FAULT SIMULATION - Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs. | 11-12-2015 |
| 20150377960 | SIMULTANEOUS TRANSITION TESTING OF DIFFERENT CLOCK DOMAINS IN A DIGITAL INTEGRATED CIRCUIT - Implementations of the present disclosure involve an apparatus and/or method for conducting simultaneous transition testing of different clock domains of a microprocessor design at different frequencies through a controlled order of clock pulses in each domain. In general, a microelectronic design utilizes test control circuitry associated with each clock domain of the design to conduct simultaneous transition testing of the clock domains. The testing control circuitry associated with each clock domain of the microelectronic design further allows for the testing device to delay testing within a particular clock domain. By delaying the testing within a particular clock domain, the testing of the various clock domains can be synchronized. Through these testing procedures, the amount of time required to perform the ATPG testing of a microelectronic design may be greatly reduced. | 12-31-2015 |
