Entries |
Document | Title | Date |
20080215942 | Testing of integrated circuits using boundary scan - Circuit testing equipment comprising a computer ( | 09-04-2008 |
20080244343 | STRUCTURAL TESTING USING BOUNDARY SCAN TECHNIQUES - A boundary scan technique to generate toggling waveform such as a square wave signal to perform structural testing is disclosed. An instr_extesttoggle command is provided that enables IEEE 1149.1 boundary scan cell to selectively generate the toggling signal on the pre-specified output pads of the integrated circuit. The frequency of the toggling signal may be controlled by the JTAG clock signal and the frequency of the toggling signal may be independent of the length of the boundary scan chain. Such an approach circumvents provisioning test points on the interconnects of a printed circuit board. | 10-02-2008 |
20080250287 | IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES - In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals. | 10-09-2008 |
20080256406 | Testing System - There is provided an improved testing system. More specifically, in one embodiment, there is provided a method including accessing machine overall equipment effectiveness or efficiency (OEE) data including machine generated operational event states of an automated testing (ATE) system and times the machine generated operational event states occurred, receiving operator OEE data including operator entered operational event states of the ATE and times the operator observed operational event states, and combining the machine OEE data and the operator OEE data to generate merge OEE data. | 10-16-2008 |
20080263420 | TEST STANDARD INTERFACES AND ARCHITECTURES - In a first embodiment a TAP | 10-23-2008 |
20080270857 | BOUNDARY SCAN CONNECTOR TEST METHOD CAPABLE OF FULLY UTILIZING TEST I/O MODULES - Read the description file of a PCBA without determining and selecting connectors which might be relevant to boundary scan. The description file of the PCBA determines which pins of the connectors on the PCBA should correspond to the pins of a test I/O module. And use the wiring report generated by an auto test program generator to correspond the pins of the test I/O module to the pins of the connectors which are accessed by boundary scan. Thus the IC of the test I/O module would not have any unused pin between any two consecutive pins wired to the connectors of the PCBA. | 10-30-2008 |
20080270858 | Device and Method for Configuring Input/Output Pads - A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information; and repeating the stage of serially writing a certain boundary scan register word to a boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. A device that includes a core, connected to a boundary scan register, a TAP controller and multiple IO pad circuits, the device is characterized by including a control circuit adapted to determine a current configuration of the IO pads, to generate multiple boundary scan register words that comprise configuration information; and to control a repetition of: writing a certain boundary scan register word to the boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. | 10-30-2008 |
20080288839 | Jtag Test Architecture For Multi-Chip Pack - A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip. | 11-20-2008 |
20080288840 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 11-20-2008 |
20080294954 | SYSTEM, METHOD AND PROGRAM FOR PROCESSING READ ERROR - A system for processing a data read error from a tape medium in one embodiment includes a reading section for reading data in data units from a tape medium; a reading control section for controlling said reading section to read data, and on condition that if an error occurs in reading one of said data units, the data unit where the error occurs is considered an error data unit and the reading control section issues an instruction to skip the error data unit and read the next readable data unit immediately after the error data unit; a computation section for computing a number of records and a number of boundary marks included in the error data unit where said error occurs from information about the records and boundary marks included in the data unit preceding the error data unit that is read immediately before said error occurs, and information about the records and boundary marks included in the data unit next to said error data unit, the boundary marks indicating the boundary of a record block; and a communication section for outputting the number information about said computed number of records and said computed number of boundary marks. | 11-27-2008 |
20080307279 | SERIAL SCAN CHAIN IN A STAR CONFIGURATION - A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase. | 12-11-2008 |
20080307280 | Scan cells with minimized shoot-through and scan chains and integrated circuits using the same - A scan including data and shift inputs, and input selection circuitry for selecting between the data and shift inputs during normal, capture, and shift modes in response to only a first control signal and a second control signal. The input selection circuitry includes a first storage element for storing a bit representing a state of the first control signal in response to a change in state of the second control signals and multiplexing circuitry. The multiplexing circuitry is operable in the normal mode to select the data input in response to a first state of the second control signal, in the capture mode to select the data input when the bit stored in the first storage element represents a first state of the first control signal, and in the shift mode to select the shift input when the bit stored in the first storage element represents a second state of the first control signal. A second storage element stores, in response to the first state of the first control signal, data presented at the selected one of the data and shift inputs. | 12-11-2008 |
20080320350 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 12-25-2008 |
20090006915 | APPARATUS AND METHOD FOR EMBEDDED BOUNDARY SCAN TESTING - Embedded boundary scan testing apparatus and methodologies are disclosed for testing processor-based circuit boards without processor intervention. A boundary scan controller is embedded in a circuit board along with a boundary scan chain having JTAG devices connected with an electrical circuit of the board. Upon power up, the boundary scan controller holds an on-board processor system in reset, loads boundary scan test vectors and commands from an on-board non-volatile memory, and runs boundary scan testing while holding the processor system in the reset state. The boundary scan controller preferably includes a test access port controller that implements only a subset of the JTAG standard 16 machine states to optimize performance and minimize controller hardware. The test results may be stored in an externally accessible on-board memory for subsequent retrieval in order to facilitate board troubleshooting and/or repair, where the provision of on-board boundary scan testing allows testing of boards while installed in the field, and the embedded scan controller allows field testing of on-board processor systems and related circuitry to enhance the test coverage over processor-driven boundary scan testing. | 01-01-2009 |
20090019328 | IC CIRCUIT WITH TEST ACCESS CONTROL CIRCUIT USING A JTAG INTERFACE - An integrated circuit comprises a first circuit portion ( | 01-15-2009 |
20090031179 | JTAG TEST CODE AND DATA COMPILER AND METHOD - A software compiler is described here that is capable of analyzing JTAG test functions and translating them into code and date usable and accessible by a JTAG-bus controller hardware circuit. The compiler is capable of reading instructions and data information not directly usable by a JTAG-bus controller, such as Serial Victor Format, and generating instructions and data executable by a JTAG-bus controller hardware circuit. This allows the JTAG-bus controller to directly access such compiled code during the test without using an interpreter to translate such information before executing them. | 01-29-2009 |
20090037785 | LOW OVERHEAD INPUT AND OUTPUT BOUNDARY SCAN CELLS - A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic circuit. The cell is placed in a test mode that disables normal operation of the logic circuit. The data scanned into the input memory circuit is transferred into the output memory circuit simultaneous with the placing the cell in the test mode. A transmission gate between the logic circuit and the output memory circuit and a transmission gate between the input memory circuit and the output memory circuit effect the changes between normal operation and test modes. | 02-05-2009 |
20090055697 | ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed. | 02-26-2009 |
20090077438 | CIRCUIT INTERCONNECT TESTING ARRANGEMENT AND APPROACH THEREFOR - Logic level crossings in an integrated circuit are detected. According to an example embodiment, a reset signal is provided to a flip-flop ( | 03-19-2009 |
20090083594 | Testing Functional Boundary Logic at Asynchronous Clock Boundaries of an Integrated Circuit Device - Mechanisms for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device are provided. With these mechanisms, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation. | 03-26-2009 |
20090089635 | Electronic Device Testing System and Method - The invention provides a testing system and method suitable for determining whether a pin-out of an electrical component is properly connected to a PCB. The testing system includes a testing signal source, a signal detector, a signal processor, an analysis unit and an integrated circuit having boundary-scan test function to provide testing signals to the device under test (DUT) whose signal traces are passing through inner layer of PCB in order to detect whether the sensed signal is an error signal. | 04-02-2009 |
20090106612 | ENHANCING SPEED OF SIMULATION OF AN IC DESIGN WHILE TESTING SCAN CIRCUITRY - A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a path through combinational logic in a design of the IC chip, starting from an output port of a first scan cell and ending in an input port of a second scan cell. If the first and second scan cells receive a common scan enable signal, then the computer generates at least a portion of the computer program, i.e. software to perform simulation of propagating a signal through the path conditionally, for example when the common scan enable signal is inactive and alternatively to skip performing simulation when the common scan enable signal is active. The computer stores the portion of the computer program in memory, for use with other such portions of the computer program. | 04-23-2009 |
20090113264 | BUILT IN SELF TEST FOR INPUT/OUTPUT CHARACTERIZATION - A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes test logic configured to provide a test completion signal indicative of completion of a respective test based on a comparison of an output of the first storage element relative to test value (TVALUE). The output of the first storage element is provided to the input of the second storage element unchanged during a first operating state and, depending on the test completion signal, an inverted version of the output of the first storage element can be provided to the input of the second storage element during a second operating state. A bi-directional element is connected to receive the output of the second storage element and to feed the output of the second storage element back to an input of the first storage element. | 04-30-2009 |
20090119557 | HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS - A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure. | 05-07-2009 |
20090119558 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 05-07-2009 |
20090125767 | Methods for the Support of JTAG for Source Synchronous Interfaces - Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver. | 05-14-2009 |
20090138771 | BOUNDARY SCAN METHOD, SYSTEM AND DEVICE - A boundary scan method, including generating a first parallel unipolarity boundary scan signal by a scan signal generation apparatus, sending the first parallel unipolarity boundary scan signal to a boundary scan controller; and converting, by the boundary scan controller, the first parallel unipolarity boundary scan signal into a serial boundary scan signal in a differential signaling form, and using the serial boundary scan signal for scanning a boundary scan device connected between a scan signal output and a scan signal input of the boundary scan controller. | 05-28-2009 |
20090150731 | TEST CIRCUIT CAPABLE OF SEQUENTIALLY PERFORMING BOUNDARY SCAN TEST AND TEST METHOD THEREOF - A boundary scan test circuit is capable of sequentially performing a boundary scan test with respect to semiconductor integrated circuits bonded to both surfaces of a memory board. In order to reduce a boundary scan test time, the boundary scan test circuit includes a mirror function unit which transmits data signals of a first group pin or data signals of a second group pin corresponding to the first group pin according to a mirror function enable signal, and a boundary scan test unit which receives the data signals of the mirror function unit to perform a boundary scan test. | 06-11-2009 |
20090164859 | DRIVING CIRCUIT OF DISPLAY APPARATUS AND DRIVING METHOD THEREOF - A driving circuit of a display apparatus includes a decoder coupled to a plurality of scan lines of a display panel for decoding a plurality of input signals to output a plurality of scan line driving signals to thereby enable at least one scan line of the plurality of scan lines, and a plurality of control units (respectively coupled to the plurality of scan lines) for receiving an output enable signal to disable the plurality of scan lines during an interval between two scan lines being enabled. | 06-25-2009 |
20090172485 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 07-02-2009 |
20090187799 | Common test logic for multiple operation modes - In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed. | 07-23-2009 |
20090193305 | TEST MODE SOFT RESET CIRCUITRY AND METHODS - An integrated circuit chip having testing logic for testing circuitry of the integrated circuit chip is provided. The integrated circuit chip includes at least a scan-in pin, a scan clock pin, and a test controller. The test controller has test mode registers for storing a type of test mode to be executed, and the test controller accepting signals from the scan-in pin and the scan clock pin. The scan-in pin and the scan clock pin receiving a test program for the type of test mode and a soft-reset pattern. Also included is a state machine logic that is part of the integrated circuit chip. The state machine logic, during execution of the test program, being configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The sampling by the state machine circuitry identifying a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggering a soft reset by updating the test mode registers of the test controller. The soft reset therefore eliminates the need for an extra reset pin, when testing in scan mode. The communication channel defined through the use of the scan-in and scan clock pins can be used to trigger other soft actions. | 07-30-2009 |
20090217113 | UTILIZING SERIALIZER-DESERIALIZER TRANSMIT AND RECEIVE PADS FOR PARALLEL SCAN TEST DATA - A Serializer/De-serializer (SerDes) of an integrated circuit (IC) includes selectable inputs and outputs not only for functional data and boundary scan (e.g., JTAG) test data, but also for parallel-scan test data. The serializing portion of the SerDes includes multiplexing logic responsive to control signals to select or identify one of the multiplexing logic inputs for functional data, boundary scan data and parallel-scan data. The de-serializing portion similarly includes selection logic responsive to such control signals to select or identify one of the selection logic outputs for functional data, boundary scan data and parallel-scan data. The multiplexing logic and selection logic couple the selected input or output, respectively, to the SerDes input/output pads. | 08-27-2009 |
20090217114 | SELECTABLE DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 08-27-2009 |
20090235135 | BSC macrostructure for three-dimensional wiring and substrate having the BSC macrostructure - A BSC macrostructure for three-dimensional wiring includes a BSC (boundary scan cell) and an aperture electrode for electrode connection which is connected to the BSC. | 09-17-2009 |
20090235136 | ADDRESSABLE TEST ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP. | 09-17-2009 |
20090249144 | SHADOW ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal. | 10-01-2009 |
20090259901 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 10-15-2009 |
20090265594 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. Trace circuitry within an IC can operate autonomously to store and output functional data occurring in the IC. The store and output operations of the trace circuitry are transparent to the functional operation of the IC. An auto-addressing RAM memory stores input data at an input address generated in response to an input clock, and outputs stored data from an output address generated in response to an output clock. | 10-22-2009 |
20090265595 | MULTIPLE TEST ACCESS PORT PROTOCOLS SHARING COMMON SIGNALS - A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the states. The predetermined sequence of the states represents a no-operation for at least one of the modes and also represents a mode change command. | 10-22-2009 |
20090287973 | ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA ABSTRACT - Scan testing of plural target electrical circuits, such as circuits | 11-19-2009 |
20090307547 | Integrated circuit board with JTAG functions - In an integrated circuit board, a plurality of integrated circuits to be checked are connected together in a star shape. Operation clock data for JTAG of each integrated circuit and check data for checking each integrated circuit are stored. When an integrated circuit to be checked is specified, operation clock data for JTAG and check data for the specified integrated circuit are determined. With an operation clock for JTAG according to the determined operation clock data for JTAG, the determined check data is input to the specified integrated circuit. Based on the check data and output data output from the integrated circuit to which this check data is input, the integrated circuit board determines a malfunction in the integrated circuit, and then stores the determination result in a storage device. | 12-10-2009 |
20100011263 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 01-14-2010 |
20100023820 | Asynchronous Communication Apparatus Using JTAG Test Data Registers - An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register. | 01-28-2010 |
20100023821 | Asynchronous Communication Using Standard Boundary Architecture Cells - An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR. Further still, a digital logic interface is configured to control the direct transfer of data between the JTAG standard parallel TDR and a corresponding one of the plurality of function registers. As a result of the re-use of existing boundary scan architecture, a significant reduction in wiring congestion is realized. Thus, asynchronous communication is provided without sacrificing valuable integrated circuit real estate. | 01-28-2010 |
20100023822 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 01-28-2010 |
20100031102 | IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES - In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals. | 02-04-2010 |
20100077269 | REDUCED SIGNALING INTERFACE METHOD AND APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. | 03-25-2010 |
20100095172 | LOW POWER TESTING OF VERY LARGE CIRCUITS - Plural scan test paths ( | 04-15-2010 |
20100100780 | HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS - A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure. | 04-22-2010 |
20100174957 | CORRELATION AND OVERLAY OF LARGE DESIGN PHYSICAL PARTITIONS AND EMBEDDED MACROS TO DETECT IN-LINE DEFECTS - A method of identifying defects in a chip integral to a wafer by correlating physical defects to a corresponding logic fail. The method includes partitioning a logic representation of the chip; identifying physical defects and determining corresponding coordinates of each identified physical defect; determining boundaries of the failing logic partitions, each logic partition being bound by coordinates; and correlating the physical coordinates of the defects to the bounded failing logic partitions. The scaled back, low overhead method correlates design sensitivities and test fails to physical process defects detected during semiconductor manufacturing in-line test inspection. It further identifies and records design physical coordinates of large embedded logic physical partitions test structures, memory arrays, and the like. | 07-08-2010 |
20100174958 | Test circuit including tap controller selectively outputting test signal based on mode and shift signals - A test circuit includes a plurality of TAP controllers conforming to a standard specification defined in IEEE 1149 and includes a master TAP controller which receives a control code and a test control signal and performs a test on a circuit to be tested and which outputs a shift mode signal, a first slave TAP controller which receives the control code and the test control signal and performs a test on a circuit to be tested, and a first TAP pin control circuit provided to correspond to the first slave TAP controller and which switches between inputting the control code to the first slave TAP controller from the outside and inputting the control code through the master TAP controller, on the basis of the shift mode signal. | 07-08-2010 |
20100180169 | SYSTEMS AND METHODS OF IMPLEMENTING REMOTE BOUNDARY SCAN FEATURES - A system and method for remotely performing boundary scans on a circuit board, device and/or system across a network. A first computing component, connected to the network, includes a computer readable media including computer executable instructions. The instructions cause the computing component to maintain or access a library of test scan procedures for a plurality of subject circuit boards. At least one of the test scan procedure is downloaded to a second computing component proximate the circuit board, device and/or system. The second computing component and the test scan procedure are monitored and controlled remotely via the network. | 07-15-2010 |
20100211838 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 08-19-2010 |
20100235696 | EMBEDDED TEST SYSTEM AND METHOD - An embedded test system is provided where asynchronous communications links are used to pass the boundary scan information by the use of a network router to a boundary scan adapter ( | 09-16-2010 |
20100241915 | IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES - In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals. | 09-23-2010 |
20100262877 | Techniques for Boundary Scan Testing Using Transmitters and Receivers - A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit. | 10-14-2010 |
20100262878 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE | 10-14-2010 |
20100281318 | Tolerant in-system programming of field programmable gate arrays (fpgas) - Fault tolerant programming of a programmable device advantageously occurs via a host controller that first queries the programmable device through a Boundary scan interface to identify the device. Thereafter, host controller selects a program file in accordance with the device identity for subsequent downloading via the Boundary scan interface to program the device. Thereafter, the host controller verifies that successful programming has occurred. | 11-04-2010 |
20100287428 | System and method for testing a circuit - A system for testing a circuit. The system comprises a first circuit mounted on an embedded first circuit board and a test circuit mounted on the embedded first circuit board. The system further comprises a second circuit board on the first circuit board, the second circuit board including a second circuit and a test device external to the first and second circuit board. The test circuit is effective to send at least one first test signal from the test circuit to the first circuit, receive a first response of the at least one first test signal from the first circuit, and forward the first response to the test device. | 11-11-2010 |
20100299568 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 11-25-2010 |
20110010593 | SCAN ARCHITECTURE FOR FULL CUSTOM BLOCKS - A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability. | 01-13-2011 |
20110010594 | INTERFACE TO FULL AND REDUCE PIN JTAG DEVICES - The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( | 01-13-2011 |
20110016365 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 01-20-2011 |
20110016366 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 01-20-2011 |
20110055648 | SYSTEM AND A METHOD FOR TESTING CONNECTIVITY BETWEEN A FIRST DEVICE AND A SECOND DEVICE - A device and a method for testing a connectivity between a first device and a second device, the method includes: writing, at a first frequency and in a serial manner, a first test word to a source boundary scan register; writing a content of the source boundary scan register, at a second frequency and in a parallel manner, to a target boundary scan register; wherein the second frequency is higher than the first frequency; reading the content of the target boundary scan register; wherein the source and target boundary scan registers are selected from a first boundary scan register of the first device and a second boundary scan register of the second device; and evaluating a connectivity between the first and second device in response to a relationship between the first test word and the content of the target boundary scan register. | 03-03-2011 |
20110072325 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 03-24-2011 |
20110087938 | REDUCED SIGNALING INTERFACE METHOD AND APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. | 04-14-2011 |
20110087939 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals. The need for different IC pins and/or core terminals is overcome by an interface in accordance with the disclosure that allows the TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core terminals. Further, this interface allows merged TAP and scan test port interfaces to be selected individually or in groups. | 04-14-2011 |
20110087940 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 04-14-2011 |
20110093751 | SYSTEM AND METHOD FOR SINGLE TERMINAL BOUNDARY SCAN - An electronic circuit having a boundary scan test circuit receives, though one pin, an embedded clock encoded test signal having an encoded bit stream having occurrences of a first header followed by at least one encoded boundary scan mode bit and an encoded second header followed by at least one boundary scan test input bit. The bit stream and the clock are extracted and occurrences of the first header and second header are detected. Based on the detected occurrences the boundary scan mode bits and boundary scan input bits are identified and distributed to the electronic circuit, along with the extracted clock, and boundary scan test is performed. | 04-21-2011 |
20110099441 | ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA ABSTRACT - Scan testing of plural target electrical circuits, such as circuits | 04-28-2011 |
20110113298 | METHOD OF AND AN ARRANGEMENT FOR TESTING CONNECTIONS ON A PRINTED CIRCUIT BOARD - A method of and an arrangement for testing connections on a printed circuit board between boundary-scan compliant circuit terminals of one or more boundary-scan compliant devices mounted at the printed circuit board and comprising a boundary-scan register of boundary-scan cells of the boundary-scan compliant circuit terminals. Under control of an electronic processing unit, boundary-scan properties of the or each boundary-scan compliant device are retrieved, a list comprising boundary-scan compliant circuit terminals is displayed, and a selection of at least a first and second boundary-scan compliant circuit terminal is received. Based on this selection, a boundary-scan cell of a first boundary-scan compliant circuit terminal of a boundary-scan compliant device is operated as a driver and a boundary-scan cell of a second boundary-scan compliant circuit terminal of a boundary-scan compliant device is operated as a sensor. The driver is controlled through data provided to the boundary-scan register. Data sensed by the sensor are latched in the boundary-scan register. The driver and sensor data are analyzed for a connection between the first and the second boundary-scan compliant circuit terminals and the result of the analyses is presented. | 05-12-2011 |
20110119542 | SEMICONDUCTOR DEVICE TEST SYSTEM WITH TEST INTERFACE MEANS - A semiconductor device test system has an interface for use with a semiconductor device test method, and a semiconductor device test method. In a first mode of an interface, in reaction to test signals corresponding to a test standard, for example, a JTAG test standard, and received by the interface from a test device, the interface outputs signals corresponding to the test standard to a semiconductor device to be tested. In a second mode of the interface, in reaction to test signals corresponding to the test standard and received by the interface from a test device, the interface outputs signals that do not correspond to the test standard to a semiconductor device to be tested. | 05-19-2011 |
20110119543 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 05-19-2011 |
20110145665 | ACCESSING SEQUENTIAL DATA IN A MICROCONTROLLER - System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols. | 06-16-2011 |
20110154140 | DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller. | 06-23-2011 |
20110161757 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 06-30-2011 |
20110179325 | SYSTEM FOR BOUNDARY SCAN REGISTER CHAIN COMPRESSION - A system for testing input/output pads of an integrated circuit includes boundary scan register chains, a test control unit and a test data processing unit. Input test data is provided to the test control unit, which then provides the test data to the test data processing unit. The test data processing unit processes the test data to obtain processed test data. Thereafter, the processed data is loaded in each of the boundary scan register chains in parallel. The processed test data is propagated sequentially through the plurality of boundary scan register chains to obtain output test data. The output test data is used to detect faults present in the input/output pads of the integrated circuit. | 07-21-2011 |
20110185242 | INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES - The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( | 07-28-2011 |
20110185243 | CONTROLLING TWO JTAG TAP CONTROLLERS WITH ONE SET OF JTAG PINS - Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary scan circuit with a second plurality of control inputs, and a plurality of boundary scan control signals connected to the first plurality of control inputs on the first boundary scan circuit and to the second plurality of control inputs on the second boundary scan circuit. At least two of the plurality of boundary scan control signals are connected between the first boundary scan circuit and the second boundary scan circuit in a crossover fashion. | 07-28-2011 |
20110202808 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. | 08-18-2011 |
20110209014 | HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS - A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure. | 08-25-2011 |
20110209015 | SERIAL SCAN CHAIN IN A STAR CONFIGURATION - A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase. | 08-25-2011 |
20110209016 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 08-25-2011 |
20110209017 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 08-25-2011 |
20110209018 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 08-25-2011 |
20110209019 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 08-25-2011 |
20110214027 | 1149.1 TAP LINKING MODULES - IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 09-01-2011 |
20110258502 | WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals. | 10-20-2011 |
20110271160 | ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA ABSTRACT - Scan testing of plural target electrical circuits, such as circuits | 11-03-2011 |
20110276847 | SHADOW ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal. | 11-10-2011 |
20110289370 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 11-24-2011 |
20110307749 | Low leakage boundary scan device design and implementation - A boundary scan circuit comprising a freeze circuit and a transparency circuit provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving power. There are two transparency circuit configurations, one that connects to an input pad cell and one that connects to an output pad cell. The circuitry in the transparency circuit is controlled in such a manner as to establish at the output of transparency circuit a known logic state to control leakage current resulting from the circuitry of the various pad cell configurations, which further conserves power during sleep mode. | 12-15-2011 |
20120017129 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 01-19-2012 |
20120023381 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 01-26-2012 |
20120036406 | METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION - The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure. | 02-09-2012 |
20120060067 | APPARATUS AND METHOD OF AUTHENTICATING JOINT TEST ACTION GROUP (JTAG) - In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed. | 03-08-2012 |
20120089878 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead. | 04-12-2012 |
20120102375 | AT-SPEED TEST ACCESS PORT OPERATIONS - This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements. | 04-26-2012 |
20120117435 | PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES - The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure. | 05-10-2012 |
20120124438 | SERIAL I/O USING JTAG TCK AND TMS SIGNALS - The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. | 05-17-2012 |
20120131403 | MULTI-CHIP TEST SYSTEM AND TEST METHOD THEREOF - A multi-chip test system and a method thereof utilize a Complex Programmable Logic Device (CPLD) to be connected in series to multiple chips having a Joint Test Action Group (JTAG) interface for function inspection. The test system includes a device to-be-tested and a control device. The device to-be-tested includes multiple chips, a CPLD, and a second JTAG interface. Each of the chips has a first JTAG interface. The CPLD is coupled to the chips through the first JTAG interfaces. The second JTAG interface is connected to the CPLD. The control device is connected to the second JTAG interface and used for sending a switching instruction to the CPLD. In the test method, firstly, a switching instruction is received to select a chip to-be-tested; then, a test signal is sent to the chip to-be-tested according to the chip to-be-tested; and the chip to-be-tested transfers a test result back to a CPLD according to the test signal. | 05-24-2012 |
20120137186 | METHOD AND APPARATUS FOR POSITION-BASED SCHEDULING FOR JTAG SYSTEMS - A position-based scheduling capability supports interaction between one or more user applications and a scheduler for performing testing via a scan chain of a unit under test. The scheduler receives access requests from one or more user applications, where each access request is a request for access to a segment of the scan chain, respectively. The scheduler determines scheduling of the access requests using a circuit model configured to represent an ordering of the segments of the scan chain. The scheduler may provide the access responses to the user application(s) from which the access requests are received, thereby enabling the user application(s) to issue test operations toward a processor configured to generate test data to be applied to the scan chain. The scheduler may obtain the test operations and send the test operations toward a processor configured to generate test data to be applied to the scan chain. | 05-31-2012 |
20120144254 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 06-07-2012 |
20120144255 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 06-07-2012 |
20120173941 | METHOD, SYSTEM AND PROCESSOR FOR LOADING LOGICAL DEVICES ONLINE - A method, a system, and a processor for loading a logical device online are disclosed. The method for loading a logical device online includes receiving an online loading command; disabling a Joint Test Action Group (JTAG) link of a board on which the logical device is located through a bus between a processor and the logical device according to the online loading command, and enabling a link between an input/output (I/O) interface and a JTAG interface of the logical device through the bus according to the online loading command; and controlling the logical device through the bus so that the logical device is loaded online through the link between the I/O interface and the JTAG interface of the logical device. In this way, the logical device is loaded online without occupying any I/O interface or requiring addition of any I/O device. | 07-05-2012 |
20120192022 | DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller. | 07-26-2012 |
20120198295 | POSITION INDEPENDENT TEST OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers. | 08-02-2012 |
20120198296 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 08-02-2012 |
20120204073 | IEEE 1149.1 INTERPOSER METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack. | 08-09-2012 |
20120210182 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 08-16-2012 |
20120210183 | INTERFACE DEVICE AND METHOD - An interface device is adapted to: in a first mode, in reaction to test signals and corresponding to a test standard, output signals corresponding to the test standard via at least one signal line. In a second mode it is adapted to, in reaction to test signals and corresponding to the test standard, output signals that do not correspond to the test standard via the at least one signal line. | 08-16-2012 |
20120216089 | Integrated Circuit Testing with Power Collapsed - In examples, apparatus and methods are provided for an integrated circuit. The integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit. | 08-23-2012 |
20120216090 | REDUCED SIGNALING INTERFACE METHOD AND APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. | 08-23-2012 |
20120221906 | SCAN-BASED MCM INTERCONNECTING TESTING - A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect. | 08-30-2012 |
20120221907 | HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITS - An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation. | 08-30-2012 |
20120221908 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 08-30-2012 |
20120221909 | SHADOW ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal. | 08-30-2012 |
20120239993 | Method and Apparatus for Fault Injection - The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled fault injection circuit. This type of circuit uses internal scan chains as a way by which a fault injection operation is performed while a system clock is in the off state. Another type of fault injection circuit is a concurrent fault injection circuit. This type of fault injection circuit uses dedicated fault injection scan chains in parallel with or without internal scan chains. Yet another type of fault injection circuit is a hybrid fault injection circuit that uses both clock controlled and concurrent fault injection circuits. Other embodiments are disclosed and still other embodiments would be obvious to those of ordinary skill in the art upon understanding the full scope of the present disclosure. | 09-20-2012 |
20120239994 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 09-20-2012 |
20120246530 | INTERFACE TO FULL AND REDUCE PIN JTAG DEVICES - The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( | 09-27-2012 |
20120260140 | SEMICONDUCTOR TEST SYSTEM AND METHOD - A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test. | 10-11-2012 |
20120266035 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface uses a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that compare test response data within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. | 10-18-2012 |
20120272111 | JTAG Apparatus and Method for Implementing JTAG Data Transmission - A Joint Test Action Group (JTAG) apparatus and a method for implementing JTAG data transmission are disclosed, wherein the JTAG apparatus includes: a processor and a JTAG programmable logic device; and further includes an isolation circuit connected with the processor and pins of the JTAG programmable logic device, wherein the isolation circuit has a register/registers corresponding to the pins of the JTAG programmable logic device; based on a high or low level signal written into the register/registers of the isolation circuit by the processor, the isolation circuit drives the pins of the JTAG programmable logic device, and transmits the JTAG data corresponding to the high or low level signal from the processor to the JTAG programmable logic device. In the scheme of the present invention, the isolation circuit is used to implement protection of a JTAG interface or a serial port of a personal computer connected with the JTAG apparatus. | 10-25-2012 |
20120272112 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES - Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls. | 10-25-2012 |
20120278673 | SEMICONDUCTOR DEVICE AND TEST METHOD THEROF - A semiconductor device includes a clock control unit configured to receive an external test clock signal in a boundary scan test mode and generate a boundary test clock signal in synchronization with an entry time point of the boundary scan test mode, and a plurality of latches configured to receive and store a plurality of data in parallel in a boundary capture test mode and form a boundary scan path to sequentially output the plurality of stored data in the boundary scan test mode in response to the boundary test clock signal. | 11-01-2012 |
20120278674 | INTERPOSER INSTRUMENTATION METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an | 11-01-2012 |
20120284578 | GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS - In a first embodiment a TAP | 11-08-2012 |
20120284579 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 11-08-2012 |
20120284580 | DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM - A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed. | 11-08-2012 |
20120290890 | METHOD OF AND AN ARRANGEMENT FOR AUTOMATICALLY MEASURING ELECTRIC CONNECTIONS OF ELECTRONIC CIRCUIT ARRANGEMENTS MOUNTED ON PRINTED CIRCUIT BOARDS - A method of and an arrangement for determining electric connections at a printed circuit board between boundary-scan compliant circuit terminals of one or more boundary-scan compliant devices. An electronic processing unit retrieves properties of the or each boundary-scan compliant device and a list comprising boundary-scan cells operable as a driver and/or sensor. Based on this list, a boundary-scan cell connected to a circuit terminal is operated as a driver, and at least one other boundary-scan cell connected to another circuit terminal is operated as a sensor. Data from the boundary-scan register, comprising the driver and sensor data, is stored in a storage device. The steps of operating boundary-scan cells as driver and sensor are repeated for a plurality of cells. The data stored are analyzed for determining electric connections. A result of the analysis is presented. | 11-15-2012 |
20120297261 | SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS - Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values. | 11-22-2012 |
20120304029 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 11-29-2012 |
20120317452 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 12-13-2012 |
20120324302 | INTEGRATED CIRCUIT FOR TESTING USING A HIGH-SPEED INPUT/OUTPUT INTERFACE - An integrated circuit configured for testing is described. The integrated circuit includes a high-speed input/output interface. The integrated circuit also includes a test controller coupled to the high-speed input/output interface. The integrated circuit further includes test circuitry coupled to the test controller. The test controller controls the test circuitry based on controller protocol test information from the high-speed input/output interface. | 12-20-2012 |
20120331359 | Mechanism to Instantiate a JTAG Debugger in a Browser - An operating system independent JTAG debugging system implemented to run in a web browser. The software executing in the browser identifies the JTAG enabled components in the target system that is to be tested and automatically downloads the latest versions of the appropriate software and drivers from a test server database, together with any applicable patches and software updates. | 12-27-2012 |
20120331360 | METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits. | 12-27-2012 |
20130019135 | TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY - The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states. | 01-17-2013 |
20130024737 | TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS - A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit. | 01-24-2013 |
20130024738 | METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION - The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure. | 01-24-2013 |
20130031435 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 01-31-2013 |
20130042159 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 02-14-2013 |
20130042160 | SERIAL I/O USING JTAG TCK AND TMS SIGNALS - The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. | 02-14-2013 |
20130047046 | DRAM TEST ARCHITECTURE FOR WIDE I/O DRAM BASED 2.5D/3D SYSTEM CHIPS - A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper. | 02-21-2013 |
20130047047 | 3D STACKED DIE TEST ARCHITECTURE - This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die. | 02-21-2013 |
20130067291 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 03-14-2013 |
20130067292 | Scan Latch with Phase-Free Scan Enable - A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period when the scan control signal is in a state corresponding to a capture cycle. A slave latch in each scan flop may latch a value appearing at the regular data input of the scan flop according to a narrow pulse triggered by the rising edge of the master clock when the scan control signal is in the state corresponding to the capture cycle. The slave latch may latch the data provided by the master latch according to a wide pulse triggered by the rising edge of the master clock when the scan control signal is in a state corresponding to a shift cycle. This may permit toggling the scan control signal during either a high phase or a low phase of the master clock, and may also enable testing the pulse functionality of each scan flop. | 03-14-2013 |
20130073915 | TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT - The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure. | 03-21-2013 |
20130073916 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead. | 03-21-2013 |
20130073917 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed. | 03-21-2013 |
20130080850 | SERIAL SCAN CHAIN IN A STAR CONFIGURATION - A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase. | 03-28-2013 |
20130086441 | DYNAMICALLY SELF-RECONFIGURABLE DAISY-CHAIN OF TAP CONTROLLERS - A self-reconfigurable daisy-chain of TAP controllers includes a main TAP controller and one or more auxiliary TAP controllers. The daisy-chain is dynamically self-reconfigurable in that the main TAP controller can configure and reconfigure the daisy-chain multiple times during the testing of a circuit. A data register within the main TAP controller is associated with a special JTAG instruction. This instruction is usable to enable and disable selected individual ones of the auxiliary TAP controllers. If an auxiliary controller is enabled, then it is made a part of the TDI-to-TDO daisy-chain scan path. If the auxiliary controller is disabled, then it is not a part of the daisy-chain scan path. A disabled controller and its registers are not, however, reset. A disabled controller can continue to supply test signals to the circuit under test. Using this mechanism, test time can be reduced by reducing the amount of shifting through slow controllers. | 04-04-2013 |
20130097466 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 04-18-2013 |
20130097467 | SCAN FRAME BASED TEST ACCESS MECHANISMS - Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation. | 04-18-2013 |
20130103995 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 04-25-2013 |
20130103996 | HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITS - An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation. | 04-25-2013 |
20130124934 | PACKETIZING JTAG ACROSS INDUSTRY STANDARD INTERFACES - Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces. The devices employ processors configured to receive packetized test input data from a tester over a standard communication interface such as a USB or Ethernet port and perform associated testing operations defined by the test input data, such as JTAG-compliant testing. This is facilitated, in part, via use of a bridge and one or more DFx handlers, with the bridge operating as an interface between the DFx handlers and a bus and/or interconnect over which test input and result data is transferred via the standard communication interface. The techniques enable testing such as JTAG testing to be performed on fully-assembled devices and systems without requiring the use of dedicated test or debug ports. | 05-16-2013 |
20130124935 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 05-16-2013 |
20130124936 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 05-16-2013 |
20130139014 | VERIFYING AND DETECTING BOUNDARY SCAN CELLS TO INPUT/OUTPUT MAPPING - In some embodiments, a computer-implemented method includes receiving, in a processor, a device description code identifying components of a device and connections between the components, wherein some of the components and connections form boundary cells used for testing the device. The method can include processing, in the processor, the device description code to determine that the components and the connections meet a standard governing components and connections necessary for the boundary cells. The method can also include traversing the connections between the components to determine that the connections meet the standard, and reporting, via one or more output devices, that the device complies with the standard. | 05-30-2013 |
20130139015 | METHODS AND APPARATUS FOR TESTING MULTIPLE-IC DEVICES - Embodiments of integrated circuits include a first input interconnect, a second input interconnect, an output interconnect, a shift register, a select register, a test access port (TAP) controller, and select register decode circuitry. The TAP controller is coupled to the first input interconnect and the select register, and the TAP controller is configured to shift a select value provided on the first input interconnect into the select register. The select register decode circuitry is configured to control, based on the select value, which of a plurality of test data output signals are provided to the output interconnect, where the plurality of test data output signals includes a first test data output signal and a second test data output signal. The first test data output signal is provided by the shift register, and the second test data output signal is received from a second integrated circuit on the second input interconnect. | 05-30-2013 |
20130139016 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF CONTROLLING THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND INFORMATION PROCESSING SYSTEM - A debug system scans a scan memory element group having a plurality of scan memory elements which are connected in series in a semiconductor integrated circuit device and collects data in the scan memory element group. The semiconductor integrated circuit device has an end code register which is provided between an input terminal and an input side of the scan memory element group and holds an end code, a start code register which is provided between an output terminal and an output side of the scan memory element group and holds a start code, and a scan control circuit which controls shift operations of the scan memory element group, the end code register and the start code register, and outputs scan data to the output terminal. | 05-30-2013 |
20130145226 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 06-06-2013 |
20130151916 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 06-13-2013 |
20130151917 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 06-13-2013 |
20130159800 | Scan Compression Architecture with Bypassable Scan Chains for Low Test Mode Power - This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations. | 06-20-2013 |
20130159801 | ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 06-20-2013 |
20130166975 | APPARATUS FOR PROTECTING AGAINST EXTERNAL ATTACK FOR PROCESSOR BASED ON ARM CORE AND METHOD USING THE SAME - An apparatus for protecting against external attacks for a processor based on an ARM core and a method using the same are provided. A method for protecting against external attacks for a processor based on an ARM core in accordance with an embodiment of the present invention includes: setting up a register using a reset handler, which is executed first within a boot image; generating a control signal for protecting against external attacks using any one of an external debug request signal and an output signal of the register; and blocking a JTAG interface used for JTAG communication with the processor based on the ARM core according to the control signal for protecting against external attacks. | 06-27-2013 |
20130166976 | Diagnosis-Aware Scan Chain Stitching - Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design are analyzed to determine information of potential logic relationship between the scan cells. The information of potential logic relationship between the scan cells may comprise information of fan-in cones for the scan cells. Based at least in part on the information of potential logic relationship between the scan cells, scan chains may be formed. The formation of scan chains may be further based on layout information of the circuit design. The formation of scan chains may be further based on compactor information of the circuit design. | 06-27-2013 |
20130166977 | SECURE LOW PIN COUNT SCAN - A contactless smartcard type integrated circuit needing only two pins for performing a standard ATPG test is disclosed. A scan test may be performed using one pin for the clock and the other pin for the input and input of the scan test data. Additionally, security is enhanced by using an embedded signature generator to avoid observation of the data shifted out. | 06-27-2013 |
20130166978 | INTEGRATED CIRCUIT - An integrated circuit includes a first signal processing circuit in which first combination circuits and scan FFs are connected in an order of a scan FF, a first combination circuit, and a scan FF; a second signal processing circuit including a second combination circuit different from the first combination circuit; a first selection circuit configured to select data from a scan FF on an input side of one first combination circuit or data from an input terminal of the second signal processing circuit, and to output the data to the second combination circuit; and a second selection circuit configured to select data from another first combination circuit different from the one first combination circuit or data from the second combination circuit, and to output the data to the scan FF on an output side of the another first combination circuit. | 06-27-2013 |
20130173978 | MULTIPLE INPUT AND/OR OUTPUT DATA FOR BOUNDARY SCAN NODES - A boundary scan node of a boundary scan chain for testing an associated node of core logic core logic includes a first boundary scan cell having an input that is coupled to a first data output of the core logic. A second boundary scan cell having an output is coupled to a first data input of the core logic. A programmable series connection is arranged to selectively couple an output of the first boundary scan cell to an input of the second boundary scan cell when the boundary scan node is arranged in an internal test mode for the core logic. Test stimulus can be written to the boundary scan node using a data register clock and test results can be read from the boundary scan node using the data register clock. | 07-04-2013 |
20130173979 | HIGH PERFORMANCE COMPACTION FOR TEST RESPONSES WITH MANY UNKNOWNS - A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m07-04-2013 | |
20130179743 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 07-11-2013 |
20130179744 | DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller. | 07-11-2013 |
20130185608 | SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS - Stacked integrated circuits (ICs) having a base component and secondary component are tested. The base component has a scan input pad, a scan output pad, a base scan chain, and a base chain access block including a base chain select multiplexor and a base bypass multiplexor. The secondary component has a secondary scan chain and a secondary chain access block including a secondary chain select multiplexor and a secondary bypass multiplexor. The secondary chain select multiplexor is configured to receive input directly from the base component and another component. The base and secondary chain access blocks are configured to selectively access the base scan chain and/or the secondary scan chain. | 07-18-2013 |
20130198578 | Maximizing Re-Use of External Pins of an Integrated Circuit for Testing - At least one external pin of an integrated circuit (IC) is coupled to receive a first configuration signal used in configuring an internal circuit block for a test designed to uncover faults in the circuit block, and to receive a first test signal during the test. Configuration logic in the IC is designed to generate control data by decoding configuration signals that include the first configuration signal. A test configuration register stores the control data and applies the control data during the test, but is decoupled from the configuration logic prior to commencement of the test. A sequence detector in the IC is designed to detect a reset sequence signifying an end of the test and in response to re-couple the test configuration register to the configuration logic. The number of external pins needed for testing the IC is reduced. | 08-01-2013 |
20130198579 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 08-01-2013 |
20130205180 | FAULT DETECTION SYSTEM, ACQUISITION APPARATUS, FAULT DETECTION METHOD, PROGRAM, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM - It is a purpose of the invention to provide a fault detection system, etc., having improved fault coverage with a reduced number of test patterns to be input to a logic circuit. The fault detection system detects a fault in a logic circuit based on multiple output logic values of the logic circuit after a test input pattern is input. The output logic values are input to the logic circuit as an updated test input pattern. The system comprises: a first acquisition unit which acquires a part of or all of the output logic values; a comparison unit which compares the logic values acquired by the first acquisition unit with those predicted for when there are no faults, or for when there is a specific fault; and a fault judgment unit which judges whether or not there is a fault based on the comparison result obtained by the comparison unit. | 08-08-2013 |
20130212445 | APPARATUS FOR JTAG-DRIVEN REMOTE SCANNING - A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle. | 08-15-2013 |
20130219237 | SCAN CHAIN FAULT DIAGNOSIS - Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell. | 08-22-2013 |
20130227363 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 08-29-2013 |
20130227364 | DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM - A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed. | 08-29-2013 |
20130227365 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 08-29-2013 |
20130232387 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 09-05-2013 |
20130232388 | METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits. | 09-05-2013 |
20130238948 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first register configured to store a first value indicating whether or not a macro is in a state at a first time point, and to update the first value to a second value indicating whether or not the macro is in the state at a second time point after the first time point, and a second register configured to store and retain the first value, and not to update the first value to the second value. | 09-12-2013 |
20130246871 | ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator | 09-19-2013 |
20130246872 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 09-19-2013 |
20130246873 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 09-19-2013 |
20130254605 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 09-26-2013 |
20130254606 | METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION - The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure. | 09-26-2013 |
20130254607 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 09-26-2013 |
20130254608 | IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES - In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals. | 09-26-2013 |
20130262944 | SCAN CHAIN MODIFICATION FOR REDUCED LEAKAGE - A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected. | 10-03-2013 |
20130268816 | Interconnections for Plural and Hierarchical P1500 Test Wrappers - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores.—The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 10-10-2013 |
20130268817 | Fully X-Tolerant, Very High Scan Compression Scan Test Systems And Techniques - Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods. | 10-10-2013 |
20130275826 | Interconnections for Plural and Hierarchical P1500 Test Wrappers - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 10-17-2013 |
20130283111 | SEMICONDUCTOR DEVICE - A semiconductor device includes a scan chain that scans out latch signals of a plurality of latches; a first switch that selects any one of an output signal of a combinational circuit and a signal of the scan chain; a first latch that is inserted into the scan chain and receives an output signal of the first switch; a second latch that receives an output signal of the combinational circuit; and a second switch that selects any one of a latch signal of the first latch and a latch signal of the second latch and supplies the selected one to a combinational circuit in a following stage. | 10-24-2013 |
20130297981 | LOW COST HIGH THROUGHPUT TSV/MICROBUMP PROBE - A first apparatus, such as a die or a semiconductor package, has signal paths extending through the apparatus. The signal paths can include through vias and other components. The signal paths are operable to communicate with a second apparatus when the second apparatus is stacked with the first apparatus. The first apparatus also has pass gates. Each pass gate is configurable in response to a signal, to short a pair of the signal paths to enable substantially simultaneous testing of the signal paths. The pass gates may be configurable to isolate the signal paths during operation of the first apparatus. | 11-07-2013 |
20130305108 | 1149.1 TAP LINKING MODULES - IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 11-14-2013 |
20130305109 | HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITS - An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation. | 11-14-2013 |
20130305110 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 11-14-2013 |
20130305111 | Circuit And Method For Simultaneously Measuring Multiple Changes In Delay - A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple paths, and may be implemented in digital boundary scan to test I/O pin delays. Synchronous to a first frequency, the circuit applies an alternating signal to the paths and samples the paths' output logic values synchronous with a second frequency that is asynchronous and coherent to the first clock frequency. The shift register conveys the samples to a modulo counter that counts the number of samples between consecutive rising or consecutive falling edges in the signal samples from a selected path. Between the two edges, the path or a path characteristic is changed, and the resulting modulo count after the second edge is proportional to the change in delay. The circuit can compare the count, or the difference between counts, to test limits. | 11-14-2013 |
20130305112 | Method and Apparatus for Diagnosing an Integrated Circuit - System and method for diagnosing failures within an integrated circuit is provided. In an embodiment, the apparatus includes a diagnostic cell coupled in series with a buffer chain. The diagnostic cell includes a plurality of logic operators that when activated invert a signal received from the buffer chain. The inversion of the signal from the buffer chain allows the diagnostic cell to determine the location of a failure within an integrated circuit previously determined by a scan chain design for test methodology to contain a failure. | 11-14-2013 |
20130311841 | SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS - Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values. | 11-21-2013 |
20130311842 | TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT - The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure. | 11-21-2013 |
20130318410 | Removing Scan Channel Limitation on Semiconductor Devices - A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals. | 11-28-2013 |
20130318411 | SCAN TEST METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test. | 11-28-2013 |
20130318412 | TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY - The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states. | 11-28-2013 |
20130318413 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead. | 11-28-2013 |
20130326298 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 12-05-2013 |
20130332786 | Test Data Volume Reduction Based On Test Cube Properties - Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals. | 12-12-2013 |
20130332787 | ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA - Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state. | 12-12-2013 |
20130339812 | Dynamic Device Identification for Making a JTAG Debug Connection with a Internet Browser - An operating system independent JTAG debugging system implemented to run in a web browser. The software executing in the browser identifies the JTAG enabled components in the target system that is to be tested, and automatically downloads the latest versions of the appropriate software, JTAG drivers and configuration information from a test server. | 12-19-2013 |
20130346815 | REMOTE BOUNDARY SCANNING - Techniques related to remotely boundary scanning of an integrated circuit embedded in a target computing system are disclosed herein. In an example, a host computing system includes a first peripheral port and a second peripheral port. A port-to-port boundary scan assembly is to interface boundary scan data between the first and the second peripheral ports. Thereby the boundary scan data can be routed from the second peripheral bus to the target computing system via a network port at the host computing system. | 12-26-2013 |
20130346816 | METHOD AND APPARATUS FOR TESTING I/O BOUNDARY SCAN CHAIN FOR SOC'S HAVING I/O'S POWERED OFF BY DEFAULT - Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology. | 12-26-2013 |
20130346817 | Method for controlling a state machine - A method and a system for controlling a state machine are described. In the method, a script is used via which each arbitrary path in the state machine. The script is created using a language which includes the “data” command, the “data” command allowing reading and writing of data. | 12-26-2013 |
20130346818 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 12-26-2013 |
20140006887 | On-Chip Probe Circuit for Detecting Faults in an FPGA | 01-02-2014 |
20140006888 | CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES | 01-02-2014 |
20140013174 | IEEE 1149.1 INTERPOSER METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack. | 01-09-2014 |
20140013175 | PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES - The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure. | 01-09-2014 |
20140013176 | ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator | 01-09-2014 |
20140026007 | COMMANDED JTAG TEST ACCESS PORT OPERATIONS - The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device. | 01-23-2014 |
20140032986 | SYSTEM AND METHOD FOR PERFORMING SCAN TEST - A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided. | 01-30-2014 |
20140040688 | LOW POWER SCAN FLIP-FLOP CELL - A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption. | 02-06-2014 |
20140040689 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 02-06-2014 |
20140040690 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 02-06-2014 |
20140040691 | POSITION INDEPENDENT TESTING OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers. | 02-06-2014 |
20140047293 | SEMICONDUCTOR CIRCUIT AND METHODOLOGY FOR IN-SYSTEM SCAN TESTING - A semiconductor circuit comprising a digital circuit portion, which comprises a combinatorial logic block. The semiconductor circuit further comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion involves, using the scan chain, writing bit values to inputs of the individually addressable scan control registers, and reading bit values from at least one output of an individually addressable scan control register. The method and semiconductor circuit allow thorough testing and diagnosing of failing semiconductor devices, including core logic thereof, while mounted on a printed circuit board. | 02-13-2014 |
20140068362 | CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES - A circuit includes a plurality of scan chains each including a plurality of scan blocks. Each scan block includes a storage element and a switching device having an output directly coupled to an input of the storage element. The switching device has a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed and a second input configured to receive one of a function logic output signal or a scan input signal. The switching device is configured to selectively couple the first input or the second input to the input of the storage element. | 03-06-2014 |
20140075255 | DEBUGGING CONTROL SYSTEM USING INSIDE CORE EVENT AS TRIGGER CONDITION AND METHOD OF THE SAME - A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition and a search range of the clock cycle according to internal states of a core under debug. Pause clock and recover clock of each clock cycle within the search range. Retrieve data of scan chains of the core under debug by a shift buffer during the clock pausing. Next combine data of the scan chains by a trigger comparator circuit to form trigger signals and check whether the trigger signals satisfy the trigger condition. If the trigger condition is satisfied or the trigger signal is over the search range, the clock is paused continuingly and internal states of the scan chains of the core under debug are output otherwise the core under debug is recovered. | 03-13-2014 |
20140082441 | 3D TAP AND SCAN PORT ARCHITECTURES - This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure. | 03-20-2014 |
20140082442 | GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS - In a first embodiment a TAP | 03-20-2014 |
20140082443 | ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA ABSTRACT - Scan testing of plural target electrical circuits, such as circuits | 03-20-2014 |
20140082444 | METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits. | 03-20-2014 |
20140082445 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 03-20-2014 |
20140089749 | APPARATUS FOR JTAG-DRIVEN REMOTE SCANNING - A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle. | 03-27-2014 |
20140095950 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 04-03-2014 |
20140101500 | CIRCUITS AND METHODS FOR FUNCTIONAL TESTING OF INTEGRATED CIRCUIT CHIPS - Circuits and methods are provided for debugging an integrated circuit. An integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The scan test circuitry includes scan chains with scan cells interspersed throughout the core circuitry. The scan control circuitry controls the scan test circuitry to scan test the core circuitry. The debug control circuitry utilizes the scan test circuitry and controls the scan control circuitry to debug failure conditions of the integrated circuit during normal use. The scan control circuitry applies a debug clock signal to a clock port of each scan cell of a given scan chain to store data values that are generated by the core circuitry into the scan cells. The scan control circuitry controls the scan test circuitry to scan shift out the stored data values generated by the core circuitry during the debug process. | 04-10-2014 |
20140101501 | SCAN TEST CIRCUITRY CONFIGURED TO PREVENT VIOLATION OF MULTIPLEXER SELECT SIGNAL CONSTRAINTS DURING SCAN TESTING - An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing. The multiplexer may be, for example, a one-hot multiplexer for which the select signal constraint indicates that only one of the select signal inputs should receive a logic high select signal at a particular time. | 04-10-2014 |
20140101502 | FALLING CLOCK EDGE JTAG BUS ROUTERS - The disclosure describes a novel method and apparatus for allowing a controller to access a bus router using a communication occurring in response to one edge of a clock to select one or more devices for access using a communication occurring on the opposite edge of the clock. Additional embodiments are also provided and described in the disclosure. | 04-10-2014 |
20140101503 | SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS - Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values. | 04-10-2014 |
20140101504 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 04-10-2014 |
20140108876 | PROCESSOR SWITCHABLE BETWEEN TEST AND DEBUG MODES - A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP. | 04-17-2014 |
20140108877 | BOUNDARY SCAN TEST INTERFACE CIRCUIT - The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and M are positive integers, and M is smaller than N. The test interfacing module is coupled to the test input pads. The test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads. The test output pads are coupled to output pins of the logical gates in the test interfacing module. | 04-17-2014 |
20140115412 | SCAN CHAIN FAULT DIAGNOSIS - Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell. | 04-24-2014 |
20140115413 | FAULT DICTIONARY BASED SCAN CHAIN FAILURE DIAGNOSIS - A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified. | 04-24-2014 |
20140122951 | SCAN TEST OF DIE LOGIC IN 3D ICs USING TSV PROBING - A test architecture for 3D ICs is provided in which Through-Silicon-Vias and die logic can be tested pre-bonding dies in the stack for the 3D ICs. Post-bond scan test architecture is reconfigured to be accessed during pre-bond testing through using stratigically placed MUXs and TSVs. By connecting post-bond architecture including scan flops and boundary registers to gated scan flops used in TSV testing, an internal chain of scan flops such as typically used in post-bond testing can be selectively connected to gated scan flops connected to one end of each TSV for pre-bond testing of the internal logic through the TSVs. | 05-01-2014 |
20140122952 | BOUNDARY SCAN CHAIN FOR STACKED MEMORY - A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain. | 05-01-2014 |
20140122953 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 05-01-2014 |
20140129886 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 05-08-2014 |
20140136914 | HIGHLY SECURE AND EXTENSIVE SCAN TESTING OF INTEGRATED CIRCUITS - In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register. | 05-15-2014 |
20140143621 | SCAN CIRCUITRY FOR TESTING INPUT AND OUTPUT FUNCTIONAL PATHS OF AN INTEGRATED CIRCUIT - An integrated circuit comprises scan test circuitry, additional circuitry subject to testing utilizing the scan test circuitry, and control circuitry associated with the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells, and the associated control circuitry is coupled to at least a given one of a primary input of the integrated circuit and a primary output of the integrated circuit. The scan test circuitry is configurable by the control circuitry so as to permit testing of both an input functional path associated with the given one of the primary input and the primary output and an output functional path associated with the given one of the primary input and the primary output. | 05-22-2014 |
20140143622 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 05-22-2014 |
20140149812 | SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells. The scan test circuitry further comprises control circuitry comprising first switching elements configured to control selective application of respective scan input signals to respective scan inputs of respective ones of the plurality of scan chains and second switching elements configured to control selective application of a shift enable signal to respective shift enable inputs of the respective ones of the plurality of scan chains. By appropriate control of the switching elements using test data register bits or other scan chain specific control signals, one or more debug modes can be supported by the scan test circuitry of the integrated circuit. | 05-29-2014 |
20140149813 | TEST CIRCUIT HAVING SCAN WARM-UP - A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch. | 05-29-2014 |
20140149814 | Isolating Failing Latches Using a Logic Built-In Self-Test - A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out. | 05-29-2014 |
20140149815 | SYSTEM AND METHOD FOR PROGRAMMING CHIPS ON CIRCUIT BOARD THROUGH BOUNDARY SCAN TECHNOLOGY - A system and a method for programming chips on circuit board through boundary scan technology are provided. Each chip and a Joint Test Action Group (JTAG) interface on a target circuit board are connected in series according to a boundary scan technology to form a boundary scan chain. A read and write device selects a corresponding chip according to programming data, pushes the programming data to the selected chip through the JTAG interface by using the boundary scan technology to perform programming, thereby achieving the technical effects of simplifying the programming of different chips on circuit board and enhancing the efficiency of programming chips. | 05-29-2014 |
20140157070 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 06-05-2014 |
20140164859 | Dynamic Design Partitioning For Scan Chain Diagnosis - Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers. | 06-12-2014 |
20140181603 | METHOD AND APPARATUS FOR TUNING SCAN CAPTURE PHASE ACTIVITY FACTOR - A method and apparatus for tuning the activity factor of a scan capture phase is described. In one example an activity factor is determined for a die to be tested. The die may be isolated or part of a wafer. A structural scan test is modified to run with an activity factor based on the determined activity factor. The modified structural scan test is run and the die is characterized based on the test. | 06-26-2014 |
20140181604 | CHANNEL CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal. | 06-26-2014 |
20140181605 | ASYNCHRONOUS PROGRAMMABLE JTAG-BASED INTERFACE TO DEBUG ANY SYSTEM-ON-CHIP STATES, POWER MODES, RESETS, CLOCKS, AND COMPLEX DIGITAL LOGIC - An asynchronous debug interface is disclosed that allows TAG agents, JTAG-based debuggers, firmware, and software to debug, access, and override any functional registers, interrupt registers, power/clock gating enables, etc., of core logic being tested. The asynchronous debug interface works at a wide range of clock frequencies and allows read and write transactions to take place on a side channel, as well as within the on chip processor fabric without switching into a debug or test mode. The asynchronous debug interface works with two-wire and four-wire JTAG controller configurations, and is compliant with IEEE standards, such as 1149.1, 1149.7, etc., and provides an efficient and seamless way to debug complex system-on-chip states and system-on-chip products. | 06-26-2014 |
20140181606 | DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller. | 06-26-2014 |
20140181607 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a scan test port. The process maintains the state machine in an IDLE 1 state while receiving a scan test port capture signal and transitions the state machine to an IDLE 2 state when receiving a scan test port shift signal. The process then transitions the state machine to a SEQUENCE 1 state, then to a SEQUENCE 2 state, and then to a SEQUENCE 3 state when receiving sequential scan test port capture signals. The state machine then transitions to an UNLOCK TAP state and then back to the IDLE 1 state when receiving sequential scan test port shift signals on the test mode select/capture select lead. | 06-26-2014 |
20140189452 | SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE LOCAL LEVEL FOR SCAN BASED TESTS - A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, wherein each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, wherein each partition receives a respective one of the plurality of second clock signals and wherein the plurality of second clock signals are staggered wherein each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency. | 07-03-2014 |
20140189453 | HIGH DENSITY LOW POWER SCAN FLIP-FLOP - A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate coupled to a tri-stated AND gate. A tri-state inverter is coupled to an output of the master latch and a slave latch is configured to receive an output of the tri-state inverter. A delay element is coupled to the slave latch, where the delay element is configured to delay a first output of the slave latch in response to the scan enable to generate a dedicated scan output. | 07-03-2014 |
20140201583 | System and Method For Non-Intrusive Random Failure Emulation Within an Integrated Circuit - The apparatus and methods allow random hardware failure emulation of an integrated circuit (IC) by emulation of potential defects to enable behavior evaluation of the rest of the design in such situation. This emulation can non-intrusively address multiple points of failure. The emulation is performed in a pseudo-functional mode in order to evaluate the IC behavior in its standard functional mode. The system allows creation of a failure, and tracking both the detection of this failure and the required time for this detection. The system further allows generation of a failure in different points of the IC, on a single or multipoint failure approaches. Failure detection and correction mechanisms for a product life cycle are therefore provided. In an embodiment the system checks the conformity of the safety function of an IC, and makes sure the safety control logic behaves as expected in case of data corruption in any register. | 07-17-2014 |
20140201584 | SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIATED RESET MULTIPLEXING CIRCUITRY - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises control circuitry configured to control selective application of at least a particular one of a plurality of reset signals to reset inputs of at least a subset of the scan cells of the scan chain. For example, the control circuitry may comprise a first reset multiplexer configured to select between a first functional mode reset signal and a first scan mode reset signal for application to reset inputs of respective scan cells of the scan chain, and an additional multiplexer configured to select between an additional functional mode reset signal and an additional scan mode reset signal for application to reset inputs of respective internal flip-flops of the additional circuitry. | 07-17-2014 |
20140208175 | AT-SPEED SCAN TESTING OF CLOCK DIVIDER LOGIC IN A CLOCK MODULE OF AN INTEGRATED CIRCUIT - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated clock divider logic, and the scan test circuitry is configured to permit testing of at least a portion of the clock divider logic. A given scan chain of the scan test circuitry may comprise first and second scan cells, with the first scan cell having a scan output coupled to a scan input of the second scan cell, and the second scan cell having a data input driven by an output of the clock divider logic. | 07-24-2014 |
20140208176 | SCAN CHAIN IN AN INTEGRATED CIRCUIT - In an embodiment, a scannable storage element includes an input circuit for providing a first signal at first node based on a data input and a scan input, where the scan input is of pull-up logic in functional mode. The input circuit includes a first pull-up path comprising a switch receiving data input and a switch receiving scan enable input, and second pull-up path comprising a switch receiving scan input, first pull-down path comprising a switch receiving the scan enable input and a switch receiving the scan input, and second pull-down path comprising a switch receiving the data input. The storage element includes a shifting circuit configured to provide a second signal in response to the first signal at second node, and a scan output buffer coupled to the second node and configured to provide a scan output at a scan output terminal in response to the second signal. | 07-24-2014 |
20140215282 | 1149.1 TAP LINKING MODULES - IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 07-31-2014 |
20140215283 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 07-31-2014 |
20140223249 | SYSTEM AND METHOD FOR SCAN CHAIN RE-ORDERING - A system for re-ordering a scan chain of an electronic circuit design using an electronic design automation (EDA) tool includes a processor and a memory in communication with the processor. The scan chain includes a plurality of scan cells. All connections of the scan chain are disconnected. An output port of a first scan cell is connected to input ports of other scan cells to form a first set of scan cell combinations. A first scan cell combination is selected from the first set of scan cell combinations based on weighted averages of ordering parameters of each of the first set of scan cell combinations. The process is repeated to re-order the scan chain. | 08-07-2014 |
20140223250 | INTEGRATED CIRCUIT TESTING WITH POWER COLLAPSED - Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain. | 08-07-2014 |
20140237310 | Test Architecture for Characterizing Interconnects in Stacked Designs - Aspects of the invention relate to ring-oscillator-based test architecture for characterizing interconnects in stacked designs. The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by control circuitry. | 08-21-2014 |
20140237311 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 08-21-2014 |
20140250342 | AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 09-04-2014 |
20140258798 | TEST CONTROL POINT INSERTION AND X-BOUNDING FOR LOGIC BUILT-IN SELF-TEST (LBIST) USING OBSERVATION CIRCUITRY - Test control point insertion and x-bounding for Logic Built-In Self-Test (LBIST) using observation circuitry. In some embodiments, LBIST circuitry may include a plurality of test control circuits coupled to a scan chain of a Circuit Under Test (CUT), and a plurality of observation circuits coupled to the test control circuits, each of the plurality of observation circuits including one or more latch devices configured to drive a respective one of the plurality of test control circuits. In other embodiments, a method of testing an integrated circuit may include issuing an instruction that a plurality of observation circuits and a plurality of input/output (I/O) control circuits within the integrated circuit enter a test mode, and providing, one or more test patterns to a selected one or more of a plurality of scan chains within the integrated circuit and to each of the plurality of observation circuits. | 09-11-2014 |
20140258799 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 09-11-2014 |
20140281774 | Two-Level Compression Through Selective Reseeding - A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance. | 09-18-2014 |
20140281775 | System on a Chip FPGA Spatial Debugging Using Single Snapshot - A method for performing on-chip spatial debugging of a user circuit programmed into a user-programmable integrated circuit includes halting an internal clock driving synchronous logic elements in the integrated circuit and reading the states of all synchronous logic elements programmed into the integrated circuit while the internal clock is halted. An interrupt to an embedded processor in the integrated circuit running a user application can also be generated. The output of at least one synchronous logic element can be forced to a desired state while the internal clock is halted. The clock can then be restarted or stepped. | 09-18-2014 |
20140289576 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR SELF TEST OF SEMICONDUCTOR INTEGRATED CIRCUIT - Certain embodiments provide a semiconductor integrated circuit comprising: a logic circuit including combination circuits and first flip-flops; plural selectors for respective first flip-flops configured to switch between first paths from the combination circuits and second paths from previous stage flip-flops of the first flip-flops; plural scan chains in the logic circuit, each of the scan chains configured to have the second path activated by the selectors; a pattern generator configured to generate patterns for test for the scan chains; a test control circuit configured to control the pattern generator and the plural selectors, the test control circuit performing self test; and plural setting terminals configured to set logic values individually in a combination of a part of second flip-flops which are representative of a logic pattern and of the first flip-flops in the logic circuit, the setting flip-flops being representative of a logic pattern. | 09-25-2014 |
20140289577 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 09-25-2014 |
20140289578 | SCAN CIRCUIT HAVING FIRST SCAN FLIP-FLOPS AND SECOND SCAN FLIP-FLOPS - A scan circuit includes first scan flip-flops each including a first logic circuit to receive a plurality of control signals in addition to a scan input signal and a data input signal, and second scan flip-flops each including a second logic circuit to receive the plurality of control signals in addition to a scan input signal and a data input signal, wherein the first scan flip-flops and the second scan flip-flops are connected in series, and the plurality of control signals include only a one-bit reset signal and control signals whose purpose is other than an initialization purpose, and wherein the plurality of control signals are set to a predetermined combination of logic values to cause each of the first scan flip-flops to be initialized to “0” by the first logic circuit and each of the second scan flip-flops to be initialized to “1” by the second logic circuit. | 09-25-2014 |
20140304563 | POSITION INDEPENDENT TESTING OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers. | 10-09-2014 |
20140304564 | SCAN FRAME BASED TEST ACCESS MECHANISMS - Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation. | 10-09-2014 |
20140310565 | SCAN COMPRESSION RATIO BASED ON FAULT DENSITY - A processor-implemented method for determining scan compression ratio based on fault density is provided. The processor-implemented method may include calculating, by a processor, a fault density value for each of a plurality of partitions of an integrated circuit. The fault density is computed by the processor based on a ratio of a total number of faults per partition to a total number of flip-flops per partition. The processor-implemented method further includes the processor determining a compression ratio for each of the plurality of partitions based on the fault density value for each of the plurality of partitions and applying the compression ratio to each of the plurality of the partitions of the integrated circuit. | 10-16-2014 |
20140325299 | TESTING SYSTEM AND TESTING METHOD FOR MOTHERBOARD - A testing system includes a computer, a testing circuit board, and a motherboard. The testing circuit board includes a programmable logic device connected to the computer. The programmable logic device includes a predetermined signal. The programmable logic device is used to output an excitation signal to the motherboard. The motherboard is used to generate a back signal according to the excitation signal. The programmable logic device is used to analyze whether the back signal is consistent with the predetermined signal. The computer is used to display a testing result output by the programmable logic device. The disclosure further offers a testing method. | 10-30-2014 |
20140331097 | MANAGING REDUNDANCY REPAIR USING BOUNDARY SCANS - An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode. | 11-06-2014 |
20140331098 | SENSOR ENHANCEMENT THROUGH ALGORITHMIC ACQUISITION USING SYNCHRONIZATION WITH A SCAN GENERATOR - A system and method for image enhancement associated with scan generators is provided. For example, a source stimulates a device under test (DUT) at electrical interconnects. An internal clock of the DUT is synchronized with the scan rate of the source to reduce the noise of the output signal and enhance a resultant image. A phase adjustment is effected to further reduce the noise in the signal. The synchronization and the phase adjustment seek to ensure that the data is collected at uniform times relative to the reference signal and thereby reduce the noise introduced into the system, by such offsets. Post-scan processing increases the signal-to-noise ratio through averaging techniques. Using a pixel overlay algorithm the averaged data is transformed into a 2-D array and the image of the DUT reconstructed. | 11-06-2014 |
20140337678 | SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS - Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values. | 11-13-2014 |
20140337679 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 11-13-2014 |
20140344636 | Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit - A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. | 11-20-2014 |
20140351665 | INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES - The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( | 11-27-2014 |
20140359386 | SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION - A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection. | 12-04-2014 |
20140359387 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 12-04-2014 |
20140359388 | CORE CIRCUIT TEST ARCHITECTURE - A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate. | 12-04-2014 |
20140365839 | ELECTRONIC CONTROL UNIT HAVING INTEGRATED CIRCUIT ELEMENT AND STANDALONE TEST UNIT FOR INTEGRATED CIRCUIT ELEMENT - There is provided a low-cost electronic control unit that is capable of performing its hardware check every start and stop of the electronic control unit. A monitoring and control circuit section that is an integrated circuit element built in the electronic control unit includes a self-test circuit configured with a built-in self-test control block, scan chain circuits and mask circuitry, and performs a self-test using the built-in self-test control block and a partial combination of the scan chain circuits at start of the operation. In the shipment inspection of the integrated circuit element alone, an external test is performed by a checker microprocessor using an entire combination of the scan chain circuits. Thus, the electronic control unit of low-cost configuration is capable of performing a scan test by making use of part of the scan chain circuits designed for the component inspection. | 12-11-2014 |
20140365840 | Logic Built-In Self-Test with High Test Coverage and Low Switching Activity - The test circuitry according to various aspects of the presently disclosed techniques comprises: low-toggling pseudo-random test pattern generation circuitry, wherein the low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator; scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry; background chains configurable to shift in a background test pattern; and weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern. | 12-11-2014 |
20140372819 | Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology - Aspects of the invention relate to generating scan chain configurations for test-per-clock based on circuit topology. With various implementations of the invention, weight vectors between scan chains in a circuit are first determined. Based on the weight vectors, a scan chain configuration is generated by assigning some scan chains in the scan chains to a stimuli group and some other scan chains in the scan chains to a compacting group. Here, the stimuli group comprises scan chains to operate in a shifting-launching mode, and the compacting group comprises scan chains to operate in a capturing-compacting-shifting mode. | 12-18-2014 |
20140372820 | Fault-Driven Scan Chain Configuration For Test-Per-Clock - Aspects of the invention relate to using fault-driven techniques to generate scan chain configurations for test-per-clock. A plurality of test cubes that detect a plurality of faults are first generated. Scan chains for loading specified bits of the test cubes are then assigned to a stimuli group. From the plurality of test cubes, a test cube that detects a large number of faults that do not propagate exclusively to scan chains in the stimuli group is selected. One or more scan chains that are not in the stimuli group and are needed for observing the large number of faults are assigned to a compacting group. The number of scan chains either in the compacting group or in both of the compacting group and the stimuli group may be limited to a predetermined number. | 12-18-2014 |
20140372821 | Scan Chain Stitching For Test-Per-Clock - Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively. | 12-18-2014 |
20140372822 | Scheme for Masking Output of Scan Chains in Test Circuit - A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated. | 12-18-2014 |
20150019928 | SEMICONDUCTOR TEST SYSTEM AND METHOD - A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test. | 01-15-2015 |
20150019929 | ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA - Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state. | 01-15-2015 |
20150026533 | WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals. | 01-22-2015 |
20150026534 | INTERPOSER INSTRUMENTATION METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer. | 01-22-2015 |
20150033088 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. | 01-29-2015 |
20150039955 | Systems and methods for Analog, Digital, Boundary Scan, and SPI Automatic Test Equipment - An Integrated Automatic Test Equipment that provides the test program development environments and execution of test programs for the assembled Print Circuit Boards. This test equipment includes Microsoft Windows PC executable programs, a digital/analog/SPI test controller, and a JTAG controller for boundary scan test. Both test controllers are attached to PC via USB ports for receiving test commands and replying test results. Test program development allows user to specify the rest stimulus and the expected test response for both digital test and boundary scan test. In addition to perform standalone tests, digital tester and boundary scan tester can drive and detect test signals to and from each other. The combination of digital test function and boundary scan test function can increase PCB production line test fault coverage. | 02-05-2015 |
20150046763 | Apparatus and Method for Controlling Internal Test Controllers - An apparatus and method for controlling a test controller is disclosed. An apparatus includes test controllers of a first type configured to operate according to a first protocol and test controllers of a second type configured to operate according to a second protocol. A test controller of the second type may be associated with one of the test controllers of the first type, with the former controlling the latter. The test controllers of the second type may each control associated ones of the test controllers of the second type in parallel and independently of one another. | 02-12-2015 |
20150052410 | SYSTEM ON CHIP FOR DEBUGGING A CLUSTER REGARDLESS OF POWER STATE OF THE CLUSTER, METHOD OF OPERATING THE SAME, AND SYSTEM HAVING THE SAME - A system on chip includes a debugging controller, a plurality of clusters, and a power management unit (PMU). The debugging controller is included in a first power domain and a joint test action group (JTAG) interface is included in the first power domain. Each of the clusters is included in at least second power domain different from the first power domain. The PMU is configured to release a powered-off state of the debugging controller in response to a debugging request signal output from the JTAG interface. | 02-19-2015 |
20150052411 | APPARATUS FOR AT-SPEED TESTING, IN INTER-DOMAIN MODE, OF A MULTI-CLOCK-DOMAIN DIGITAL INTEGRATED CIRCUIT ACCORDING TO BIST OR SCAN TECHNIQUES - An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer. | 02-19-2015 |
20150052412 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 02-19-2015 |
20150058688 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 02-26-2015 |
20150058689 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 02-26-2015 |
20150067425 | INTEGRATED CIRCUIT (IC) FOR RECONSTRUCTING VALUES OF FLIP-FLOPS CONNECTED IN A SCAN-CHAIN BY USING A JOINT TEST ACTION GROUP (JTAG) INTERFACE, A METHOD OF OPERATING THE IC, AND DEVICES HAVING THE IC - An integrated circuit (IC) includes an on-chip logic that includes an input terminal, an output terminal, and a plurality of synchronizing circuits connected in a scan-chain; a test data in (TDI) line; a test data out (TDO) line connected to the output terminal; and a test access port (TAP) controller that transmits, to the input terminal, data output from one of a plurality of data sources, the data sources including the TDI line and the output terminal, in response to one or more selection signals. | 03-05-2015 |
20150067426 | PACKET BASED INTEGRATED CIRCUIT TESTING - Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system. | 03-05-2015 |
20150067427 | GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS - In a first embodiment a TAP | 03-05-2015 |
20150074477 | CONTROL TEST POINT FOR TIMING STABILITY DURING SCAN CAPTURE - A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation. | 03-12-2015 |
20150074478 | METHOD FOR SCAN TESTING THREE-DIMENSIONAL CHIP - A method for scan testing a three-dimensional chip, comprising: establishing a scan forest structure for the three-dimensional chip; generating a first test set and a plurality of test periods, and dividing the first test set into a plurality of test subsets; distributing test vectors in the plurality of test subsets into the plurality of test periods; obtaining a current hotspot of the three-dimensional chip; ranking the plurality of test subsets in accordance with an order of temperature rising values from small to large to obtain a test vector strategy; selecting the test subsets corresponding to the temperature rising values less than a temperature threshold from the plurality of test subsets according to the test vector strategy, so as to generate a second test set; and applying the second test set to the scan forest structure, and updating the current hotspot of the three-dimensional chip. | 03-12-2015 |
20150074479 | METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits. | 03-12-2015 |
20150082109 | DETECTING DEFECTS IN A PROCESSOR SOCKET - A socket can include a plurality of pins. The socket may be tested to determine if there are any faults or defects. For example, it can be determined whether any of the plurality of pins is bent or missing. | 03-19-2015 |
20150082110 | 3D STACKED DIE TEST ARCHITECTURE - This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die. | 03-19-2015 |
20150089313 | HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITSGB - An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation. | 03-26-2015 |
20150089314 | POSITION INDEPENDENT TESTING OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers. | 03-26-2015 |
20150095730 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 04-02-2015 |
20150095731 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 04-02-2015 |
20150100841 | LINEAR DECOMPRESSOR WITH TWO-STEP DYNAMIC ENCODING - Methods and apparatuses for generating compressed test data for use by a tester, decompressing the test data during test, and routing the decompressed test data into a set of scan chains within a circuit under test are described. | 04-09-2015 |
20150106672 | CIRCUIT FOR TESTING INTEGRATED CIRCUITS - An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode. | 04-16-2015 |
20150113343 | SEMICONDUCTOR DEVICE, TEST STRUCTURE OF THE SEMICONDUCTOR DEVICE, AND METHOD OF TESTING THE SEMICONDUCTOR DEVICE - A semiconductor device, a test structure of the semiconductor device, and a method of testing the semiconductor device are provided. The test structure including a first pad and a second pad being separated from each other, and a first test element and a second test element connected between the first pad and the second pad, a first value of a characteristic parameter of the first test element being different from a second value of the characteristic parameter of the second test element, may be provided. | 04-23-2015 |
20150113344 | TESTING METHOD, TESTING APPARATUS AND CIRCUIT FOR USE WITH SCAN CHAINS - A scan chain includes a plurality of scan chain blocks coupled together in series and reference circuitry inserted before one of the plurality of scan chain blocks. The reference circuitry, in a scan mode of operation, receives a scan input signal. In a test data capture mode of operation, the reference circuitry receives a known test signal value, and, in a scan out mode of operation, outputs the known test signal value to the one scan chain block of the plurality of scan chain blocks. | 04-23-2015 |
20150113345 | SCAN FLIP-FLOP AND ASSOCIATED METHOD - Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit. | 04-23-2015 |
20150113346 | ELECTRONIC CIRCUIT HAVING SERIAL LATCH SCAN CHAINS - The invention relates to an electronic circuit ( | 04-23-2015 |
20150113347 | COMMANDED JTAG TEST ACCESS PORT OPERATIONS - The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device. | 04-23-2015 |
20150128002 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 05-07-2015 |
20150135029 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 05-14-2015 |
20150143190 | PARTIAL SCAN CELL - An integrated circuit | 05-21-2015 |
20150143191 | SHADOW ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal. | 05-21-2015 |
20150149844 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed. | 05-28-2015 |
20150149845 | DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM - A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed. | 05-28-2015 |
20150293172 | Method and Apparatus for Connecting Debug Interface to Processing Circuits Without Sideband Interface - An integrated circuit (IC) having a debug access port coupled to a processing circuit without a dedicated sideband interface is disclosed. In one embodiment, an IC includes a processor circuit and a DAP. The IC also includes a communications fabric over which communications transactions may be conveyed between the various functional circuits of the IC using a fabric protocol. Both the DAP and the processing circuit are coupled to the communications fabric. The IC also includes a translation circuit coupled between the processing circuit and the communications fabric. The translation circuit may translate transactions conveyed between the processing circuit and the DAP from or to a debug protocol to or from the fabric protocol. Thus, the DAP and the processing circuit may communicate according to the debug protocol without a dedicated sideband coupled therebetween. | 10-15-2015 |
20150293173 | SEMICONDUCTOR DEVICE, DIAGNOSTIC TEST, AND DIAGNOSTIC TEST CIRCUIT - Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device | 10-15-2015 |
20150309116 | ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator | 10-29-2015 |
20150316612 | GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS - In a first embodiment a TAP | 11-05-2015 |
20150323594 | MONITORING ON-CHIP CLOCK CONTROL DURING INTEGRATED CIRCUIT TESTING - The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer. | 11-12-2015 |
20150323595 | SYSTEM FOR REDUCING TEST TIME USING EMBEDDED TEST COMPRESSION CYCLE BALANCING - An apparatus for reducing test time is disclosed. The apparatus includes a processor operable to execute one or more modules to cause the processor to receive operational parameters associated with a first scan chain grouping circuitry and a second scan chain grouping circuitry of an integrated circuit design. The operational parameters include a number of initialization cycles of a first test signal selected for the first scan chain grouping circuitry, a number of initialization cycles of a second test signal selected for the second scan chain grouping circuitry, and a sum for a total number of cycles for the first test signal. The processor also determines a scan chain length for one of the first scan chain grouping circuitry or the second scan chain grouping circuitry based upon the operation parameters such that the total number of cycles of the first signal and the second signal are the same. | 11-12-2015 |
20150323596 | METHOD AND APPARATUS FOR TEST TIME REDUCTION USING FRACTIONAL DATA PACKING - An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency. | 11-12-2015 |
20150323597 | Low Power Testing Based On Dynamic Grouping Of Scan - Aspects of the disclosed technology relate to low power testing. A low power test circuit comprises a test stimulus source, a controller; and a grouping and selection unit. The grouping and selection unit has inputs coupled to the test stimulus source and the controller and has outputs coupled to a plurality of scan chains. The grouping and selection unit is configured to dynamically group scan chains in the plurality of scan chains into a plurality of scan chain groups and to selectively output either original test pattern values generated by the test stimulus source or a constant value to each scan chain group in the plurality of scan chain groups based on control signals received from the controller. | 11-12-2015 |
20150323598 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 11-12-2015 |
20150323599 | ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA - Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state. | 11-12-2015 |
20150331043 | SYSTEM-ON-CHIP SECURE DEBUG - A system on chip (SOC) includes a policy generator to identify lifecycle data that identifies a lifecycle of the SOC and identify authentication data that identifies a particular user that is to debug the SoC. A particular policy is determined based on the lifecycle and identification of the particular user, and policy data is sent to at least one block of the SoC, the policy data identifying the particular policy. Debug access at the block is based on the particular policy. | 11-19-2015 |
20150331044 | SCAN FLIP-FLOP CIRCUIT WITH LOS SCAN ENABLE SIGNAL - A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a Launch On Shift (LOS) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the LOS signal, and generates an intermediate output signal that is an inherent LOS scan enable signal. The multiplexer receives the test input signal and the intermediate output signal, and outputs the test input signal. The flip-flop circuit receives the test input signal as a second input signal, the clock signal, and the reset signal, and generates the output signal. | 11-19-2015 |
20150331045 | COMMANDED JTAG TEST ACCESS PORT OPERATIONS - The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device. | 11-19-2015 |
20150331046 | METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits. | 11-19-2015 |
20150338459 | SCAN RESPONSE REUSE METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure. | 11-26-2015 |
20150338460 | METHOD AND CONTROL DEVICE FOR LAUNCH-OFF-SHIFT AT-SPEED SCAN TESTING - The invention provides a method for launch-off-shift at-speed scan testing for at least two scan chains of an integrated circuit comprises iteratively shifting set values for functional elements of a first one of the scan chains clocked with a shift clock, iteratively shifting set values for functional elements of a second one of the scan chains clocked with the shift clock, launching an at-speed scan test clocked with a functional clock for the first one of the scan chains at a last shift cycle of the first one of the scan chains, delaying the last shift cycle for the second one of the scan chains for a predetermined time span, launching an at-speed scan test clocked with a functional clock for the second one of the scan chains at the last shift cycle of the second one of the scan chains, capturing the sample values of the functional elements of the first and second scan chains after the last shift cycle of the scan chains. | 11-26-2015 |
20150338461 | Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit - A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. | 11-26-2015 |
20150338462 | INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES - The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( | 11-26-2015 |
20150338463 | 3D TAP AND SCAN PORT ARCHITECTURES - This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure. | 11-26-2015 |
20150346277 | ELECTRONIC DEVICE AND METHOD FOR STATE RETENTION - An electronic device includes a set of two or more scan chains and a buffer chain. Each of the scan chains includes a sequence of stateful elements connected in series, and each of the scan chains is arranged to hold a string having a length identical to the length of the ( | 12-03-2015 |
20150346278 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 12-03-2015 |
20150346279 | MANAGING REDUNDANCY REPAIR USING BOUNDARY SCANS - An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode. | 12-03-2015 |
20150346280 | SCAN CHAIN PROCESSING IN A PARTIALLY FUNCTIONAL CHIP - A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons. | 12-03-2015 |
20150346281 | CONTROL TEST POINT FOR TIMING STABILITY DURING SCAN CAPTURE - A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation. | 12-03-2015 |
20150355276 | ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 12-10-2015 |
20150355277 | Circuit And Method For Monolithic Stacked Integrated Circuit Testing - A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit. The KGL test circuit includes a scan segment, and a plurality of inputs, outputs, and multiplexers coupled to the scan segment. The KGL test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis. | 12-10-2015 |
20150362554 | SYSTEM ON CHIP - A system on chip (SOC) is provided. The system on chip (SOC) includes: at least one core including a plurality of scan chains operated by a trigger signal; a delay controller generating a delay target selection signal selecting at least one of the plurality of scan chains and a delay depth control signal indicating a delay depth of the trigger signal; and a delay signal generating unit delaying the trigger signal based on the delay target selection signal and the delay depth control signal and providing the delayed trigger signal to the plurality of scan chains. | 12-17-2015 |
20150369863 | DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller. | 12-24-2015 |
20150377963 | IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES - In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals. | 12-31-2015 |
20160003901 | SCAN CHAIN CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop. | 01-07-2016 |
20160003902 | SCAN CHAIN LATCH DESIGN THAT IMPROVES TESTABILITY OF INTEGRATED CIRCUITS - A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency. | 01-07-2016 |
20160003905 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 01-07-2016 |
20160003906 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 01-07-2016 |
20160003909 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. | 01-07-2016 |
20160011258 | REPLACEMENT METHOD FOR SCAN CELL OF INTEGRATED CIRCUIT, SKEWABLE SCAN CELL AND INTEGRATED CIRCUIT | 01-14-2016 |
20160011260 | On-Chip Service Processor | 01-14-2016 |
20160011261 | SCAN TEST MULTIPLEXING | 01-14-2016 |
20160011262 | SCAN TEST MULTIPLEXING | 01-14-2016 |
20160018464 | ARRANGEMENT FOR PARTIAL RELEASE OF A DEBUGGING INTERFACE - An arrangement for the partial release of a debug interface of a programmable hardware component, whereby a first logic for the programmable hardware component can be stored in a configuration memory and a configuration device is designed to program the programmable hardware component via a configuration interface of the programmable hardware component according to the first logic. The configuration device is further designed to register a programming process of the programmable hardware component which occurs via the debug interface according to a second logic and, upon termination of the programming process occurring via the debug interface, reprograms the programmable hardware component according to the first logic. | 01-21-2016 |
20160033572 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead. | 02-04-2016 |
20160033573 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 02-04-2016 |
20160033574 | Scan Speed Optimization of Input and Output Paths - Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input/output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved. | 02-04-2016 |
20160041224 | SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS - Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values. | 02-11-2016 |
20160041225 | CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES - A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element. | 02-11-2016 |
20160047860 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 02-18-2016 |
20160054387 | METHOD FOR PROVIDING AN ON-CHIP VARIATION DETERMINATION AND INTEGRATED CIRCUIT UTILIZING THE SAME - A method for providing an on-chip variation determination and an integrated circuit utilizing the same are provided. The method includes: outputting, by a launch register circuit, a test data to the capture register circuit according to the first clock; receiving, by a capture register circuit, the test data from the launch register circuit according to the second clock; adjusting, by a control circuit, a first number of a first chain of delay elements to generate the first clock and a second number of a second chain of delay elements for the capture register circuit to just capture the test data to generate the second clock; and determining, by the control circuit, a path delay between the launch register circuit and the capture register circuit based on the first number of the first chain of delay elements and the second number of the second chain of delay elements. | 02-25-2016 |
20160061890 | INTEGRATED CIRCUIT DEVICE AND METHOD OF PERFORMING SELF-TESTING WITHIN AN INTEGRATED CIRCUIT DEVICE - IC device comprising a plurality of functional components arranged into self-test cells. The IC device is configurable into a first self-test configuration comprising a first set of self-test partitions. Each self-test partition within the first set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the first set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the first self-test configuration. The IC device is configurable into a second self-test configuration comprising a second set of self-test partitions. Each self-test partition within the second set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the second set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the second self-test configuration. | 03-03-2016 |
20160061892 | SCAN PROGRAMMABLE REGISTER CONTROLLED CLOCK ARCHITECTURE FOR TESTING ASYNCHRONOUS DOMAINS - Embodiments contained in the disclosure provide a method of testing an electronic chip. The method comprises: scanning a test program into multiple clock registers; pulsing a clock to activate multiple asynchronous clock domain registers one at a time; staggering capture across and within the multiple asynchronous clock domains; shifting acquired data out of the multiple scan chains simultaneously; and then comparing the data scanned out with the test program data. | 03-03-2016 |
20160061893 | TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY - The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states. | 03-03-2016 |
20160069955 | SHADOW ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal. | 03-10-2016 |
20160069956 | CHANNEL CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock to buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal. | 03-10-2016 |
20160069957 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed. | 03-10-2016 |
20160069958 | COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS - Electronic scan circuitry includes a decompressor ( | 03-10-2016 |
20160077155 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 03-17-2016 |
20160077156 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 03-17-2016 |
20160077157 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 03-17-2016 |
20160091563 | SCAN FLIP-FLOP - A pull cell scan flip-flop includes a scan flip-flop and a pull cell. The pull cell is configured to receive a scan flip-flop output signal from the scan flip-flop, the scan flip-flop output signal having a scan flip-flop output value. The pull cell is configured to receive a scan-enable signal and to generate a modified flip-flop output signal. The modified flip-flop output signal has a specified fixed value responsive to the scan-enable signal having a first logic value, and the modified flip-flop output signal has the scan flip-flop output value responsive to the scan-enable signal having a second logic value. | 03-31-2016 |
20160091564 | COMPRESSED SCAN TESTING TECHNIQUES - Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells. | 03-31-2016 |
20160091566 | INTEGRATED CIRCUIT WTH LOW POWER SCAN FLIP-FLOP - A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption. | 03-31-2016 |
20160091567 | HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS - A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure. | 03-31-2016 |
20160109514 | STRUCTURAL TESTING OF INTEGRATED CIRCUITS - An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature. | 04-21-2016 |
20160109518 | 3D STACKED DIE TEST ARCHITECTURE - This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die. | 04-21-2016 |
20160116532 | TEST METHOD AND TEST APPARATUS FOR TESTING A PLURALITY OF BLOCKS IN A CIRCUIT - Disclosed are a test apparatus and a test method for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures. The test apparatus comprises: a comparing device, configured to collect output responses generated by the plurality of blocks by applying an excitation signal to the plurality of blocks in parallel, compare the output responses of the plurality of blocks to determine whether the output responses of the plurality of blocks are identical, and output results of the comparison of the comparing device; and a determining device, configured to receive the results of the comparison of the comparing device, and determine whether the plurality of blocks have a defect according to the results of the comparison of the comparing device. With the test apparatus and the test method, a process for testing the plurality of blocks having the identical structures may be simplified, and test efficiency may be improved. | 04-28-2016 |
20160116534 | SCAN CHAIN LATCH DESIGN THAT IMPROVES TESTABILITY OF INTEGRATED CIRCUITS - A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency. | 04-28-2016 |
20160116535 | ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA - Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state. | 04-28-2016 |
20160131705 | CIRCUIT FOR TESTING INTEGRATED CIRCUITS - An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode. | 05-12-2016 |
20160131706 | CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD - Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure | 05-12-2016 |
20160139201 | DEBUG INTERFACE FOR MULTIPLE CPU CORES - A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of several types of packets such as a Second Access Bus (SAB) packet and Debug Access Bus (DAB) packet. The cores include specified resources and non-specified resources. A core that executes a transaction in response to a SAB packet accesses a non-specified resource and a core that executes a transaction in response to a DAB packet accesses a specified resources. A debug specification identifies the specified resources as being accessible by a debug controller. The debug specification does not identify the non-specified resources as being accessible by the debug controller. | 05-19-2016 |
20160154057 | TEST CIRCUIT AND METHOD FOR CONTROLLING TEST CIRCUIT | 06-02-2016 |
20160154058 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY | 06-02-2016 |
20160154059 | DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM | 06-02-2016 |
20160169965 | SCAN TESTING WITH STAGGERED CLOCKS | 06-16-2016 |
20160169966 | INTEGRATED CIRCUIT WITH SCAN CHAIN HAVING DUAL-EDGE TRIGGERED SCANNABLE FLIP FLOPS AND METHOD OF OPERATING THEREOF | 06-16-2016 |
20160169968 | PARTITIONED SCAN CHAIN DIAGNOSTICS USING MULTIPLE BYPASS STRUCTURES AND INJECTION POINTS | 06-16-2016 |
20160169969 | PARTITIONED SCAN CHAIN DIAGNOSTICS USING MULTIPLE BYPASS STRUCTURES AND INJECTION POINTS | 06-16-2016 |
20160178695 | TEST CIRCUIT FOR VERY LOW VOLTAGE AND BIAS SCAN TESTING OF INTEGRATED CIRCUIT | 06-23-2016 |
20160178697 | SCAN TEST METHOD AND APPARATUS | 06-23-2016 |
20160187420 | REPROGRAMMING A PORT CONTROLLER VIA ITS OWN EXTERNAL PORT - Systems and methods may provide for a debug tool including a debug port and a controller including logic to send, via the debug port, a debug mode request to an external port of a target device. Additionally, the target device may include a connector having the external port and a port controller coupled to the external port, wherein the port controller includes logic to detect the debug mode request via the external port, activate a program path between the external port and the port controller in response to the debug mode request, and process one or more commands received via the program path. In one example, the target device further includes a multiplexer coupled to the external port and the port controller, wherein the logic is to send a routing signal to the multiplexer to activate the program path. | 06-30-2016 |
20160187422 | SEMICONDUCTOR DEVICE - The semiconductor device cyclically outputs given status information pieces according to a predetermined procedure from a test output terminal one by one on receipt of a test enable direction through a test enable terminal, and outputs the same status information pieces as those output at that time from the test output terminal without interruption on receipt of a test disable direction. Operating the test enable terminal, the semiconductor device cyclically outputs status information pieces without the need for initial setting and further, outputs only desired status information without interruption. | 06-30-2016 |
20160187423 | SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS - Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values. | 06-30-2016 |
20160202315 | SYSTEM ON CHIP CAPABLE OF BEING DEBUGGED IN ABNORMAL OPERATING STATE AND DEBUGGING METHOD FOR SYSTEM ON CHIP | 07-14-2016 |
20160202316 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT | 07-14-2016 |
20160202317 | SERIAL I/O USING JTAG TCK AND TMS SIGNALS | 07-14-2016 |
20160202318 | SCAN FRAME BASED TEST ACCESS MECHANISMS | 07-14-2016 |
20160202319 | SCAN TESTING SYSTEM, METHOD AND APPARATUS | 07-14-2016 |
20160252573 | TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN CHAINS | 09-01-2016 |
20160252574 | PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO | 09-01-2016 |
20160252575 | COMMANDED JTAG TEST ACCESS PORT OPERATIONS | 09-01-2016 |
20160377677 | CHIP AND METHOD FOR TESTING A PROCESSING COMPONENT OF A CHIP - In accordance with one embodiment, a chip is provided which includes an interface configured to receive test data and masking data, a processing component having a plurality of scan chains. Each scan chain is configured to generate a test response on the basis of a processing of the test data. The chip further includes a compression circuit configured to compress the test responses generated by the scan chains to form a compressed test response, and a signature generating circuit configured to generate a signature on the basis of the compressed test response, depending on whether the masking data specify that the compressed test response is to be masked. | 12-29-2016 |
20170234925 | Non-Interleaved Scan Operation for Achieving Higher Scan Throughput in Presence of Slower Scan Outputs | 08-17-2017 |
20170234928 | DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM | 08-17-2017 |
20180024190 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE | 01-25-2018 |
20190146033 | SHADOW ACCESS PORT METHOD AND APPARATUS | 05-16-2019 |