Entries |
Document | Title | Date |
20080261410 | METHOD FOR TREATING BASE OXIDE TO IMPROVE HIGH-K MATERIAL DEPOSITION - A method for forming a high-K material layer in a semiconductor device fabrication process including providing a silicon semiconductor substrate or thermally growing interfacial oxide layer comprising silicon dioxide over the silicon substrate; treating with an aqueous base solution or nitridation and depositing a high-K material layer. | 10-23-2008 |
20090004879 | TEST STRUCTURE FORMATION IN SEMICONDUCTOR PROCESSING - Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices. | 01-01-2009 |
20090004880 | MASK REUSE IN SEMICONDUCTOR PROCESSING - A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers. | 01-01-2009 |
20090011607 | Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition Precursors - Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated. | 01-08-2009 |
20090011608 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated. | 01-08-2009 |
20090047796 | Method of Manufacturing a Dielectric Layer having Plural High-K Films - Nitridizing and optionally annealing plural high-k films layer-by-layer are performed to dope nitrogen into high-k films. | 02-19-2009 |
20090053902 | LOW DIELECTRIC (LOW K) BARRIER FILMS WITH OXYGEN DOPING BY PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PECVD) - Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma. | 02-26-2009 |
20090081882 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR DESIGNING PHOTOMASK PATTERN - A method for designing a photomask pattern is provided. First, all line ends of object patterns are determined with reference to layout data. Then, object patterns, front edge portions, and joints, which are aligned on the same line extending along the Y-axis, are connected to form first reticle data. Reticle pattern data having data representing binding portions serving as light blocking portions is formed. The front edge portions being adjacent to each other and aligned in the X-axis are connected and adjacent joints being aligned in the same manner as the front edge portions are also connected to form second reticle data. Then, portions are provided at central regions between the binding portions so as to connect the adjacent binding portions including the front edge portions and the joints. Then, reticle data having data representing the binding portions serving as transparent patterns is formed. | 03-26-2009 |
20090087998 | DIFFUSION BARRIER LAYER AND METHOD FOR MANUFACTURING A DIFFUSION BARRIER LAYER - A diffusion barrier system for a display device comprising a layer system with at least two layers of dielectric material, wherein at least two adjacent layers of that layer system comprise the same material. A respective method for manufacturing such a diffusion barrier system in a single process chamber of a plasma deposition system has the steps of introducing a substrate to be treated in said process chamber, discretely varying in a controlled manner during deposition at least one process parameter in the process chamber, without completely interrupting such process parameter, which results in layers with different properties and finally unloading said substrate from said process. | 04-02-2009 |
20090111279 | FUNCTIONAL FILM CONTAINING STRUCTURE AND METHOD OF MANUFACTURING FUNCTIONAL FILM - A method of manufacturing a functional film by which a functional film formed on a film formation substrate can be easily peeled from the film formation substrate. The method includes the steps of: (a) forming a separation layer on a substrate by using an inorganic material which is decomposed to generate a gas by being applied with an electromagnetic wave; (b) forming a layer to be peeled containing a functional film, which is formed by using a functional material, on the separation layer; and (c) applying the electromagnetic wave toward the separation layer so as to peel the layer to be peeled from the substrate or reduce bonding strength between the layer to be peeled and the substrate. | 04-30-2009 |
20090111280 | METHOD FOR REMOVING OXIDES - A method for removing native oxides from a substrate surface is provided. In one embodiment, the method comprises positioning a substrate having an oxide layer into a processing chamber, generating a plasma of a reactive species from a gas mixture within the processing chamber, exposing the substrate to the reactive species while forming a volatile film on the substrate and maintaining the substrate at a temperature below 65° C., heating the substrate to a temperature of at least about 75° C. to vaporize the volatile film and remove the oxide layer, and depositing a first layer on the substrate after heating the substrate. | 04-30-2009 |
20090124093 | Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities - A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors. | 05-14-2009 |
20090176377 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming patterns of a semiconductor device. In an aspect of the present invention, the method may include providing a semiconductor substrate, including a first area in which patterns are formed at a first interval and a second area formed wider than the first interval, forming an etch mask layer formed over the semiconductor substrate, forming photoresist patterns formed over the etch mask layer, wherein an auxiliary pattern is formed at an outermost area of the second area, forming first etch mask patterns by patterning the etch mask layer using the photoresist patterns and the auxiliary pattern, forming an auxiliary layer on the entire surface including the first etch mask patterns, forming a second etch mask pattern in concave portions of the auxiliary layer, and removing the auxiliary layer that is exposed. | 07-09-2009 |
20090176378 | MANUFACTURING METHOD OF DUAL DAMASCENE STRUCTURE - A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second dielectric layer, and the first dielectric layer. A portion of the second dielectric layer is then removed, so as to transform the first trench structure into a second trench structure. Here, a bottom of the second trench structure exposes the first dielectric layer. | 07-09-2009 |
20090197425 | SUBSTRATE PROCESSING APPARATUS - An ALD apparatus comprises: a process chamber ( | 08-06-2009 |
20090203221 | APPARATUS AND METHOD FOR INCORPORATING COMPOSITION INTO SUBSTRATE USING NEUTRAL BEAMS - An apparatus and method for incorporating a composition into a substrate using neutral beams are provided to repeatedly process an oxide layer using the neutral beams having low energy to minimize electrical damage to the oxide layer and improve characteristics of the oxide layer. The apparatus is mounted in a plasma generating chamber, and includes: an ion beam generating gas inlet, which injects a gas for generating ion beams; an ion source, which generates the ion beams having a polarity from the gas introduced through the ion beam generating gas inlet; a grid assembly, which is installed on one end of the ion source; a reflector, which is aligned with the grid assembly and converts the ion beams to the neutral beams; and a stage, on which the substrate is placed on a traveling path of the neutral beams. Formation of the oxide layer and application of the neutral beams are repeatedly performed on the substrate so as to improve the characteristics of the oxide layer. | 08-13-2009 |
20090215277 | DUAL CONTACT ETCH STOP LAYER PROCESS - A dual CESL process includes: (1) providing a substrate having thereon a first device region, a second device region and a shallow trench isolation (STI) region between the first and second device regions; (2) forming a first-stress imparting film with a first stress over the substrate, wherein the first-stress imparting film does not cover the second device region; and (3) forming a second-stress imparting film with a second stress over the substrate, wherein the second-stress imparting film does not cover the first device region, an overlapped boundary between the first- and second-stress imparting films is created directly above the STI region, and wherein the overlapped boundary is placed in close proximity to the second device region in order to induce the first stress to a channel region thereof in a transversal direction. | 08-27-2009 |
20090215278 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Prior to a step of providing a stress layer covering a first transistor, a second transistor and a gate structure, another silicon oxide film is formed over the second transistor to form a silicon oxide film with a predetermined thickness over the second transistor. By a step of removing the portion of the stress layer over the second transistor and the gate structure and leaving the portion of the stress layer over the first transistor, the silicon oxide film over the second transistor is prevented from becoming excessively thinner than the silicon oxide film over the first transistor. The source region and the drain region of the second transistor can be prevented from being shaved because of thinness of the silicon oxide film over the second transistor when removing silicon oxide films over the first transistor and second transistor. | 08-27-2009 |
20090275210 | COMBINATORIAL PLASMA ENHANCED DEPOSITION TECHNIQUES - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 11-05-2009 |
20090291568 | Semiconductor devices and method of forming the same - Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer. | 11-26-2009 |
20090298297 | DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION - A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed. | 12-03-2009 |
20100009544 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A coating solution of SOG is applied on a silicon oxynitride film ( | 01-14-2010 |
20100022100 | BI-LAYER CAPPING OF LOW-K DIELECTRIC FILMS - A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film. | 01-28-2010 |
20100029090 | NOVEL CONTACT ETCH STOP FILM - A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer. In addition, the partially completed integrated circuit device includes a profile characterized by the silicon dioxide material in the first thickness portion changing to the silicon nitride material in the second thickness portion. | 02-04-2010 |
20100041241 | HIGH DENSITY PLASMA DIELECTRIC DESPOSITION FOR VOID FREE GAP FILL - A process for void free deposition of dielectric films over high aspect ratio structures using HDP CVD. In a dielectric liner deposition step and the etch to deposition ratio is increased and the deposition pressure is reduced to reduce the aspect ratio of the gap and to deposit a dielectric sidewall on the gap with a significant slope. | 02-18-2010 |
20100041242 | Double Anneal with Improved Reliability for Dual Contact Etch Stop Liner Scheme - A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal. | 02-18-2010 |
20100055926 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the steps of carrying a substrate in a processing chamber, bringing the processing chamber into a state at a first pressure by supplying a silicon compound gas which contains carbon and hydrogen into the processing chamber, forming a silicon oxide film on the substrate by irradiating a UV light to the silicon compound gas supplied into the processing chamber in the state kept at the first pressure, and decompression process to bring the processing chamber into a state at a second pressure lower than the first pressure. This makes it possible to form the dense silicon oxide film in the trench with high aspect ratio and small width. | 03-04-2010 |
20100081290 | METHOD OF FORMING A GATE DIELECTRIC BY IN-SITU PLASMA - A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer. | 04-01-2010 |
20100099267 | SYSTEM AND METHOD OF VAPOR DEPOSITION - Provided is a method and system for vapor deposition of a coating material onto a semiconductor substrate. In an embodiment, photoresist is deposited. An in-situ baking process may be performed with the vapor deposition. In an embodiment, a ratio of chemical components of a material to be deposited onto the substrate is changed during the deposition. Therefore, a layer having a gradient chemical component distribution may be provided. In an embodiment, a BARC layer may be provided which includes a gradient chemical component distribution providing an n,k distribution through the layer. Other materials that may be vapor deposited include pattern freezing material. | 04-22-2010 |
20100099268 | Rapid Thermal Processing using Energy Transfer Layers - A method that is performed for heat treating a semiconductor wafer in a process chamber, as an intermediate part of an overall multi-step technique for processing the wafer, includes applying an energy transfer layer to at least a portion of the wafer, and exposing the wafer to an energy source in the process chamber in a way which subjects the wafer to a thermal profile such that the energy transfer layer influences at least one part of the thermal profile. The thermal profile has at least a first elevated temperature event. The method further includes, in time relation to the thermal profile, removing the energy transfer layer in the process chamber at least sufficiently for subjecting the wafer to a subsequent step. An associated intermediate condition of the wafer is described. | 04-22-2010 |
20100112823 | METHOD OF FORMING A RESIST PATTERN - A lower-layer film to which a fluorine-doped polymer is added is formed on a film to be processed. The lower-layer film is baked. An intermediate film is formed on the lower-layer film. A resist film is formed on the intermediate film. The resist film is baked. A resist protection film is formed. The resist film is immersion-exposed. The resist film is developed to form a resist pattern. | 05-06-2010 |
20100130024 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided are a method of manufacturing a semiconductor device and a substrate processing apparatus. The method includes: forming a first layer including a first element on a substrate by supplying a gas containing the first element; forming a second layer including first and second elements by supplying a gas containing the second element to modify the first layer; and forming a thin film having a predetermined thickness by setting the forming of the first layer and the forming of the second layer to one cycle and repeating the cycle at least once. Pressure, or pressure and a gas supply time in one process of the forming of the first layer and the forming of the second layer are controlled to be higher or longer, or lower or shorter than pressure, or pressure and a time in the one process when the thin film having a stoichiometric composition is formed. | 05-27-2010 |
20100151693 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE COMPRISING MUTIOXIDE - A semiconductor device comprises a first region including a first semiconductor element and a second region including a second semiconductor element different from the first semiconductor element. A silicon germanium film is formed on a surface of a semiconductor substrate in the first region and the second region. The surface of the silicon germanium film at least in the first region is nitrided. A first insulating film mainly includes silicon and oxygen is formed, on the silicon germanium film nitrided at least in the first region in the first region and the second region. The first insulating film in the second region is removed. A second insulating film mainly includes metal and oxygen is formed, on the nitrided silicon germanium film in the second region. | 06-17-2010 |
20100173500 | SEMICONDUCTOR WAFER STRUCTURE WITH BALANCED REFLECTANCE AND ABSORPTION CHARACTERISTICS FOR RAPID THERMAL ANNEAL UNIFORMITY - Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate. | 07-08-2010 |
20100190353 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 07-29-2010 |
20100190354 | INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT - An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage. | 07-29-2010 |
20100197145 | SILICON NITRIDE PASSIVATION FOR A SOLAR CELL - A silicon nitride layer may be formed with a suitable refractive index, mass density, and hydrogen concentration so that the layer may serve as an ARC/passivation layer on a solar cell substrate. The silicon nitride layer may be formed on a solar cell substrate by adding a hydrogen gas diluent to a conventional precursor gas mixture during the deposition process. Alternatively, the silicon nitride layer may be formed on a solar cell substrate by using a precursor gas mixture consisting essentially of silane and nitrogen. To improve deposition chamber throughput, the silicon nitride layer may be a dual stack film that includes a low-hydrogen interface layer and a thicker bulk silicon nitride layer. Placing a plurality of solar cell substrates on a substrate carrier and transferring the substrate carrier into the deposition chamber may further enhance deposition chamber throughput. | 08-05-2010 |
20100210116 | METHODS OF FORMING VAPOR THIN FILMS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME - A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate. | 08-19-2010 |
20100267246 | Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition Precursors - Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated. | 10-21-2010 |
20100279513 | Systems and Methods for Nanowire Growth and Manufacturing - The present invention is directed to compositions of matter, systems, and methods to manufacture nanowires. In an embodiment, a buffer layer is placed on a nanowire growth substrate and catalytic nanoparticles are added to form a catalytic-coated nanowire growth substrate. Methods to develop and use this catalytic-coated nanowire growth substrate are disclosed. In a further aspect of the invention, in an embodiment a nanowire growth system using a foil roller to manufacture nanowires is provided. | 11-04-2010 |
20100279514 | MULTILAYER DIELECTRIC - A method forms a first inorganic dielectric layer having a first concentration of defects and a second inorganic dielectric layer in contact with a first layer and having a second lesser concentration of defects. | 11-04-2010 |
20100311251 | BATCH PROCESSING METHOD FOR FORMING STRUCTURE INCLUDING AMORPHOUS CARBON FILM - A batch processing method for forming a structure including an amorphous carbon film includes performing a preliminary treatment of removing water from a surface of the underlying layer by heating the inside of the reaction chamber at a preliminary treatment temperature of 800 to 950° C. and supplying a preliminary treatment gas selected from the group consisting of nitrogen gas and ammonia gas into the reaction chamber while exhausting gas from inside the reaction chamber; and, then performing main CVD of forming an amorphous carbon film on the underlying layer by heating the inside of the reaction chamber at a main process temperature and supplying a hydrocarbon gas into the reaction chamber while exhausting gas from inside the reaction chamber. | 12-09-2010 |
20100330812 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first-conductivity-type well and a second-conductivity-type well in a silicon substrate; stacking a first high-dielectric-constant insulating film and a first cap dielectric film above the silicon substrate; removing at least the first cap dielectric film from above the second-conductivity-type well; conducting a first annealing at a first temperature to cause an element included in the first cap dielectric film to diffuse into the first high-dielectric-constant insulating film disposed above the first-conductivity-type well; after the first annealing, stacking a second high-dielectric-constant insulating film and a second cap dielectric film above the silicon substrate; removing the second cap dielectric film disposed above the first-conductivity-type well; and conducting a second annealing at a second temperature lower than the first temperature to cause an element included in the second cap dielectric film to diffuse into the second high-dielectric-constant insulating film disposed above the second-conductivity-type well. | 12-30-2010 |
20100330813 | DIELECTRIC FILM AND SEMICONDUCTOR DEVICE USING DIELECTRIC FILM - The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film ( | 12-30-2010 |
20110014795 | Method of Forming Stress-Tuned Dielectric Film Having Si-N Bonds by Modified PEALD - A method of forming stress-tuned dielectric films having Si—N bonds on a semiconductor substrate by modified plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen-and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space using a high frequency RF power source and a low frequency RF power source; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a stress-tuned dielectric film having Si—N bonds on the substrate. | 01-20-2011 |
20110021035 | DEPOSITION APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - Provided are a deposition apparatus and a method of manufacturing a semiconductor device. In the method, a reaction chamber provided with a gaseous source supply unit and a liquid source supply unit is prepared, and an etch stop layer is formed on a substrate by using a gaseous source. Then, an interlayer insulation layer is formed on the etch stop layer by using a vaporized liquid source and a vaporized dopant source. In this way, the etch stop layer and the interlayer insulation layer are formed in-situ in the same reaction chamber. | 01-27-2011 |
20110028002 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a semiconductor device includes the following processes. A metal nitride film is formed with a thickness of 3 nm or less over a substrate. The metal nitride film is oxidized to form a metal oxide film. A set of the formation of the metal nitride film and the oxidation of the metal nitride film is repeated, to form a stack of the metal oxide films over the substrate. | 02-03-2011 |
20110034035 | STRESS MANAGEMENT FOR TENSILE FILMS - The formation of a gap-filling silicon oxide layer with reduced tendency towards cracking is described. The deposition involves the formation of a flowable silicon-containing layer which facilitates the filling of trenches. Subsequent processing at high substrate temperature causes less cracking in the dielectric film than flowable films formed in accordance with methods in the prior art. A compressive liner layer deposited prior to the formation of the gap-filling silicon oxide layer is described and reduces the tendency for the subsequently deposited film to crack. A compressive capping layer deposited after a flowable silicon-containing layer has also been determined to reduce cracking. Compressive liner layers and compressive capping layers can be used alone or in combination to reduce and often eliminate cracking. Compressive capping layers in disclosed embodiments have additionally been determined to enable an underlying layer of silicon nitride to be transformed into a silicon oxide layer. | 02-10-2011 |
20110045675 | SUBSTRATE PROCESSING APPARATUS AND PRODUCING METHOD OF SEMICONDUCTOR DEVICE - Disclosed is a substrate processing apparatus, comprising a processing chamber, a holder to hold at least a plurality of product substrates, a heating member, a supplying member to alternately supply at least a first reactant and a second reactant, and a control unit, wherein the control unit executes forming thin films on the substrates by supplying the first reactant, removing a surplus of the first reactant after the first reactant has been adsorbed on the product substrates, subsequently supplying the second reactant, to cause the second reactant to react with the first reactant adsorbed on the substrates, and executes the forming the thin films in a state where a number of the product substrates is insufficient when a number of the product substrates is less than a maximum number of the product substrates which can be held by the holder. | 02-24-2011 |
20110065284 | Method and System for Isolated and Discretized Process Sequence Integration - A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided. | 03-17-2011 |
20110086515 | MASK PATTERN VERIFICATION APPARATUS, MASK PATTERN VERIFICATION METHOD AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - In one embodiment, a mask pattern verification apparatus is disclosed. The mask pattern verification apparatus can include a library registration portion registered a clean circuit pattern, a memory portion saved a design circuit pattern, a verification circuit pattern, a verification mask pattern, and a verification wafer pattern, a mask verification portion performing mask verification to the verification mask pattern, a lithography verification portion performing lithography verification to the verification wafer pattern, and a CPU including a library registration circuit registering the clean circuit pattern to the library registration portion, a pattern matching circuit verifying the clean circuit pattern being set or not in the design circuit pattern, a verification pattern extraction circuit extracting the verification circuit pattern from the design circuit pattern, an OPC circuit performing OPC to the verification circuit pattern, a mask verification circuit controlling the mask verification portion, and a lithography verification circuit controlling the lithography verification portion. | 04-14-2011 |
20110189860 | METHODS FOR NITRIDATION AND OXIDATION - Methods of nitridation and selective oxidation are provided herein. In some embodiments, a method of nitridation includes providing a substrate having a first layer disposed thereon, where the substrate is disposed on a substrate support in a process chamber; forming a remote plasma from a process gas comprising nitrogen; and exposing the first layer to a reactive species formed from the remote plasma to form a nitrogen-containing layer, wherein a density of the reactive species is about 10 | 08-04-2011 |
20110212628 | SEQUENTIAL PULSE DEPOSITION - A method for growing films on substrates using sequentially pulsed precursors and reactants, system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. | 09-01-2011 |
20110244693 | COMPONENT FOR SEMICONDUCTOR PROCESSING APPARATUS AND MANUFACTURING METHOD THEREOF - A component for a semiconductor processing apparatus includes a matrix defining a shape of the component, and a protection film covering a predetermined surface of the matrix. The protection film consists essentially of an amorphous oxide of a first element selected from the group consisting of aluminum, silicon, hafnium, zirconium, and yttrium. The protection film has a porosity of less than 1% and a thickness of 1 nm to 10 μm. | 10-06-2011 |
20110275225 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a transistor over a semiconductor substrate; forming a first silicon nitride film covering the transistor over the semiconductor substrate; supplying a NH | 11-10-2011 |
20110300717 | METHOD FOR CONTROLLING DANGLING BONDS IN FLUOROCARBON FILMS - Embodiments of the invention describe methods for forming fluorocarbon (CF) films for semiconductor devices. According to one embodiment, the method includes providing a substrate, depositing a CF film on the substrate, generating, in the absence of a plasma, a treatment gas containing a gaseous specie having a molecular dipole, and treating the CF film with the treatment gas containing the gaseous specie having the molecular dipole to reduce the number of dangling bonds in the CF film. According to some embodiments, the method further includes depositing a second CF film on the treated CF film. According to some embodiments, the CF films may be deposited using a microwave plasma source containing a radial line slot antenna (RLSA). | 12-08-2011 |
20120003840 | IN-SITU OZONE CURE FOR RADICAL-COMPONENT CVD - Methods of forming a dielectric layer are described. The methods include the steps of mixing a silicon-containing precursor with a plasma effluent, and depositing a silicon-and-nitrogen-containing layer on a substrate. The silicon-and-nitrogen-containing layer is converted to a silicon-and-oxygen-containing layer by curing in an ozone-containing atmosphere in the same substrate processing region used for depositing the silicon-and-nitrogen-containing layer. Another silicon-and-nitrogen-containing layer may be deposited on the silicon-and-oxygen-containing layer and the stack of layers may again be cured in ozone all without removing the substrate from the substrate processing region. After an integral multiple of dep-cure cycles, the conversion of the stack of silicon-and-oxygen-containing layers may be annealed at a higher temperature in an oxygen-containing environment. | 01-05-2012 |
20120015526 | Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition Precursors - Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated. | 01-19-2012 |
20120071004 | STRESS-ADJUSTING METHOD OF MOS DEVICE - A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress. | 03-22-2012 |
20120083133 | AMINE CURING SILICON-NITRIDE-HYDRIDE FILMS - Methods of forming dielectric layers are described. The methods may include forming a silicon-nitrogen-and-hydrogen-containing layer on a substrate. The methods include ozone curing the silicon-nitrogen-and-hydrogen-containing layer to turn the silicon-nitrogen-and-hydrogen-containing layer into a silicon-and-oxygen-containing layer. Following ozone curing, the layer is exposed to an amine-water combination at low temperature before an anneal. The presence of the amine cure allows the conversion to silicon-and-oxygen-containing layer to occur more rapidly and completely at a lower temperature during the anneal. The amine cure also enables the anneal to use a less oxidative environment to effect the conversion to the silicon-and-oxygen-containing layer. | 04-05-2012 |
20120083134 | METHOD OF MITIGATING SUBSTRATE DAMAGE DURING DEPOSITION PROCESSES - Systems, methods, and apparatus for depositing a protective layer on a wafer substrate are disclosed. In one aspect, a protective layer is deposited over a surface of a wafer substrate using a process configured to produce substantially less damage in the wafer substrate than a first plasma-assisted deposition process. The protective layer is less than about 100 Angstroms thick. A barrier layer is deposited over the protective layer using the first plasma-assisted deposition process. | 04-05-2012 |
20120094503 | COMBINATORIAL PLASMA ENHANCED DEPOSITION TECHNIQUES - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 04-19-2012 |
20120100723 | COMBINATORIAL PLASMA ENHANCED DEPOSITION TECHNIQUES - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 04-26-2012 |
20120100724 | COMBINATORIAL PLASMA ENHANCED DEPOSITION TECHNIQUES - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 04-26-2012 |
20120129356 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method. | 05-24-2012 |
20120156889 | METHODS FOR FORMING HIGH-K CRYSTALLINE FILMS AND RELATED DEVICES - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures. | 06-21-2012 |
20120202353 | NANOLAYER DEPOSITION USING PLASMA TREATMENT - A process to deposit a thin film by chemical vapor deposition includes evacuating a chamber of gases; exposing a device to a gaseous first reactant, wherein the first reactant deposits on the device to form the thin film having a plurality of monolayers in thickness; evacuating the chamber of gases; exposing the device, coated with the first reactant, to a gaseous second reactant under a plasma treatment, wherein the thin film is treated by the first reactant; and repeating the previous steps. | 08-09-2012 |
20120238107 | PROCESSING METHOD FOR FORMING STRUCTURE INCLUDING AMORPHOUS CARBON FILM - A processing method for forming a structure including an amorphous carbon film includes performing a preliminary treatment of removing water from a surface of the underlying layer by heating the inside of the reaction chamber at a preliminary treatment temperature of 800 to 950° C. and supplying a preliminary treatment gas selected from the group consisting of nitrogen gas and ammonia gas into the reaction chamber while exhausting gas from inside the reaction chamber; and, then performing main CVD of forming an amorphous carbon film on the underlying layer by heating the inside of the reaction chamber at a main process temperature and supplying a hydrocarbon gas into the reaction chamber while exhausting gas from inside the reaction chamber. | 09-20-2012 |
20120276752 | HARDMASK MATERIALS - Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si | 11-01-2012 |
20120289061 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, including introducing a first plurality of precursors to deposit a thin film and introducing a second plurality of precursors to modify the deposited thin film. The deposition using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film, including treatments such as modification of film composition and doping or removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 11-15-2012 |
20120302071 | Forming Substrate Structure by Filling Recesses with Deposition Material - A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure. | 11-29-2012 |
20120322272 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, comprising: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film, wherein the forming an insulating film covering the field-effect transistors and the shrinking the insulating film are repeated a plurality of time. | 12-20-2012 |
20130034969 | Thin Film Deposition Method - The present invention provides a thin film deposition method, comprising: seasoning a first deposition chamber; seasoning a second deposition chamber; pre-processing the first deposition chamber, depositing a thin film in the first deposition chamber, cleaning the first deposition chamber, post-processing and withdrawing the wafers; pre-processing the second deposition chamber, depositing a thin film in the second deposition chamber, cleaning the second deposition chamber, post-processing and withdrawing the wafers; characterized in that there is a time interval between the step of seasoning the second deposition chamber and the step of seasoning the first deposition chamber. The method of stabilizing the thin film thickness of the present invention can well solve the problem that the thin film on the first pair of wafers of each batch of products becomes thinner or thicker during the deposition. In addition, the present invention greatly reduces the influences from human activities without increasing the seasoning wafers, thus realizing automation; moreover, the affected wafers no longer need to be scraped, thus increasing the yield of products. | 02-07-2013 |
20130045607 | PATTERN GENERATING APPARATUS, PATTERN GENERATING PROGRAM, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - According to one embodiment, a pattern generating apparatus includes a light intensity calculating part that calculates light intensity at a pattern to be formed based on exposure and light intensity at the periphery of the pattern, a light intensity evaluating part that evaluates the light intensities at the pattern and the periphery of the pattern, and a data output part that outputs correction data for the pattern based on the results of the evaluation by the light intensity part. | 02-21-2013 |
20130078818 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure. | 03-28-2013 |
20130122719 | Method for Manufacturing a Barrier on a Sheet and a Sheet for PV Modules - A method for manufacturing a barrier layer ( | 05-16-2013 |
20130143414 | NANOSTRUCTURED ELECTRODES AND ACTIVE POLYMER LAYERS - Embodiments of methods for fabricating polymer nanostructures and nanostructured electrodes are disclosed. Material layers are deposited onto polymer nanostructures to form nanostructured electrodes and devices including the nanostructured electrodes, such as photovoltaic cells, light-emitting diodes, and field-effect transistors. Embodiments of the disclosed methods are suitable for commercial-scale production of large-area nanostructured polymer scaffolds and large-area nanostructured electrodes. | 06-06-2013 |
20130149871 | CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL - The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another. | 06-13-2013 |
20130164944 | Methods Of Forming Openings And Methods Of Patterning A Material - Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines. | 06-27-2013 |
20130217237 | SPIN-ON DIELECTRIC METHOD WITH MULTI-STAGE RAMPING TEMPERATURE - A Spin-On Dielectric (SOD) method with multi stage ramping temperature for coating a dielectric material onto a substrate, comprising the steps of: (a) placing the substrate on a chill plate to decrease the temperature; (b) fixing the chilled substrate on a spinning device; (c) rotating the spinning device to drive the substrate rotating; (d) injecting the dielectric material onto the center of the substrate; (e) spreading the dielectric material on the upper surface of the substrate by spinning; (f) baking the substrate and the dielectric material by a heat plate to achieve multi stages ramping temperature, where the temperature of each stage has a steady state temperature for a predetermined time and the posterior stage has higher temperature than the anterior stage; (g) placing the substrate on the chill plate for cooling down; (h) spreading a film of dielectric material and finishing the coating. | 08-22-2013 |
20130217238 | Substrate Processing Including A Masking Layer - Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer. | 08-22-2013 |
20130244445 | Method of Fabricating Semiconductor Device - Methods of fabricating a semiconductor device include forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming unit layers on the semiconductor substrate. The unit layer is formed by forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and film-control material into the process chamber, purging the process chamber, forming a unit layer from the preliminary unit layer, and again purging the process chamber. The precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material includes a hydride of the ligand. | 09-19-2013 |
20130252436 | DIELECTRIC THIN FILM, METHOD OF MANUFACTURING SAME, AND APPLICATIONS THEREOF - A dielectric thin film and a method of manufacturing the same, wherein the manufacture of a dielectric thin film having a composition represented by Ba | 09-26-2013 |
20130316543 | METHOD AND APPARATUS FOR SUBSTRATE-MASK ALIGNMENT - A shadow masking device for use in the semiconductor industry includes self-aligning mechanical components that permit shadow masks to be exchanged while maintaining precise alignment with the target substrate. The misregistration between any two of the various layers in the formed structure can be kept to less than 40 microns. | 11-28-2013 |
20130330932 | HARDMASK MATERIALS - Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si | 12-12-2013 |
20140004711 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140057451 | METHOD OF PREVENTING CHARGE ACCUMULATION IN MANUFACTURE OF SEMICONDUCTOR DEVICE - A method of preventing a charge accumulation in the manufacturing process of a semiconductor device is provided. The method includes: forming a material layer on a substrate; patterning (or processing) the material layer; and forming a graphene layer before patterning the material layer, wherein the graphene layer is formed on a surface of the material layer or on a surface of the substrate under the material layer. The substrate may be an insulation substrate. In addition, the substrate may have a stacked structure including a plurality of layers. | 02-27-2014 |
20140057452 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, carbon, nitrogen and a borazine ring skeleton on a substrate by performing a cycle for a first predetermined number of times. The cycle includes forming a first layer containing the predetermined element, a halogen group, carbon and nitrogen by supplying a first precursor gas containing the predetermined element and the halogen group and a second precursor gas containing the predetermined element and an amino group to the substrate, for a second predetermined number of times; and forming a second layer containing the predetermined element, carbon, nitrogen and the borazine ring skeleton by supplying a reaction gas containing a borazine compound to the substrate and allowing the first layer to react with the borazine compound to modify the first layer under a condition where the borazine ring skeleton in the borazine compound is maintained. | 02-27-2014 |
20140065838 | THIN FILM DIELECTRIC LAYER FORMATION - A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A second inorganic thin film dielectric material layer is deposited on the treated surface of the first inorganic thin film dielectric material layer using an atomic layer deposition process. | 03-06-2014 |
20140065839 | METHOD OF PATTERN FORMATION - According to the embodiments, a method for pattern formation includes: creating a first self-assembly material layer which contains a first segment and a second segment, on a substrate on which a guide layer is installed; creating a first self-assembled pattern in which the first self-assembly material layer is phase-separated, the pattern including a first area containing the first segment and a second area containing the second segment; creating a second self-assembly material layer which includes a third segment and a fourth segment, in the first self-assembled pattern; creating a second self-assembled pattern in which the second self-assembly material layer is phase-separated, and which includes a third area containing the third segment and a fourth area containing the fourth segment. | 03-06-2014 |
20140073141 | METHOD FOR FORMING PATTERN AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side. | 03-13-2014 |
20140087566 | PATTERN FORMATION METHOD - A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film. | 03-27-2014 |
20140134849 | Combinatorial Site Isolated Plasma Assisted Deposition - An apparatus that includes a base, a sidewall extending from the base, and a lid disposed over a top of the sidewall is provided. A plasma generating source extends through a surface of the lid. A rotatable substrate support is disposed within the chamber above a surface of the base, the rotatable substrate support operable to vertically translate from the base to the lid. A first fluid inlet extends into a first surface of the sidewall and a second fluid inlet extends into a second surface of the sidewall. The plasma generating source provides a plasma activated species to a region of a surface of a substrate supported on the rotatable substrate support and a fluid delivered proximate to the region from one of the first or the second fluid inlet interacts with the plasma activated species to deposit a layer of material over the region. | 05-15-2014 |
20140162464 | AUTHENTICATION USING GRAPHENE BASED DEVICES AS PHYSICAL UNCLONABLE FUNCTIONS - A method of manufacturing a secure device having a physical unclonable function includes providing a first graphene layer, providing a second graphene layer and applying a variability enhancement to at least one of the first graphene layer and the second graphene layer such that a measurable property is different for each of the first graphene layer and the second graphene layer. The physical unclonable function is represented by at least the first and second graphene layers. In still another embodiment, a method of manufacturing a secure device having a physical unclonable function includes providing an integrated circuit comprising at least one graphene layer and including a measurement circuit in the integrated circuit that is configured to measure at least one property of the at least one graphene layer for authenticating the secure device. The at least one graphene layer represents the physical unclonable function. | 06-12-2014 |
20140193980 | PATTERNED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. Accordingly, first patterned second hard mask (HM) region is patterned, thus forming the line end space structure associated with an end-to-end space. | 07-10-2014 |
20140193981 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 07-10-2014 |
20140206202 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS - A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate. Alternatively, the semiconductor substrate is immersed in the first chemical liquid coated with the second chemical liquid. The semiconductor substrate is then dried. | 07-24-2014 |
20140213065 | Method for Forming Layer Constituted by Repeated Stacked Layers - A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer. | 07-31-2014 |
20140213066 | LAYOUT DECOMPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE APPLYING THE SAME - A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas. | 07-31-2014 |
20140322920 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - Provided are a deposition apparatus and a method of manufacturing a semiconductor device. In the method, a reaction chamber provided with a gaseous source supply unit and a liquid source supply unit is prepared, and an etch stop layer is formed on a substrate by using a gaseous source. Then, an interlayer insulation layer is formed on the etch stop layer by using a vaporized liquid source and a vaporized dopant source. In this way, the etch stop layer and the interlayer insulation layer are formed in-situ in the same reaction chamber. | 10-30-2014 |
20140342573 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM - There is provided a method for manufacturing a semiconductor device, including forming a thin film containing a specific element and having a prescribed composition on a substrate by alternately performing the following steps prescribed number of times: forming a first layer containing the specific element, nitrogen, and carbon on the substrate by alternately performing prescribed number of times: supplying a first source gas containing the specific element and a halogen-group to the substrate, and supplying a second source gas containing the specific element and an amino-group to the substrate, and forming a second layer by modifying the first layer by supplying a reactive gas different from each of the source gases, to the substrate. | 11-20-2014 |
20140342574 | PATTERN FORMATION METHOD - A pattern formation method for forming a micropattern includes a first step of causing a first pattern-formable area at which a first pattern is to be formed on a liquid-repellent, first film that is formed on a substrate and that has a lyophilic/lyophobic variable function to be lyophilic and to reduce in thickness; a second step of forming a second film having a flat surface on the first film; and a third step of forming the first pattern at the first pattern-formable area by drying the second film. | 11-20-2014 |
20140357090 | CYCLIC ALUMINUM NITRIDE DEPOSITION IN A BATCH REACTOR - A process for depositing aluminum nitride is disclosed. The process comprises providing a plurality of semiconductor substrates in a batch process chamber and depositing an aluminum nitride layer on the substrates by performing a plurality of deposition cycles without exposing the substrates to plasma during the deposition cycles. Each deposition cycle comprises flowing an aluminum precursor pulse into the batch process chamber, removing the aluminum precursor from the batch process chamber, and removing the nitrogen precursor from the batch process chamber after flowing the nitrogen precursor and before flowing another pulse of the aluminum precursor. The process chamber may be a hot wall process chamber and the deposition may occur at a deposition pressure of less than 1 Torr. | 12-04-2014 |
20140363982 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ◯ atoms and hexa-coordinated Al atoms each surrounded by six ◯ atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms. | 12-11-2014 |
20140377961 | THIN FILM DEPOSITION APPARATUS WITH MULTI CHAMBER DESIGN AND FILM DEPOSITION METHODS - A multi chamber thin film deposition apparatus and a method for depositing films, is provided. Each chamber includes a three dimensional gas delivery system including process gases being delivered downwardly toward the substrate and laterally toward the substrate. A pumping system includes an exhaust port in each chamber that is centrally positioned underneath the substrate being processed and therefore the gas flow around all portions of the edge of the substrate are equally spaced from the exhaust port thereby creating a uniform gas flow profile which results in film thickness uniformity of films deposited on both the front and back surfaces of the substrate. The deposited films demonstrate uniform thickness on the front and back of the substrate and extend inwardly to a uniform distance on the periphery of the backside of the substrate. | 12-25-2014 |
20140377962 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 12-25-2014 |
20150087158 | METHOD FOR DEPOSITING A FILM AND FILM DEPOSITION APPARATUS - A method for depositing a film is provided. In the method, an object to be processed is accommodated in a process chamber, and an insulating film made of a polymer thin film is deposited on a surface of the object to be processed by supplying a first source gas composed of an acid anhydride and a second source gas composed of a diamine into the process chamber that is evacuated. Next, the insulating film is modified so as to have a barrier function by stopping the supply of the second source gas into the process chamber and continuously supplying the first source gas into the process chamber. | 03-26-2015 |
20150093910 | METHODS FOR CONVERTING PLANAR DESIGNS TO FINFET DESIGNS IN THE DESIGN AND FABRICATION OF INTEGRATED CIRCUITS - Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area. | 04-02-2015 |
20150093911 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device includes: (a) forming a first film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a first precursor gas being a fluorine-free inorganic gas containing the metal element to the substrate; and (a-2) supplying a first reactant gas having reducibility to the substrate; (b) forming a second film containing the metal element on the first film by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a second precursor gas containing the metal element and fluorine to the substrate; and (b-2) supplying a second reactant gas having reducibility to the substrate; and (c) forming a film containing the metal element and obtained by the first film and the second film being laminated on the substrate by performing the (a) and (b). | 04-02-2015 |
20150099372 | SEQUENTIAL PRECURSOR DOSING IN AN ALD MULTI-STATION/BATCH REACTOR - Disclosed herein are methods of depositing layers of material on multiple semiconductor substrates at multiple processing stations within one or more reaction chambers. The methods may include dosing a first substrate with film precursor at a first processing station and dosing a second substrate with film precursor at a second processing station with precursor flowing from a common source, wherein the timing of said dosing is staggered such that the first substrate is dosed during a first dosing phase during which the second substrate is not substantially dosed, and the second substrate is dosed during a second dosing phase during which the first substrate is not substantially dosed. Also disclosed herein are apparatuses having a plurality of processing stations contained within one or more reaction chambers and a controller with machine-readable instructions for staggering the dosing of first and second substrates at first and second processing stations. | 04-09-2015 |
20150126042 | SOFT LANDING NANOLAMINATES FOR ADVANCED PATTERNING - Methods for depositing nanolaminate protective layers over a core layer to enable deposition of high quality conformal films over the core layer for use in advanced multiple patterning schemes are provided. In certain embodiments, the methods involve depositing a thin silicon oxide or titanium oxide film using plasma-based atomic layer deposition techniques with a low high frequency radio frequency (HFRF) plasma power, followed by depositing a conformal titanium oxide film or spacer with a high HFRF plasma power. | 05-07-2015 |
20150140832 | HIGH VACUUM OLED DEPOSITION SOURCE AND SYSTEM - Sources, devices, and techniques for deposition of organic layers, such as for use in an OLED, are provided. A vaporizer may vaporize a material between cooled side walls and toward a mask having an adjustable mask opening. The mask opening may be adjusted to control the pattern of deposition of the material on a substrate, such as to correct for material buildup that occurs during deposition. Material may be collected from the cooled side walls for reuse. | 05-21-2015 |
20150311060 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device is disclosed. The method includes forming a thin film containing a predetermined element, boron, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first layer containing boron and a halogen group by supplying a first precursor gas containing boron and the halogen group to the substrate; and forming a second layer containing the predetermined element, boron, carbon, and nitrogen by supplying a second precursor gas containing the predetermined element and an amino group to the substrate and modifying the first layer. | 10-29-2015 |
20150371843 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided are a method of manufacturing a semiconductor device and a substrate processing apparatus. The method includes: forming a first layer including a first element on a substrate by supplying a gas containing the first element; forming a second layer including first and second elements by supplying a gas containing the second element to modify the first layer; and forming a thin film having a predetermined thickness by setting the forming of the first layer and the forming of the second layer to one cycle and repeating the cycle at least once. Pressure, or pressure and a gas supply time in one process of the forming of the first layer and the forming of the second layer are controlled to be higher or longer, or lower or shorter than pressure, or pressure and a time in the one process when the thin film having a stoichiometric composition is formed. | 12-24-2015 |
20160020092 | METHODS FOR DEPOSITING SILICON OXIDE - The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction. | 01-21-2016 |
20160033869 | PATTERN SHRINK METHODS - Pattern shrink methods comprise: (a) providing a semiconductor substrate comprising one or more layers to be patterned; (b) providing a resist pattern over the one or more layers to be patterned; (c) coating a shrink composition over the pattern, wherein the shrink composition comprises a polymer and an organic solvent, wherein the polymer comprises a group containing a hydrogen acceptor effective to form a bond with an acid group and/or an alcohol group at a surface of the resist pattern, and wherein the composition is free of crosslinkers; and (d) rinsing residual shrink composition from the substrate, leaving a portion of the polymer bonded to the resist pattern. Also provided are pattern shrink compositions, and coated substrates and electronic devices formed by the methods. The invention find particular applicability in the manufacture of semiconductor devices for providing high resolution patterns. | 02-04-2016 |
20160042940 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device includes: (a) forming a first film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a first precursor gas being a fluorine-free inorganic gas containing the metal element to the substrate; and (a-2) supplying a first reactant gas having reducibility to the substrate; (b) forming a second film containing the metal element on the first film by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a second precursor gas containing the metal element and fluorine to the substrate; and (b-2) supplying a second reactant gas having reducibility to the substrate; and (c) forming a film containing the metal element and obtained by the first film and the second film being laminated on the substrate by performing the (a) and (b). | 02-11-2016 |
20160093504 | METHOD FOR PRODUCING A MULTILEVEL MICROELECTRONIC STRUCTURE - The invention relates to a method for producing a multilevel microelectronic structure, comprising at least:
| 03-31-2016 |
20160118239 | GATE INSULATING LAYER AND METHOD FOR FORMING THE SAME - The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer. | 04-28-2016 |
20160163539 | METHODS FOR DEPOSITING SILICON OXIDE - The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction. | 06-09-2016 |
20160195333 | METHOD AND APPARATUS FOR HEAT-TREATING HIGH DIELECTRIC CONSTANT FILM | 07-07-2016 |
20160200569 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT | 07-14-2016 |