| Entries |
| Document | Title | Date |
|---|
| 20080206993 | Using Spectra to Determine Polishing Endpoints - Methods of determining a polishing endpoint are described using spectra obtained during a polishing sequence. In particular, techniques for using only desired spectra, faster searching methods and more robust rate determination methods are described. | 08-28-2008 |
| 20080214005 | Chemical solution feeding apparatus and method for preparing slurry - An apparatus for feeding slurry to an external device. The apparatus includes a preparation tank for preparing the slurry. A circulation pipe is connected to the preparation tank to circulate the slurry. A feeding pipe is connected between the preparation tank and the external device to feed the external device with the slurry. A pump sends the chemical solution in the preparation tank to the circulation pipe and the feeding pipe. A concentration detector is arranged downstream to the pump to detect the concentration of the slurry. A controller controls the concentration of the chemical solution in the preparation tank in accordance with the detection value of the concentration detector and controls the feeding of the chemical solution. | 09-04-2008 |
| 20080214006 | METHODS OF USING CORROSION-INHIBITING CLEANING COMPOSITIONS FOR METAL LAYERS AND PATTERNS ON SEMICONDUCTOR SUBSTRATES - Provided herein are methods for using corrosion-inhibiting cleaning compositions for semiconductor wafer processing that include an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids. The quantity of the corrosion-inhibiting compound in the admixture is preferably in a range from about 0.0001 wt % to about 0.1 wt % and the quantity of the surfactant is preferably in a range from about 0.001 wt % to about 1.0 wt %. The aqueous admixture may also include sulfuric acid and a fluoride, which act as oxide etchants, and a peroxide, which acts as a metal etchant. | 09-04-2008 |
| 20080227296 | SLURRY COMPOSITIONS, METHODS OF PREPARING SLURRY COMPOSITIONS, AND METHODS OF POLISHING AN OBJECT USING SLURRY COMPOSITIONS - A slurry composition includes an acidic aqueous solution and one or both of, an amphoteric surfactant and a glycol compound. Examples of the amphoteric surfactant include a betaine compound and an amino acid compound, and examples of the amino acid compound include lysine, proline and arginine. Examples of the glycol compound include diethylene glycol, ethylene glycol and polyethylene glycol. | 09-18-2008 |
| 20080233749 | METHODS AND APPARATUSES FOR REMOVING POLYSILICON FROM SEMICONDUCTOR WORKPIECES - Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other. | 09-25-2008 |
| 20080233750 | Method for forming fine patterns in semiconductor device - A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns. | 09-25-2008 |
| 20080242089 | Method for Distributed Processing at Copper CMP - A method of manufacturing a semiconductor device. A first thickness of a copper layer located over a semiconductor substrate is removed by chemical-mechanical polishing (CMP) on a first platen using a first polishing slurry. The copper layer is located over a barrier layer. A remaining thickness of the copper layer is removed on a second platen using a second polishing slurry. A portion of the barrier layer on the second platen is removed using a third polishing slurry. The third polishing slurry has a substantially different composition from the second polishing slurry. | 10-02-2008 |
| 20080242090 | METAL-POLISHING LIQUID AND POLISHING METHOD - A metal-polishing liquid used for chemical-mechanical polishing of a conductor film of copper or a copper alloy in a process for manufacturing a semiconductor device, the metal-polishing liquid comprising: (1) an amino acid derivative represented by the formula (I); and (2) a surfactant, | 10-02-2008 |
| 20080248649 | First inter-layer dielectric stack for non-volatile memory - A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer ( | 10-09-2008 |
| 20080261399 | METHOD FOR CHEMICAL MECHANICAL POLISHING IN A SCAN MANNER OF A SEMICONDUCTOR DEVICE - The chemical mechanical polishing of a semiconductor device includes polishing a target layer to be polished through a chemical reaction by slurry and a mechanical process by a polishing pad. Then performing a post cleaning composed of cleaning, rinsing and drying of the surface of the polished target layer. The parts for cleaning, rinsing and drying procedures are arranged in a row and the post cleaning is performed in a scan manner using a bar type module. Provided at the cleaning and rinsing parts, a solution supplying nozzle and a retrieving nozzle disposed at both sides of the solution supplying nozzle. Finally, removing the solution supplied to the target layer to be polished immediately after the solution comes in contact with the target layer. | 10-23-2008 |
| 20080261400 | POLISHING COMPOSITION, POLISHING METHOD, AND METHOD FOR FORMING COPPER WIRING FOR SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention provides a technique for realizing highly flat surface of a semiconductor integrated circuit employing copper as a wiring metal. | 10-23-2008 |
| 20080268643 | METHODS AND APPARATUS FOR POLISHING CONTROL - A CMP station can be closed loop controlled by using data obtained by an inline metrology station from a first polished wafer to affect the processing of subsequent polished wafers. The first wafer is polished and measured by the inline metrology station. The metrology station measures at various points the array dielectric thickness, field dielectric thickness, barrier residue thickness and metal residue thickness. The data is then inputted into an algorithm and polishing parameter outputs are calculated. The outputs are sent to the CMP station and used to supplement or replace the previous polishing parameters. Subsequent wafers are polished on the CMP station using the revised polishing parameters. | 10-30-2008 |
| 20080280441 | Method of Forming Isolation Layer of Flash Memory Device - An embodiment of the invention relates to a method of forming an isolation layer of a flash memory device. An isolation layer is formed using a PSZ-based material and a nitride film of liner form is deposited on a trench before the PSZ film is deposited. An oxide film can be prevented from remaining on a top of the sidewalls of a conductive film for a floating gate through an etch process employing the etch rate. The thickness of a dielectric film can be prevented from increasing when a dielectric film is deposited. Accordingly, the contact area of the floating gate and the dielectric film can be increased and the coupling ratio between the floating gate and the control gate can be improved. | 11-13-2008 |
| 20080311749 | DIELECTRIC TRENCHES, NICKEL/TANTALUM OXIDE STRUCTURES, AND CHEMICAL MECHANICAL POLISHING TECHNIQUES - A portion of a conductive layer ( | 12-18-2008 |
| 20080318425 | SEMICONDUCTOR DEVICE PRODUCTION METHOD - The purpose of the present invention is to stabilize the polishing film thickness during the overpolishing following the removal of barrier metal in Cu-CMP (chemical mechanical polishing). To this end, a table in which the relationship between wire perimeter and overpolishing process polishing rate is created. The polishing time is calculated based on the wire perimeter in determining the overpolishing time after the removal of barrier metal in Cu-CMP to stabilize the overpolishing film thickness. | 12-25-2008 |
| 20080318426 | WAFER RECYCLING METHOD - A wafer recycling method comprises varying a temperature and pressure conditions to remove a first semiconductor layer deposited on a wafer, removing a remaining semiconductor layer on the wafer through a chemical or physical process, and washing the wafer. | 12-25-2008 |
| 20090004860 | ATOMIC LAYER VOLATILIZATION PROCESS FOR METAL LAYERS - A two-stage method to remove a metal layer from a substrate surface comprises using a CMP process to remove a first portion of the metal layer from the substrate surface, and using an ALV process to remove a second portion of the copper layer from the substrate surface. The ALV process comprises pulsing a co-reactant into a reactor housing the substrate, wherein the co-reactant reacts with the metal layer to form a volatile metal-containing product, and then evacuating the reactor to volatize and remove the metal-containing product. | 01-01-2009 |
| 20090004861 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL - A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulation layer over the resultant structure, planarizing the hard mask pattern and the insulation layer until the pillars are exposed, and forming a storage electrode over the exposed pillars. | 01-01-2009 |
| 20090004862 | Method for forming fine patterns in semiconductor device - A method for forming fine patterns in a semiconductor device includes forming an etch stop layer and a sacrificial layer over an etch target layer, forming photoresist patterns over the sacrificial layer, etching the sacrificial layer by using the photoresist patterns as an etch barrier to form sacrificial patterns, forming spacers on both sidewalls of the sacrificial patterns, removing the sacrificial patterns, and etching the etch stop layer and the etch target layer by using the spacer as an etch barrier. | 01-01-2009 |
| 20090004863 | POLISHING LIQUID AND POLISHING METHOD USING THE SAME - The present invention provides a polishing liquid for polishing a ruthenium-containing barrier layer, the polishing liquid being used in chemical mechanical polishing for a semi-conductor device having a ruthenium-containing barrier layer and conductive metal wiring lines on a surface thereof, the polishing liquid comprising an oxidizing agent; and a polishing particulate having hardness of 5 or higher on the Mohs scale and having a composition in which a main component is other than silicon dioxide (SiO | 01-01-2009 |
| 20090011598 | Method of manufacturing semiconductor device including silicon carbide substrate - In a manufacturing method of a silicon carbide semiconductor device, a silicon carbide substrate is prepared by slicing an ingot that is made of silicon carbide single crystal. The silicon carbide substrate is heat treated for exposing a substrate defect generated at a surface portion of the silicon carbide substrate and the surface portion of the silicon carbide substrate is chemical-mechanical polished in such a manner that the exposed substrate defect is removed. Then, a semiconductor element is formed on the silicon carbide substrate. | 01-08-2009 |
| 20090023290 | Planarization method - A planarization method is provided. The method includes the steps of providing a substrate with a first region and a second region, and having a plurality of protrusions of different densities on a surface of said substrate; forming a first dielectric layer on the substrate to fill spaces between the plurality of protrusions; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is formed with a protruding tip having a height higher than heights of the protrusions; and partially removing said first dielectric layer and said second dielectric layer to planarize said first dielectric layer and said second dielectric layer and expose top surfaces of said protrusions. | 01-22-2009 |
| 20090029551 | Pad and method for chemical mechanical polishing - A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer. | 01-29-2009 |
| 20090035942 | Ruthenium CMP compositions and methods - The present invention provides a chemical-mechanical polishing (CMP) composition for polishing a ruthenium-containing substrate in the presence of an oxidizing agent such as hydrogen peroxide without forming a toxic level of ruthenium tetroxide during the polishing process. The composition comprises a particulate abrasive (e.g., silica, alumina, and/or titania) suspended in an aqueous carrier containing a ruthenium-coordinating oxidized nitrogen ligand (N—O ligand), such as a nitroxide (e.g., 4-hydroxy-TEMPO). In the presence of the oxidizing agent, the N—O ligand prevents the deposition of ruthenium species having an oxidation state of IV or higher on the surface of the substrate, and concomitantly forms a soluble Ru(II) N—O coordination complex with oxidized ruthenium formed during CMP of the substrate. CMP methods for polishing ruthenium-containing surfaces with the CMP composition are also provided. | 02-05-2009 |
| 20090042391 | METHODS FOR FORMING PATTERNS - A method for forming patterns comprises providing a substrate. A set of seed features is formed over the substrate. At least one bi-layer comprising a first layer followed by a second layer is formed on the set of seed features. The first layer and the second layer above the set of seed features are removed. The first layer and the second layer are anisotropically etched successively at least one time to form an opening next to the set of seed features. | 02-12-2009 |
| 20090042392 | Polishing apparatus, substrate manufacturing method, and electronic apparatus manufacturing method - A polishing apparatus is configured to simultaneously polish both surfaces of a work and includes a sun gear provided around a rotational axis of one of a pair of polishing surfaces, a carrier having a hole configured to house the work, and including teeth so as to serve as a planetary gear which rotates and revolves around the sun gear, and a first dustproof mechanism that includes a first elastic member that contacts one surface of the carrier opposite to one of the polishing surfaces between the sun gear and the hole in the carrier. | 02-12-2009 |
| 20090047785 | CMP Polishing Method, CMP Polishing Apparatus, and Process for Producing Semiconductor Device - When the remaining slurry and polishing residue are removed by cleaning with a cleaning liquid (preferably a cleaning liquid containing a surfactant), organic matter in the cleaning liquid containing a surfactant seeps into the interlayer insulating film | 02-19-2009 |
| 20090053895 | FILM FORMING METHOD OF POROUS FILM AND COMPUTER-READABLE RECORDING MEDIUM - There is provided a method for forming a porous dielectric film stably by: forming a surface densification layer by processing a surface of an SiOCH film formed by a plasma CVD process while using an organic silicon compound source; and releasing CHx groups or OH group from the SiOCH film underneath the surface densification layer by hydrogen plasma processing through the surface densification layer with a controlled rate. | 02-26-2009 |
| 20090068838 | METHOD FOR FORMING MICROPATTERNS IN SEMICONDUCTOR DEVICE - A method for forming micropatterns in a semiconductor device includes forming a first etch stop layer over a etch target layer, forming a second etch stop layer over the first etch stop layer, forming a first sacrificial layer over the second etch stop layer, etching portions of the first sacrificial layer and second etch stop layer to form first sacrificial patterns, forming an insulation layer along an upper surface of the first etch stop layer, forming a second sacrificial layer over the insulation layer to cover the insulation layer, planarizing the second sacrificial layer and the insulation layer to expose the first sacrificial patterns, removing the first sacrificial patterns and the second sacrificial layer, etching the second etch stop layer and insulation layer to thereby form second sacrificial patterns, etching the first etch stop layer, and etching the etch target layer. | 03-12-2009 |
| 20090068839 | Slurry, chemical mechanical polishing method using the slurry, and method of forming metal wiring using the slurry - A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor. | 03-12-2009 |
| 20090075479 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A substrate having a copper wiring is prepared. An insulating film is formed on the copper wiring. The insulating film is etched with a gas containing fluorine to form an opening reaching the copper wiring. A plasma treatment is carried out on a surface of copper exposed at a bottom of the opening without turning plasma discharge of f after forming the opening in the same chamber as the formation of the opening. | 03-19-2009 |
| 20090093118 | POLISHING COMPOSITION - In order to polish a wiring metal, a polishing composition ensuring that etching and erosion are suppressed and the residual wiring metal on the portion other than wiring is decreased, is provided, in which a polishing composition comprising (A) an azole group-containing compound having 3 or more azole groups within the molecule and a molecular weight of 300 to 15,000, (B) an oxidant, and (C) one, two or more acids selected from the group consisting of an amino acid, an organic acid and an inorganic acid is provided. | 04-09-2009 |
| 20090093119 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed, by which thickness of a gate oxide layer can be controlled for uniformity. Embodiments include sequentially forming a pad oxide layer and a nitride layer over a semiconductor substrate having an epi-layer grown thereon, the semiconductor substrate having a backside over which a backside nitride layer and a backside oxide layer are formed, forming a trench on the semiconductor substrate, depositing an oxide layer over a front side the semiconductor substrate to fill the trench with the oxide layer, selectively etching the oxide layer, performing a chemical mechanical polishing process on the front side of the semiconductor substrate, performing a chemical mechanical polishing process on the backside of the semiconductor substrate, and forming a gate oxide layer over the semiconductor substrate. | 04-09-2009 |
| 20090104778 | Polishing Composition for CMP and device wafer producing method using the same - Disclosed is a polishing composition for CMP which contains a polyglycerol derivative (A) represented by following Formula (1): | 04-23-2009 |
| 20090111267 | METHOD OF ANTI-STICTION DIMPLE FORMATION UNDER MEMS - A method for making a MEMS structure comprises patterning recesses in a dielectric layer overlying a substrate, each recess being disposed between adjacent mesas of dielectric material. A conformal layer of semiconductor material is formed overlying the recesses and mesas. The conformal layer is chemical mechanically polished to form a chemical mechanical polished surface, wherein the chemical mechanical polishing is sufficient to create dished portions of semiconductor material within the plurality of recesses. Each dished portion has a depth proximate a central portion thereof that is less than a thickness of the semiconductor material proximate an outer portion thereof. A semiconductor wafer is then bonded to the chemical mechanical polished surface. The bonded semiconductor wafer is patterned with openings according to the requirements of a desired MEMS transducer. Lastly, the MEMS transducer is released. Releasing advantageously exposes anti-stiction features formed from outer edges of the dished portion of semiconductor material. | 04-30-2009 |
| 20090111268 | REWORKING METHOD FOR INTEGRATED CIRCUIT DEVICES - A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method. | 04-30-2009 |
| 20090117740 | FLUID-CONFINING APPARATUS AND METHOD OF OPERATING THE SAME - The fluid-confining apparatus includes at least a substrate holder, at least a confining fluid supplying tube, at least a confining fluid recovering tube, at least a process fluid supplying tube, and at least a process fluid recovering tube. The process fluid supplying tube supplies at least a process fluid, and makes the process fluid contact with at least a treatment region of a wafer. The confining fluid supplying tube continuity supplies at least a confining fluid. The confining fluid does not dissolve the process fluid. The flowing confining fluid can contact with at least a non-treatment region of the wafer, and confines the process fluid into a predetermined space. | 05-07-2009 |
| 20090137120 | DAMPING POLYURETHANE CMP PADS WITH MICROFILLERS - A system for preparing a microcellular polyurethane material, includes a froth, prepared, for instance, by inert gas frothing a urethane prepolymer, preferably an aliphatic isocyanate polyether prepolymer, in the presence of a surfactant; a filler soluble in a CMP slurry; and a curative, preferably including an aromatic diamine and a triol. To produce the microcellular material, the froth can be combined with the filler, e.g., PVP, followed by curing the resulting mixture. The microcellular material has a low rebound and can dissipate irregular energy and stabilize polishing to yield improved uniformity and less dishing. CMP pads using the microcellular material have pores created by inert gas frothing throughout the pad polymer body and additional surface pores created by dissolution of fillers during polishing, providing flexibility in surface softness and pad stiffness. | 05-28-2009 |
| 20090137121 | Three-Dimensional Network in CMP Pad - The present disclosure is directed at a chemical-mechanical planarization polishing pad comprising interconnecting elements and a polymer filler material, wherein the interconnecting elements include interconnecting junction points that are present at a density of 1 interconnecting junction point/cm | 05-28-2009 |
| 20090170317 | CMP PROCESS FOR PROCESSING STI ON TWO DISTINCT SILICON PLANES - A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes. | 07-02-2009 |
| 20090170318 | METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process are not additionally blocked, and the oxide film is used as an etching barrier to obtain an accurate overlay between patterns and improve CD uniformity, thereby improving a characteristic of the device. | 07-02-2009 |
| 20090170319 | METHOD OF FORMING AN INTERLAYER DIELECTRIC MATERIAL HAVING DIFFERENT REMOVAL RATES DURING CMP - By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during the planarization of the interlayer dielectric layer stack prior to the formation of contact elements. | 07-02-2009 |
| 20090170320 | CMP SYSTEM AND METHOD USING INDIVIDUALLY CONTROLLED TEMPERATURE ZONES - By creating a temperature profile across a polishing pad, a respective temperature profile may be obtained in a substrate to be polished, which may result in a respective varying removal rate across the substrate for a chemically reactive slurry material or for an electro-chemically activated polishing process. Hence, highly sensitive materials, such as material comprising low-k dielectrics, may be efficiently polished with a high degree of controllability. | 07-02-2009 |
| 20090170321 | Method of Forming Isolation Layer of Semiconductor Memory Device - A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer. | 07-02-2009 |
| 20090170322 | Method for Manufacturing Semiconductor Device Including Vertical Transistor - A method for manufacturing a semiconductor device including a vertical transistor comprises: depositing a n-layered (here, n is an integer ranging from 2 to 6) mask film over a semiconductor substrate; forming a photoresist pattern over the n-layered mask film; etching the mask film with the photoresist pattern as an etching mask until the m | 07-02-2009 |
| 20090170323 | CHEMICAL MECHANICAL POLISHING METHOD AND CHEMICAL MECHANICAL POLISHING DEVICE - A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R | 07-02-2009 |
| 20090191710 | CMP method for improved oxide removal rate - The invention provides a method for the chemical-mechanical polishing of a substrate with a chemical-mechanical polishing composition that comprises an abrasive, a halide salt, water and a polishing pad. | 07-30-2009 |
| 20090203213 | Slurry composition for chemical-mechanical polishing and method of chemical-mechanical polishing with the same - Provided may be a slurry composition for chemical mechanical polishing (CMP) and a CMP method using the same. For example, the slurry composition may include a first polishing inhibitor including at least one of PO | 08-13-2009 |
| 20090203214 | SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE OBTAINED BY SUCH A METHOD - The invention relates to a method of manufacturing a semiconductor device ( | 08-13-2009 |
| 20090209102 | Use of CMP to contact a MTJ structure without forming a via - A process is described for making contact to the buried capping layers of GMR and MTJ devices without the need to form and fill via holes. CMP is applied to the structure in three steps: ( | 08-20-2009 |
| 20090215265 | Low-stain polishing composition - The invention is an aqueous composition useful for chemical mechanical polishing of a patterned semiconductor wafer containing a copper interconnect metal. The aqueous composition includes an oxidizer, an inhibitor for the copper interconnect metal, 0.001 to 15 weight percent of a water soluble modified cellulose, non-saccaride water soluble polymer, 0 to 15 complexing agent for the copper interconnect metal, 0 to 15 weight percent phosphorus compound, 0.05 to 20 weight percent of an acid compound that is capable of complexing copper ions, and water; and the solution has an acidic pH. | 08-27-2009 |
| 20090215266 | Polishing Copper-Containing patterned wafers - An aspect of the invention provides a method for polishing a patterned semiconductor wafer containing a copper interconnect metal with a polishing pad. The method includes the following: a) providing an aqueous polishing solution, the polishing solution containing an benzotriazole (BTA) inhibitor and a copper complexing compound and water; b) polishing the patterned wafer with the aqueous polishing solution and the polishing pad in a manner that dissolves copper into Cu | 08-27-2009 |
| 20090215267 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: polishing a semiconductor substrate to expose a polysilicon film on the semiconductor substrate using a chemical mechanical polishing method; cleaning the semiconductor substrate using a first acid cleaning solution; cleaning the semiconductor substrate with an ultrasonic wave using a second cleaning solution after cleaning the semiconductor substrate with said first acid cleaning solution; and cleaning the semiconductor substrate using a third cleaning solution, which is alkaline, after cleaning the semiconductor substrate with an ultrasonic wave. | 08-27-2009 |
| 20090233444 | POLISHING METHOD WITH INERT GAS INJECTION - A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process. | 09-17-2009 |
| 20090239379 | Methods of Planarization and Electro-Chemical Mechanical Polishing Processes - A method of removing a material from a surface includes providing a substrate comprising a material having a surface, contacting the surface with a polishing medium, applying a voltage to the substrate to remove material from the surface, and changing the voltage during the removing material from the surface. An electrochemical mechanical polishing method includes providing a substrate having a surface, applying a platen to the surface, applying a first voltage to the substrate, rotating the platen and surface relative to each other at a first rotational speed, increasing to a second voltage, and decreasing to a second rotational speed. | 09-24-2009 |
| 20090246955 | WAFER PROCESSING METHOD AND WAFER PROCESSING APPARATUS - A wafer processing method is provided comprising the steps of: holding a wafer ( | 10-01-2009 |
| 20090258492 | MULTIPLE SPACER STEPS FOR PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 10-15-2009 |
| 20090269927 | METHOD FOR PITCH REDUCTION IN INTEGRATED CIRCUIT FABRICATION - A method for patterning a material is provided. The method includes patterning a second material over a first material over a substrate. A surface portion of the patterned second material is converted to form a third material and a remaining patterned second material, wherein the third material is around the remaining patterned second material. One of the remaining patterned second material and the third material is removed to form a mask. The first material is patterned by using the mask. | 10-29-2009 |
| 20090269928 | METHOD FOR MANUFACTURING PHASE CHANGE MEMORY DEVICE - A method for manufacturing a phase change memory device that prevents or minimizes adverse performance characteristics associated with inadequate overlap between top electrode contacts and top electrodes. The method prevents or minimizes unwanted chemical changes and etch losses of the phase change material when building the top electrode. The method includes forming spacers on sidewalls of remaining portions of the insulation layer and the hard masks so that subsequent etching of the conductive layer and the phase change material layer uses the spacers and the hard masks as an etch mask to form top electrodes and a phase change layer. Accordingly, the method promises to provide a way of achieving a high level of integration for the resultant phase change memory devices. | 10-29-2009 |
| 20090298289 | Chemical Mechanical Polishing Composition for Copper Comprising Zeolite - The present invention relates to a novel slurry composition for copper polishing, comprising zeolite which is a porous crystalline material for CMP of copper film in a semiconductor manufacturing process. The slurry composition according to the present invention comprises zeolite, an oxidant and a polish promoting agent and may further comprise a corrosion inhibitor, a surfactant, an aminoalcohol, an antiseptic and a dispersion agent and pH is in a range of 1 to 7. The zeolite slurry according to the present invention has advantages of absorbing and removing metal cation generated in CMP process by using zeolite and having a low level of scratches as the zeolite has micropores therein and thus its hardness is low. The slurry composition using zeolite of the present invention is usable to both first and second step polishing of copper damascene process and particularly useful as the first step polishing slurry for copper. | 12-03-2009 |
| 20090325382 | BEVEL ETCHER AND THE RELATED METHOD OF FLATTENING A WAFER - The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region. | 12-31-2009 |
| 20090325383 | CHEMICAL MECHANICAL POLISHING AQUEOUS DISPERSION AND CHEMICAL MECHANICAL POLISHING METHOD FOR SEMICONDUCTOR DEVICE - A chemical mechanical polishing aqueous dispersion according to the invention includes (A) 0.1 to 4 mass % of colloidal silica having an average particle diameter of 10 to 100 nm, and (B) 0.1 to 3 mass % of at least one ammonium salt selected from ammonium phosphate, diammonium phosphate, and ammonium hydrogen sulfate, the chemical mechanical polishing aqueous dispersion having a mass ratio (A)/(B) of the component (A) to the component (B) of 1 to 3 and a pH of 4 to 5 and being able to simultaneously polish at least two films that form a polishing target surface and are selected from a polysilicon film, a silicon nitride film, and a silicon oxide film. | 12-31-2009 |
| 20090325384 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming a first insulating film on a low dielectric constant film; etching the first insulating film and the low dielectric constant film to form a trench in a region in which the wiring layer is to be formed; forming a first barrier metal film in the trench and on the first insulating film; forming a film of a conductive material on the first barrier metal film, thereby burying the conductive material in the trench to form a conductor layer; polishing and planarizing the conductor layer, the first barrier metal film and the first insulating film by CMP using a slurry, wherein the first insulating film is not completely removed; and etching the remained first insulating film after the planarization by the CMP manner. | 12-31-2009 |
| 20090325385 | Method for manufacturing silicon wafer - A method for manufacturing a silicon wafer is characterized by performing one or both of grinding and polishing to a thin discoid silicon wafer to give bowl-shaped warpage that is concave at a central part to a wafer surface. One main surface of the thin discoid silicon wafer is adsorbed and held, and one or both of grinding and polishing are performed to the other main surface to fabricate a convex wafer whose thickness is increased from a wafer outer periphery toward a wafer center or fabricate a concave wafer whose thickness is reduced from the wafer outer periphery toward the wafer center. Then, the other main surface is adsorbed and held to protrude the center or the periphery of the one main surface side based on elastic deformation. One or both of grinding and polishing are carried out with respect to the one main surface to flatten the main surface, and adsorption and holding are released to give bowl-shaped warpage that is concave at the central part to the other main surface or the one main surface. By the method, an SOI wafer or an epitaxial silicon wafer having a high degree of flatness is obtained. | 12-31-2009 |
| 20100003821 | WETTING AGENT FOR SEMICONDUCTORS, AND POLISHING COMPOSITION AND POLISHING METHOD EMPLOYING IT - To provide a wetting agent for semiconductors and a polishing composition whereby the wettability of a semiconductor substrate surface can be improved, and microdefects such as particle attachments can be remarkably reduced. | 01-07-2010 |
| 20100009537 | METHOD OF POLISHING NICKEL-PHOSPHOROUS - The invention is directed to a method of chemically-mechanically polishing a a surface of a substrate, comprising contacting a surface of a substrate comprising nickel-phosphorous with a chemical-mechanical polishing composition comprising wet-process silica, an agent that oxidizes nickel-phosphorous, and an aminopolycarboxylic acid, wherein the polishing composition has a pH of about 1 to about 5, and abrading at least a portion of the nickel-phosphorous to polish the substrate. | 01-14-2010 |
| 20100009538 | Silicon nitride polishing liquid and polishing method - A silicon nitride polishing liquid for chemical mechanical polishing of a body to be polished in a planarization process for manufacturing of a semiconductor integrated circuit, the body to be polished including at least a first layer containing silicon nitride and a second layer containing at least one silicon-including material selected from the group consisting of polysilicon, modified polysilicon, silicon oxide, silicon carbide, and silicon oxycarbide, the silicon nitride polishing liquid having a pH of 2.5 to 5.0, and including (a) colloidal silica, (b) an organic acid that has at least one sulfonic acid group or phosphonic acid group in the molecular structure thereof and functions as a polishing accelerator for silicon nitride, and (c) water. | 01-14-2010 |
| 20100015805 | Wet Etching Methods for Copper Removal and Planarization in Semiconductor Processing - Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer. In some embodiments, the etching solutions further include pH adjustors, such as sulfuric acid, aminoacids, and carboxylic acids. | 01-21-2010 |
| 20100029079 | Chemical mechanical polishing composition and methods relating thereto - A chemical mechanical polishing composition useful for chemical mechanical polishing of a patterned semiconductor wafer containing a nonferrous metal. The chemical mechanical polishing composition comprises an inhibitor for the nonferrous metal; a copolymer of poly(ethylene glycol)methyl ether (meth)acrylate and 1-vinylimidazole; and water. | 02-04-2010 |
| 20100048020 | Nanoscale Electrodes for Phase Change Memory Devices - A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions. | 02-25-2010 |
| 20100048021 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A region corresponding to a convex pattern of a first insulating film deposited above a semiconductor substrate having a plurality of convex patterns is removed by anisotropic etching up to a top surface of the convex patterns, the convex patterns are exposed, and a convex portion of the first insulating film is formed. Subsequently, a second insulating film is deposited above the semiconductor substrate, the convex portion of the first insulating film and the second insulating film that covers the convex portion are removed to a surface height of the second insulating film at least on the convex patterns by a CMP process to perform planarization. | 02-25-2010 |
| 20100055906 | TWO-STEP HARDMASK FABRICATION METHODOLOGY FOR SILICON WAVEGUIDES - Techniques are disclosed for efficiently fabricating semiconductors including waveguide structures. In particular, a two-step hardmask technology is provided that enables a stable etch base within semiconductor processing environments, such as the CMOS fabrication environment. The process is two-step in that there is deposition of a two-layer hardmask, followed by a first photolithographic pattern, followed by a first silicon etch, then a second photolithographic pattern, and then a second silicon etch. The process can be used, for example, to form a waveguide structure having both ridge and channel configurations, or a waveguide (ridge and/or channel) and a salicide heater structure, all achieved using the same hardmask. The second photolithographic pattern allows for the formation of the lower electrical contacts to the waveguides (or other structures) without a complicated rework of the hardmask. | 03-04-2010 |
| 20100055907 | Method for achieving very small feature size in semiconductor device by undertaking silicide sidewall growth and etching - In the present method of fabricating a semiconductor device, initially, a semiconductor substrate is provided. An oxide layer is provided on and in contact with the substrate, and a polysilicon layer is provided on and in contact with the oxide layer. A layer of photoresist is provided on the polysilicon layer, and the photoresist is patterned to provide a photoresist body, which is used as a mask to etch away polysilicon and oxide, forming a polysilicon element thereunder. The photoresist body is then removed. A nickel layer is provided on the resulting structure, and a reaction step is undertaken to provide that nickel diffuses into the exposed top and side portions of the polysilicon body, forming nickel silicide. After the reaction step, the remaining nickel is removed, and a chemical-mechanical polishing step is undertaken to remove nickel silicide so that a pair of nickel silicide bodies remain, separated by polysilicon. Using the nickel silicide bodies as masks, the polysilicon and oxide thereunder are etched away. | 03-04-2010 |
| 20100055908 | METHOD FOR PRODUCING A SEMICONDUCTOR WAFER - A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 μm to 30 μm of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO | 03-04-2010 |
| 20100055909 | SEMICONDUCTOR POLISHING COMPOUND, PROCESS FOR ITS PRODUCTION AND POLISHING METHOD - A semiconductor polishing compound comprising cerium oxide abrasive grains, water and an additive, wherein the additive is a water-soluble organic polymer such as ammonium polyacrylate or an anionic surfactant, the pH at 25° C. is from 3.5 to 6, and the concentration of the additive is from 0.01 to 0.5% based on the total mass of the polishing compound. This polishing compound simultaneously has dispersion stability, excellent scratch characteristics and excellent polishing planarization characteristics. In particular, this polishing compound provides excellent planarization characteristics having dishing fluctuation reduced, when used for polishing a semiconductor substrate having a silicon nitride film | 03-04-2010 |
| 20100062601 | METHODS FOR POLISHING ALUMINUM NITRIDE - The present invention provides a method for polishing an aluminum nitride substrate. The method comprises abrading a surface of the aluminum nitride substrate with a basic, aqueous polishing composition, which comprises an abrasive (e.g., colloidal silica), an oxidizing agent (e.g., hydrogen peroxide), and an aqueous carrier. The methods of the invention provide for substantially improved polishing rates relative to conventional methods that do not utilize an oxidizing agent in the polishing slurry. | 03-11-2010 |
| 20100075500 | Metal polishing slurry and chemical mechanical polishing method - The invention provides a metal polishing slurry containing a compound represented by the general formula (1): (X | 03-25-2010 |
| 20100081280 | METHOD OF PRODUCING A MIXED SUBSTRATE - The invention concerns a method of producing a mixed substrate, that is to say a substrate comprising at least one block of material different from the material of the substrate, the method comprising the following successive steps:
| 04-01-2010 |
| 20100087065 | STABILIZATION OF POLYMER-SILICA DISPERSIONS FOR CHEMICAL MECHANICAL POLISHING SLURRY APPLICATIONS - Chemical mechanical polishing (CMP) compositions and single CMP platen process for the removal of copper and barrier layer material from a microelectronic device substrate having same thereon. The process includes the in situ transformation of a copper removal CMP composition, which is used to selectively remove and planarize copper, into a barrier removal CMP composition, which is used to selectively remove barrier layer material, on a single CMP platen pad. | 04-08-2010 |
| 20100093174 | METHOD OF MANUFACTURING LOW-K DIELECTRIC FILM, AND FORMATION OF AIR-GAP USING THE LOW-K DIELECTRIC FILM - A dielectric film, a method of manufacturing a dielectric film and a method of forming an air-gap. A method of manufacturing a low-k dielectric film may include introducing TMS and 3,3-dimethyl-1-butene into a plasma deposition reactor, polymerizing TMS and 3,3-dimethyl-1-butene using plasma generated in a reactor to deposit an insulation film over a substrate disposed in a reactor and/or subjecting a deposited insulation film to heat treatment concurrently with an inductively coupled plasma (ICP) process. A dielectric film may have a dielectric constant up to approximately 3. A method of forming an air-gap may include depositing a first insulation film over a surface of a patterned substrate, depositing a decahydronaphthalene layer over a portion of a first insulation film, subjecting a patterned substrate to a polishing process, forming a second insulation film, and/or subjecting a second insulation film to heat treatment concurrently with an ICP process. | 04-15-2010 |
| 20100099259 | POLISHING COMPOSITION AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In polishing of a to-be-polished surface in the production of a semiconductor integrated circuit device, a flat surface of an insulating layer having an embedded metal interconnect can be obtained. Further, a semiconductor integrated circuit device having a highly planarized multilayer structure can be obtained. Provided is a polishing composition which is a chemical mechanical polishing composition for polishing a to-be-polished surface of a semiconductor integrated circuit device, contains one or more oxidizing agents selected from the group consisting of hydrogen peroxide, ammonium persulfate and potassium persulfate, an abrasive grain, an alicyclic resin acid, a basic compound and inorganic acid, and has a pH ranging from 8 to 12. | 04-22-2010 |
| 20100112816 | METHOD OF REDUCING NON-UNIFORMITIES DURING CHEMICAL MECHANICAL POLISHING OF MICROSTRUCTURE DEVICES BY USING CMP PADS IN A GLAZED MODE - In sophisticated CMP recipes, the material removal may be accomplished on the basis of a chemically reactive slurry material and a reduced down force, wherein the surface topography of a finally obtained material layer may be enhanced by using, at least in a final phase, a glazed state of the polishing pad. | 05-06-2010 |
| 20100120248 | ETCHING SOLUTION AND ETCHING METHOD - An etching solution contains water, nitric acid, hydrofluoric acid, and sulphuric acid. More specifically it contains 15 to 40% by weight of nitric acid, 10 to 41% by weight of sulphuric acid and 0.8 to 2.0% by weight of hydrofluoric acid. The etching solution is used for etching silicon and to etching methods for silicon wafers. | 05-13-2010 |
| 20100120249 | PROCESS FOR PRODUCING POLYURETHANE FOAM - A method for manufacturing a polishing pad containing substantially spherical cells and having high thickness accuracy includes preparing a cell-dispersed urethane composition by a mechanical foaming method; continuously discharging the cell-dispersed urethane composition from a single discharge port to a substantially central portion in the width direction of a face material A, while feeding the face material A; laminating a face material B on the cell-dispersed urethane composition; then uniformly adjusting the thickness of the cell-dispersed urethane composition by thickness adjusting means; curing the cell-dispersed urethane composition with the thickness adjusted in the preceding step without applying any additional load to the composition so that a polishing sheet including a polyurethane foam is formed; and cutting the polishing sheet. | 05-13-2010 |
| 20100151683 | Chemical mechanical polishing composition and methods relating thereto - A method for chemical mechanical polishing of a substrate comprising a barrier material in the presence of at least one of an interconnect metal and a low-k dielectric material using a chemical mechanical polishing composition comprising water; 1 to 40 wt % abrasive having an average particle size of ≦100 nm; 0.001 to 5 wt % quaternary compound; a material having a formula (I): | 06-17-2010 |
| 20100159697 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include forming a first oxide film, a nitride film and/or a second oxide film over a substrate, and may include forming a trench over a semiconductor substrate by etching a portion of a first oxide film, a nitride film, a second oxide film and/or a semiconductor substrate. A method of manufacturing a semiconductor device may include performing wet etching to form a divot, which may be performed over a semiconductor substrate having a trench, and/or which may expose a portion of a nitride film. A method of manufacturing a semiconductor device may include removing a second oxide film having a portion thereof etched and a portion of a first oxide film exposed by a divot, while rounding upper edge portions of a trench using a mixed solution of deionized water and HF. A semiconductor device formed by a method is disclosed. | 06-24-2010 |
| 20100178765 | Metal Polishing Slurry and Method of Polishing a Film to be Polished - The present invention provides a metal polishing liquid capable of CMP at a high Cu polishing rate and solving the problems: (a) generation of scratches attributable to solid particles, (b) generation of deteriorations in flatness such as dishing and erosion, (c) complexity in a washing process for removing abrasive particles remaining on the surface of a substrate after polishing, and (d) higher costs attributable to the cost of a solid abrasive itself and to waste liquid treatment, as well as a method of polishing a film to be polished by using the same. Disclosed are a metal polishing liquid which comprises a metal oxidizer, a metal oxide solubilizer, a metal anticorrosive, and a water-soluble polymer having an anionic functional group with a weight-average molecular weight of 8,000 or more and has pH 1 or more to 3 or less, and a method of polishing a film to be polished, which comprises supplying the above metal polishing liquid onto a polishing cloth of a polishing platen and simultaneously relatively moving the polishing platen and a substrate having a metallic film to be polished while the substrate is pressed against the polishing cloth. | 07-15-2010 |
| 20100178766 | HIGH-YIELD METHOD OF EXPOSING AND CONTACTING THROUGH-SILICON VIAS - An assembly including a main wafer having a body with a front side and a back side, and a handler wafer, is obtained. The main wafer has a plurality of blind electrical vias terminating above the back side. The blind electrical vias have conductive cores with surrounding insulator adjacent side and end regions of the cores. The handler wafer is secured to the front side of the body of the main wafer. An additional step includes exposing the blind electrical vias on the back side. The blind electrical vias are exposed to various heights across the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side, to open the dielectric only adjacent the conductive cores of the vias. | 07-15-2010 |
| 20100178767 | CHEMICAL-MECHANICAL POLISHING COMPOSITION COMPRISING METAL-ORGANIC FRAMEWORK MATERIALS - The present invention relates to compositions for chemical-mechanical polishing comprising A 0.01% to 40% by weight based on the total amount of the composition of abrasive particles of at least one porous metal-organic framework material, wherein the framework material comprises at least one at least bidentate organic compound which is coordinately bound to at least one metal ion; B 40% to 99.8% by weight based on the total amount of the composition of a liquid carrier; and C 0.01% to 20% by weight based on the total amount of the composition of a polishing additive component. The invention further relates to the use of said composition as well as methods for chemical-mechanical polishing of a surface with the aid of said compositions. | 07-15-2010 |
| 20100178768 | CONTROLLING PASSIVATING FILM PROPERTIES USING COLLOIDAL PARTICLES, POLYELECTROLYTES, AND IONIC ADDITIVES FOR COPPER CHEMICAL MECHANICAL PLANARIZATION - The present invention provides for a copper CMP slurry composition which comprises a complexing agent, an oxidizer, an abrasive and a passivating agent. The present invention also provides for a method of chemical mechanical planarization of a copper conductive structure which comprises administering the copper CMP slurry composition during the planarization process. | 07-15-2010 |
| 20100184291 | AQUEOUS SLURRY COMPOSITION FOR CHEMICAL MECHANICAL POLISHING AND CHEMICAL MECHANICAL POLISHING METHOD - The present invention relates to an aqueous slurry composition for chemical mechanical polishing that can show good polishing rate to the target layer, and yet has a high polishing selectivity and can maintain superior surface condition of the target layer after polishing, and a chemical mechanical polishing method. | 07-22-2010 |
| 20100203729 | COMPOSITION FOR CHEMICAL MECHANICAL POLISHING - Provided is a composition for use in chemical mechanical polishing. The composition includes an amino acid and its derivatives, a surfactant, and an additive that increases the swelling of polishing particles. | 08-12-2010 |
| 20100221917 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device having low interface state density in an interface region between a gate insulating film and a silicon carbide layer is provided. An epitaxially grown layer is grown on a 4H-SiC substrate, and thereafter ion implantation is performed to form a p well region, a source region and a p+ contact region that are ion implantation layers. Thereafter, using thermal oxidation or CVD, the gate insulating film formed by a silicon oxide film is formed on the p well region, the source region and the p+ contact region. Then, plasma is generated using a gas containing N2O, which is the gas containing at least any one of oxygen and nitrogen, so as to expose the gate insulating film to plasma. | 09-02-2010 |
| 20100248478 | METHOD OF PROCESSING A SURFACE OF GROUP III NITRIDE CRYSTAL AND GROUP III NITRIDE CRYSTAL SUBSTRATE - There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains. | 09-30-2010 |
| 20100267238 | METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING PLANARIZED SPACERS - Methods of fabricating a semiconductor device on and in a semiconductor substrate are provided. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, wherein the sacrificial mandrel has sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having an upper portion and a lower portion. The upper portion of the sidewall spacers is removed. The sacrificial mandrel is removed and the semiconductor substrate is etched using the lower portion of the sidewall spacers as an etch mask. | 10-21-2010 |
| 20100273330 | RINSE FORMULATION FOR USE IN THE MANUFACTURE OF AN INTEGRATED CIRCUIT - The present invention relates to a solution for treating a surface of a substrate for use in a semiconductor device. More particularly, the present invention relates to a liquid rinse formulation for use in semiconductor processing, wherein the liquid formulation contains: i. a surface passivation agent; and ii. an oxygen scavenger, wherein the pH of the rinse formulation is 8.0 or greater. | 10-28-2010 |
| 20100323521 | PATTERNING METHOD - A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern. | 12-23-2010 |
| 20110008964 | SYSTEMS AND METHODS FOR DELIVERY OF FLUID-CONTAINING PROCESS MATERIAL COMBINATIONS - Common sources of different (e.g., concentrated) process materials are controllably supplied to multiple blending manifolds associated with multiple process tools, processing stations, or other points of use, to create an independently controllable process material blend for each tool, station, or point of use. Multi-constituent process materials may be circulated from a supply container through a blending manifold to a return container to ensure homogeneity until immediately prior to blending and use. Such containers may include liner-based containers adapted for pressure dispensation. | 01-13-2011 |
| 20110021026 | METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING L-SHAPED SPACERS - Methods for fabricating semiconductor structures, such as fin structures of FinFET transistors, are provided. In one embodiment, a method comprises providing a semiconductor substrate and forming a plurality of mandrels overlying the semiconductor substrate. Each of the mandrels has sidewalls. L-shaped spacers are formed about the sidewalls of the mandrels. Each L-shaped spacer comprises a rectangular portion disposed at a base of a mandrel and an orthogonal portion extending from the rectangular portion. Each L-shaped spacer also has a spacer width. The orthogonal portions are removed from each of the L-shaped spacers leaving at least a portion of the rectangular portions. The semiconductor substrate is etched to form fin structures, each fin structure having a width substantially equal to the spacer width. | 01-27-2011 |
| 20110027994 | POLISHING SLURRY FOR CMP - A polishing liquid for CMP has a composition loaded with, for example, an inorganic salt, a protective film forming agent and a surfactant capable of imparting a dissolution accelerating activity to enlarge a difference between polishing speed under non-load and polishing speed under load. By virtue of this polishing liquid for CMP, there can be simultaneously accomplished a speed increase for increasing CMP productivity, and wiring planarization for miniaturization and multilayer formation of wiring. | 02-03-2011 |
| 20110027995 | CLEANING SOLUTION FOR SUBSTRATE FOR SEMICONDUCTOR DEVICE - A cleaning solution of the present invention contains a sodium ion, a potassium ion, an iron ion, an ammonium salt of a sulfuric ester represented by General Formula (1), and water, and each content of the sodium ion, the potassium ion, and the iron ion is 1 ppb to 500 ppb. ROSO | 02-03-2011 |
| 20110053377 | POLISHING PAD - An object of the present invention is to provide a polishing pad that is prevented from causing an end-point detection error due to a reduction in light transmittance from the early stage to the final stage of the process, and to provide a method of producing a semiconductor device with the polishing pad. The present invention is directed to a polishing pad, comprising a polishing layer comprising a polishing region and a light-transmitting region, wherein a polishing side surface of the light-transmitting region is subjected to a surface roughness treatment, and the light-transmitting region has a light transmittance of 40% to 60% at a wavelength of 600 nm before use. | 03-03-2011 |
| 20110070735 | Method and Composition for Chemical Mechanical Planarization of a Metal-Containing Substrate - A composition and associated method for chemical mechanical planarization of a metal-containing substrate afford low dishing levels in the polished substrate while simultaneously affording high metal removal rates. Suitable metal-containing substrates include tungsten- and copper-containing substrates. Components in the composition include a silatrane compound, an abrasive, and, optionally, a strong oxidizing agent, such as a per-compound. | 03-24-2011 |
| 20110124194 | METHODS OF MANUFACTURING SEMICONDUCTORS USING DUMMY PATTERNS - A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern. | 05-26-2011 |
| 20110130002 | Methods and Apparatus for Edge Chamfering of Semiconductor Wafers Using Chemical Mechanical Polishing - Methods and apparatus for processing edge portions of a donor semiconductor wafer include controlling chemical mechanical polishing parameters to achieve chamfering of the edges of the donor semiconductor wafer; and alternatively or additionally flexing the donor semiconductor wafer to present a concave configuration, where edge portions thereof are pronounced as compared to a central surface area thereof, such that the pronounced edge portions of the donor semiconductor wafer are preferentially polished against a polishing surface in order to achieve the chamfering. | 06-02-2011 |
| 20110130003 | METHOD AND APPARATUS FOR CONFORMABLE POLISHING - Methods and apparatus provide for a conformable polishing head for uniformly polishing a workpiece. The polishing head includes an elastic polishing pad mounted on an elastic membrane that seals a cavity in the polishing head. The cavity is pressurized to expand the membrane and press the polishing pad down on the top surface of the workpiece, such that the polishing pad conforms to the surface and applies a substantially uniform pressure distribution across the workpiece and thereby uniformly removes material across high and low spots on the workpiece. | 06-02-2011 |
| 20110143539 | POLISHING PAD WITH ENDPOINT WINDOW AND SYSTEMS AND METHODS USING THE SAME - A polishing pad including a path therethrough to transmit a signal for in situ monitoring of an endpoint in a polishing operation. In one embodiment, the polishing pad includes a polishing composition distribution layer on a first side of a guide plate and a support layer on an opposed second side of a guide plate. The guide plate retains a plurality of polishing elements that extend along a first direction substantially normal to a plane including the polishing pad and through the polishing composition distribution layer. The polishing pad includes an optical path along the first direction and through a thickness of the pad. | 06-16-2011 |
| 20110143540 | Semiconductor Wafer Handler - A semiconductor wafer handler comprises a ring ( | 06-16-2011 |
| 20110165777 | Method and Slurry for Tuning Low-K Versus Copper Removal Rates During Chemical Mechanical Polishing - A composition and associated method for the chemical mechanical planarization (CMP) of metal substrates on semiconductor wafers are described. The composition contains a nonionic fluorocarbon surfactant and a per-type oxidizer (e.g., hydrogen peroxide). The composition and associated method are effective in controlling removal rates of low-k films during copper CMP and provide for tune-ability in removal rates of low-k films in relation to removal rates of copper, tantalum, and oxide films. | 07-07-2011 |
| 20110171831 | FABRIC CONTAINING NON-CRIMPED FIBERS AND METHODS OF MANUFACTURE - A chemical-mechanical planarization pad for semiconductor manufacturing is provided. The pad comprises synthetic fibers that are non-crimped fibers which are present in an amount of 1.0% by weight to 98.0% by weight in the mat and wherein the non-crimped fibers have a length of 0.1 cm to 127 cm and a diameter of 1.0 to 1000 micrometers. | 07-14-2011 |
| 20110189855 | METHOD FOR CLEANING SURFACE CONTAINING Cu - A method for cleaning a surface is disclosed. First, a substrate including Cu and a barrier layer is provided. Second, a first chemical mechanical polishing procedure is performed on the substrate. Then, a second chemical mechanical polishing procedure is performed on the barrier layer. The second chemical mechanical polishing procedure includes performing a main chemical mechanical polishing procedure to partially remove the barrier layer and performing a chemical buffing procedure on the substrate using a chemical solution which has a pH value of about 6 to about 8 to remove residues on the substrate after the main chemical mechanical polishing procedure. Later, a water rinsing procedure is performed on the substrate. Afterwards, a post clean procedure is performed on the substrate after the second chemical mechanical polishing procedure. | 08-04-2011 |
| 20110189856 | High Sensitivity Real Time Profile Control Eddy Current Monitoring System - A method of chemical mechanical polishing a metal layer on a substrate includes polishing the metal layer on the substrate at first and second polishing stations, monitoring thickness of the metal layer during polishing at the first and second polishing station with first and second eddy current monitoring systems having different resonant frequencies, and controlling pressures applied by a carrier head to the substrate during polishing at the first and second polishing stations to improve uniformity based on thickness measurements from the first and second eddy current monitoring systems. | 08-04-2011 |
| 20110189857 | CHEMICAL MECHANICAL POLISHING APPARATUS, CHEMICAL MECHANICAL POLISHING METHOD, AND CONTROL PROGRAM - Scratches and dishing are prevented from being generated when copper, which is deposited on an interlayer insulating film formed of an organic low-k film, is polished during a damascene process. In the CMP apparatus, while a rotating center axis of a rotating head, which has a polishing pad attached thereon, and a rotating center axis of a rotating table, which has a semiconductor wafer disposed face-up thereon, are aligned on the same vertical line, and the rotating head and the rotating table are spin-rotating in the same direction, the rotating head is lowered and the polishing pad touches the semiconductor wafer on the rotating table. Accordingly the polishing pad is prevented from scrubbing in a direction opposite to the rotating direction of the semiconductor wafer in the entire surface of the semiconductor wafer. | 08-04-2011 |
| 20110195575 | NOVEL HARD MASK REMOVAL METHOD - The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal. | 08-11-2011 |
| 20110212620 | POST-PLANARIZATION DENSIFICATION - Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma. | 09-01-2011 |
| 20110244683 | Fabricating Voids Using Slurry Protect Coat Before Chemical-Mechanical Polishing - A semiconductor structure is fabricated with a void such as a line, contact, via or zia. To prevent slurry particles from falling into and remaining in a void during a chemical-mechanical planarization process, a protective coat is provided in the void to trap the slurry particles and limit an extent to which they can enter the void. A metal layer is provided above the protective coat. Subsequently, the protective coat and trapped slurry particles are removed by cleaning, leaving a void which is substantially free of slurry particles. This is beneficial such as when the void is used as an alignment mark. The protective coat can be an organic layer such as spin-on carbon or i-line photoresist, an ashable material such as amorphous carbon, or a dissolvable and selective material such as SiN. | 10-06-2011 |
| 20110244684 | POLISHING LIQUID AND POLISHING METHOD - Provided is a polishing liquid which is used for chemical mechanical polishing of a body to be polished having a layer containing polysilicon or a modified polysilicon, and using which the polishing rate of a layer containing a silicon-based material other than polysilicon is high and polishing of the layer containing polysilicon can be selectively suppressed. The polishing liquid includes components (A), (B), and (C), has a pH of from 1.5 to 7.0, and is capable of selectively polishing a second layer with respect to a first layer: (A) colloidal silica particles having a negative ζ potential; (B) phosphoric acid or an organic phosphonic acid compound represented by the following Formula (1) or (2); and (C) an anionic surfactant having at least one group represented by the following Formulae (I) to (IV): | 10-06-2011 |
| 20110294293 | CHEMICAL PLANARIZATION OF COPPER WAFER POLISHING - Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarzing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer. | 12-01-2011 |
| 20110294294 | PROTECTIVE COATING FOR PLANARIZATION - Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane. | 12-01-2011 |
| 20110306210 | Method for cleaning substrates utilizing surface passivation and/or oxide layer growth to protect from pitting - A process/method for cleaning wafers that eliminates and/or reduces pitting caused by standard clean 1 by performing a pre-etch and then passivating the wafer surface prior to the application of the standard clean 1. The process/method may be especially useful for advanced front end of line post-CPM cleaning. In one embodiment, the invention is a method of processing a substrate comprising: a) providing at least one substrate; b) etching a surface of the substrate by applying an etching solution; c) passivating the etched surface of the substrate by applying ozone; and d) cleaning the passivated surface of the substrate by applying an aqueous solution comprising ammonium hydroxide and hydrogen peroxide. | 12-15-2011 |
| 20110312180 | POST CMP PLANARIZATION BY CLUSTER ION BEAM ETCH - The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies. | 12-22-2011 |
| 20110318927 | Multiple Patterning Lithography Using Spacer and Self-Aligned Assist Patterns - The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing. | 12-29-2011 |
| 20120015519 | DAMPING POLYURETHANE CMP PADS WITH MICROFILLERS - A system for preparing a microcellular polyurethane material, includes a froth, prepared, for instance, by inert gas frothing a urethane prepolymer, preferably an aliphatic isocyanate polyether prepolymer, in the presence of a surfactant; a filler soluble in a CMP slurry; and a curative, preferably including an aromatic diamine and a triol. To produce the microcellular material, the froth can be combined with the filler, e.g., PVP, followed by curing the resulting mixture. The microcellular material has a low rebound and can dissipate irregular energy and stabilize polishing to yield improved uniformity and less dishing. CMP pads using the microcellular material have pores created by inert gas frothing throughout the pad polymer body and additional surface pores created by dissolution of fillers during polishing, providing flexibility in surface softness and pad stiffness. | 01-19-2012 |
| 20120021604 | Controlling Defects in Thin Wafer Handling - A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed. | 01-26-2012 |
| 20120028466 | Method for Chemical Mechanical Planarization of a Tungsten-Containing Substrate - The titled method affords low dishing levels in the polished substrate while simultaneously affording high metal removal rates. The method utilizes an associated polishing composition. Components in the composition include a poly(alkyleneimine) such as polyethyleneimine, an abrasive, an acid, and an oxidizing agent, such as a per-compound. | 02-02-2012 |
| 20120034780 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and the large pattern. The oxide hard mask is then selectively removed. | 02-09-2012 |
| 20120040532 | PAD AND METHOD FOR CHEMICAL MECHANICAL POLISHING - A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer. | 02-16-2012 |
| 20120058641 | AQUEOUS POLISHING AGENT COMPRISING SOLID POLYMER PARTICLES AND TWO COMPLEXING AGENTS AND ITS USE IN A PROCESS FOR POLISHING PATTERNED AND UNSTRUCTURED METAL SURFACES - An aqueous CMP agent, comprising (A) solid polymer particles interacting and forming strong complexes with the metal of the surfaces to be polished; (B) a dissolved organic non-polymeric compound interacting and forming strong, water-soluble complexes with the metal and causing an increase of the material removal rate MRR and the static etch rate SER with increasing concentration of the compound (B); and (C) a dissolved organic non-polymeric compound interacting and forming slightly soluble or insoluble complexes with the metal, which complexes are capable of being adsorbed by the metal surfaces, and causing a lower increase of the MRR than the compound (B) and a lower increase of the SER than the compound (B) or no increase of the SER with increasing concentration of the compound (C); a CMP process comprising selecting the components (A) to (C) and the use of the CMP agent and process for polishing wafers with ICs. | 03-08-2012 |
| 20120064720 | PLANARIZATION CONTROL FOR SEMICONDUCTOR DEVICES - Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first material layer on the substrate. The method includes forming a second material layer over the first material layer. The second material layer is softer than the first material layer and has an exposed surface that is not in contact with the first material layer. The method includes flattening the second material layer without removing a portion of the second material layer. The flattening is carried out in a manner such that the exposed surface is substantially flat after the flattening. The method includes performing an etch back process to remove the second material layer and a portion of the first material layer. Wherein an etching selectivity of the etch back process with respect to the first and second material layers is approximately 1:1. | 03-15-2012 |
| 20120083121 | Fabrication of Replacement Metal Gate Devices - Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor. | 04-05-2012 |
| 20120088366 | CMP Retaining Ring with Soft Retaining Ring Insert - A wafer carrier adapted to further reduce the edge effect and allow a wafer to be uniformly polished across its entire surface, with a retaining ring made from very hard materials such as PEEK, PET or polycarbonate with a hardness in the range of 80 to 85 Shore D, while the inner surface or insert is made of polyurethane or other material with a hardness in the range of 85 to 95 Shore A. | 04-12-2012 |
| 20120094487 | COMPOSITIONS AND METHODS FOR MODIFYING A SURFACE SUITED FOR SEMICONDUCTOR FABRICATION - The method of the present invention comprises providing a wafer including a first, second and third material; contacting the third material in the presence of a working liquid with abrasive composites fixed to an abrasive article; and moving the wafer until an exposed surface of the wafer is substantially planar and comprises at least one area of exposed third material and one area of exposed second material. The components of the working liquid include an aqueous solvent; a pH buffer exhibiting a pK | 04-19-2012 |
| 20120094488 | CHEMICAL MECHANICAL POLISHING PROCESS - A chemical mechanical polishing process includes placing a substrate on a first polishing pad of a first platen, wherein the substrate has a bulk metal layer and a barrier layer; polishing the bulk metal layer by using the first polishing pad having a hardness of above 50 (Shore D) until the barrier layer is exposed; polishing the barrier layer on a second polishing pad of a second platen after removing the bulk metal layer, wherein the second polishing pad has a hardness ranging between 40 and 50 (Shore D) and includes an upper layer and a lower backing layer and the upper layer has a hardness less than 50 (Shore D). | 04-19-2012 |
| 20120094489 | CMP COMPOSITIONS AND METHODS FOR SUPPRESSING POLYSILICON REMOVAL RATES - The present invention provides a chemical-mechanical polishing (CMP) composition suitable for polishing a silicon nitride-containing substrate while suppressing polysilicon removal from the substrate. The composition comprises abrasive particles suspended in an acidic aqueous carrier containing a surfactant comprising an alkyne-diol, an alkyne diol ethoxylate, or a combination thereof. Methods of polishing a semiconductor substrate therewith are also disclosed. | 04-19-2012 |
| 20120108066 | PECVD SHOWERHEAD CONFIGURATION FOR CMP UNIFORMITY AND IMPROVED STRESS - A dielectric deposition tool for forming a silicon dioxide layer on a wafer with a TEOS showerhead which delivers a flow rate per unit area from an edge band of the showerhead that is at least twice a flow rate per unit area from a central region of the showerhead. The edge band extends at least one half inch from an outer edge of the showerhead up to one fourth of the diameter of the wafer. A process of forming an integrated circuit by forming a silicon dioxide layer on a wafer containing the integrated circuit using the dielectric deposition tool. The silicon dioxide layer is thicker under the edge band than under the central region. A subsequent CMP operation reduces the thickness difference between the wafer outer annulus and the wafer core by at least half. The silicon dioxide layer has a compressive stress between 125 and 225 MPa. | 05-03-2012 |
| 20120129345 | COMPOSITION AND METHOD FOR CLEANING SEMICONDUCTOR SUBSTRATES - The compositions and methods for the removal of residues and contaminants from metal or dielectric surfaces comprises at least one alkyl diphosphonic acid, at least one second acidic substance at amble ratio of about 1:1 to about 10:1 in water, arid pH is adjusted to from about 6 to about 10 with a metal ion free base, and a surfactant. Particularly, a composition and method of cleaning residues after chemical mechanical polishing of a copper or aluminum surface of the semiconductor substrates. | 05-24-2012 |
| 20120142190 | METHOD FOR MANUFACTURING THROUGH-SILICON VIA - A method for manufacturing TSVs comprises following steps: A stack structure having a substrate, an ILD layer and a dielectric stop layer is provided, in which an opening penetrating through the ILD layer and the dialectic stop layer and further extending into the substrate is formed. After an insulator layer and a metal barrier are formed on the stack structure, a top metal layer is formed on the stack structure to fulfill the opening. A first planarization process stopping on the metal barrier is conducted, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer. A second planarization process stopping on the dielectric stop layer is conducted, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric stop layer. The dielectric stop layer is than removed. | 06-07-2012 |
| 20120149197 | MANUFACTURING METHOD OF DEVICE AND PLANARIZATION PROCESS - A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed. | 06-14-2012 |
| 20120156878 | METHOD FOR PRODUCING EPITAXIAL SILICON WAFER - Mirror-polishing a front surface of a silicon wafer using polishing liquid composed of an abrasive grain-free alkaline solution including water-soluble polymers simplifies a polishing process, thus leading to an increase in productivity and a reduction in cost, and reduces the density of LPDs attributable to processing and occurring in the front surface of a mirror-polished wafer, thus improving the surface roughness of the wafer front surface. | 06-21-2012 |
| 20120178258 | METHOD OF PROCESSING A WAFER - According to embodiments of the present invention, a method of processing a wafer is provided. The wafer includes a plurality of through-wafer interconnects extending from a frontside surface of the wafer to a backside surface of the wafer. The method includes removing a part of wafer material of the back-side such that a portion of the wafer material between the through-wafer interconnects is removed, thereby exposing a portion of the through-wafer interconnects, forming a layer of low-k dielectric material between the through-wafer interconnects, and planarizing the layer of low-k dielectric material such that a surface of the portion of the through-wafer interconnect is exposed. | 07-12-2012 |
| 20120190198 | METHOD FOR IMPROVING FLATNESS OF A LAYER DEPOSITED ON POLYCRYSTALLINE LAYER - Described is a method for improving the flatness of a layer deposited on a doped polycrystalline layer, which includes reducing the grain size of the polycrystalline layer to decrease the out-diffusion amount of the dopant from the polycrystalline layer, and/or reducing the amount of the out-diffusing dopant on the surface of the polycrystalline layer. | 07-26-2012 |
| 20120190199 | SILICON POLISHING COMPOSITIONS WITH IMPROVED PSD PERFORMANCE - The invention relates to a chemical-mechanical polishing composition comprising silica, one or more tetraalkylammonium salts, one or more bicarbonate salts, one or more alkali metal hydroxides, one or more aminophosphonic acids, one or more rate accelerator compounds, one or more polysaccharides, and water. The polishing composition reduces surface roughness and PSD of polished substrates. The invention further relates to a method of chemically-mechanically polishing a substrate, especially a silicon substrate, using the polishing composition described herein. | 07-26-2012 |
| 20120190200 | Abrasive Free Silicon Chemical Mechanical Planarization - A chemical mechanical planarization method uses a chemical mechanical planarization composition that includes at least one nitrogen containing material and a pH modifying material, absent an abrasive material. The nitrogen containing material may be selected from a particular group of nitrogen containing polymers and corresponding nitrogen containing monomers. The chemical mechanical planarization method and the chemical mechanical planarization composition provide for planarizing a silicon material layer, such as but not limited to a poly-Si layer, in the presence of a silicon containing dielectric material layer, such as but not limited to a silicon oxide layer or a silicon nitride layer, with enhanced efficiency provided by an enhanced removal rate ratio. | 07-26-2012 |
| 20120202348 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device according to an embodiment, includes forming a plurality of films above a substrate in a same chamber without transferring the substrate out of the chamber, forming a target film to be polished above the plurality of films, and polishing the target film by a chemical mechanical polishing (CMP) technique using a film on a front side among the plurality of films as a polishing stopper. | 08-09-2012 |
| 20120214307 | CHEMICAL-MECHANICAL POLISHING LIQUID, AND SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD AND POLISHING METHOD USING SAID POLISHING LIQUID - The first embodiment of the CMP polishing liquid of the invention comprises cerium oxide particles, an organic compound with an acetylene bond, and water, the content of the organic compound with an acetylene bond being at least 0.00001 mass % and not greater than 0.01 mass % based on the total mass of the CMP polishing liquid. The second embodiment of the CMP polishing liquid of the invention comprises cerium oxide particles, an organic compound with an acetylene bond, an anionic polymer compound or salt thereof, and water, the anionic polymer compound being obtained by polymerizing a composition comprising a vinyl compound with an anionic substituent as a monomer component, the content of the organic compound with an acetylene bond being at least 0.000001 mass % and less than 0.05 mass % based on the total mass of the CMP polishing liquid. | 08-23-2012 |
| 20120220128 | METHOD FOR MANUFACTURING A TRANSISTOR - The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer. | 08-30-2012 |
| 20120225555 | Stable, concentratable chemical mechanical polishing composition and methods relating thereto - A chemical mechanical polishing composition useful for chemical mechanical polishing a semiconductor wafer containing an interconnect metal is provided, comprising, as initial components: water; an azole inhibitor; an alkali metal organic surfactant; a hydrotrope; a phosphorus containing agent; a water soluble cellulose; optionally, a non-saccharide water soluble polymer; optionally, a water soluble acid compound of formula I, wherein R is selected from a hydrogen and a C | 09-06-2012 |
| 20120231627 | PROCESS FOR REMOVING A BULK MATERIAL LAYER FROM A SUBSTRATE AND A CHEMICAL MECHANICAL POLISHING AGENT SUITABLE FOR THIS PROCESS - An aqueous chemical mechanical polishing (CMP) agent (A) comprising solid particles (a1) containing (a11) a corrosion inhibitor for metals, and (a12) a solid material, the said solid particles (a1) being finely dispersed in the aqueous phase; and its use in a process for removing a bulk material layer from the surface of a substrate and planarizing the exposed surface by chemical mechanical polishing until all material residuals are removed from the exposed surface, wherein the CMP agent exhibits at the end of the chemical mechanical polishing, without the addition of supplementary materials, —the same or essentially the same static etch rate (SER) as at its start and a lower material removal rate (MRR) than at its start, —a lower SER than at its start and the same or essentially the same MRR as at its start or—a lower SER and a lower MRR than at its start; such that the CMP agent exhibits a soft landing behavior. | 09-13-2012 |
| 20120244705 | POST-TUNGSTEN CMP CLEANING SOLUTION AND METHOD OF USING THE SAME - A post-W CMP cleaning solution consists of carboxylic acid and deionized water. The carboxylic acid may be selected from the group consisting of (1) monocarboxylic acids; (2) dicarboxylic acids; (3) tricarboxylic acids; (4) polycarboxylic acids; (5) hydroxycarboxylic acids; (6) salts of the above-described carboxylic acids; and (7) any combination thereof. The post-W CMP cleaning solution can work well without adding any other chemical additives such as surfactants, corrosion inhibitors, pH adjusting agents or chelating agents. | 09-27-2012 |
| 20120244706 | CHEMICAL MECHANICAL POLISHING METHOD - A chemical mechanical polishing method includes providing a device layer having a surface to be polished, polishing the surface using an alkaline grinding slurry, removing a residual layer that is been formed on the polished surface using an acid buffer, forming a passivation layer covering the polished surface of the device layer after the residual layer has been removed, and cleaning the passivation layer using deionized water. A semiconductor device thus fabricated has surfaces with excellent flatness, good manufacturing yield and long-term reliability. | 09-27-2012 |
| 20120258596 | Process of planarizing a wafer with a large step height and/or surface area features - A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer. | 10-11-2012 |
| 20120264299 | CHEMICAL MECHANICAL POLISHING METHOD - A chemical mechanical polishing (CMP) method is provided The method is capable of polishing a substrate in a CMP apparatus by using a hydrophobic polishing pad and includes following steps. A first CMP process is performed to the substrate. A first cleaning process is performed to the hydrophobic polishing pad. A second CMP process is performed to the substrate, wherein the first CMP process, the first cleaning process and the second CMP process are performed in sequence. | 10-18-2012 |
| 20120264300 | METHOD OF FABRICATING SEMICONDUCTOR COMPONENT - A method of fabricating the semiconductor component including following steps is provided. A substrate is provided, wherein an opening is already formed in the substrate. A material layer is formed on the substrate, wherein the material layer fills up the opening, and the material layer outside and above the opening has a recess therein. A sacrifice layer is formed on a surface of the recess. A chemical mechanical polishing (CMP) process is performed to remove the sacrifice layer and the material layer outside the opening, wherein a polishing rate of the CMP process on the material layer is greater than that of the CMP process on the sacrifice layer. | 10-18-2012 |
| 20120264301 | METHOD OF FORMING NON-PLANAR MEMBRANES USING CMP - A method of shaping a substrate in one embodiment includes providing a first support layer, providing a first shaping pattern on the first support layer, providing a substrate on the first shaping pattern, performing a first chemical mechanical polishing (CMP) process on the substrate positioned on the first shaping pattern, and removing the once polished substrate from the first shaping pattern. | 10-18-2012 |
| 20120270398 | PLANARIZATION METHOD FOR HIGH WAFER TOPOGRAPHY - A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed. | 10-25-2012 |
| 20120270399 | SLURRY COMPOSITION FOR CMP, AND POLISHING METHOD - The present invention relates to a CMP slurry composition comprising an abrasive particle; a dispersant; an ionic polymer additive; and a non-ionic polymer additive including a polyolefin-polyethylene glycol copolymer including at least two polyethylene glycol repeat unit as a backbone and at least a polyethylene glycol repeating unit as a side chain, and a polishing method with using the slurry composition. The CMP slurry composition shows a low polishing rate to a single-crystalline silicon layer or a polysilicon layer and a high polishing rate to a silicon oxide layer, resulting in having an excellent polishing selectivity. | 10-25-2012 |
| 20120270400 | SLURRY FOR CHEMICAL MECHANICAL POLISHING AND POLISHING METHOD FOR SUBSTRATE USING SAME - The present invention provides a slurry for chemical mechanical polishing comprising water-soluble clathrate compound (a), polymer compound (b) having an acidic group optionally in a salt form as a side chain, polishing abrasive grain (c) and water (d), wherein the content of the water-soluble clathrate compound (a) is 0.001 mass %-3 mass % of the total amount of the slurry, the polymer compound (b) has a weight average molecular weight of not less than 1,000 and less than 1,000,000, and the content of the polymer compound (b) is 0.12 mass %-3 mass % of the total amount of the slurry, and a polishing method for substrate using the slurry. | 10-25-2012 |
| 20120295442 | Chemical mechanical polishing pad having a low defect window - A chemical mechanical polishing pad having a polishing layer with an integral window and a polishing surface adapted for polishing a substrate selected from a magnetic substrate, an optical substrate and a semiconductor substrate, wherein the formulation of the integral window provides improved defectivity performance during polishing. Also provided is a method of polishing a substrate using the chemical mechanical polishing pad. | 11-22-2012 |
| 20120295443 | METHOD FOR RECLAIMING SEMICONDUCTOR WAFER AND POLISHING COMPOSITION - Provided is a polishing composition used for polishing a semiconductor wafer surface having a step in order to planarize the wafer surface and thereby reclaiming the semiconductor wafer. The polishing composition contains at least a step eliminating agent, which is adsorbed to the surface of the semiconductor wafer and acts to prevent etching of bottom portion of the step on the wafer surface during polishing. The step eliminating agent is, for example, a water-soluble polymer or a surfactant, and more specifically, a polyvinyl alcohol, a polyvinyl pyrrolidone, a polyethylene glycol, a cellulose, a carboxylic acid surfactant, a sulfonic acid surfactant, a phosphate ester surfactant, or an oxyalkylene polymer. | 11-22-2012 |
| 20120302063 | NON-POLISHED GLASS WAFER, THINNING SYSTEM AND METHOD FOR USING THE NON-POLISHED GLASS WAFER TO THIN A SEMICONDUCTOR WAFER - A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0. | 11-29-2012 |
| 20120302064 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE AND CHEMICAL MECHANICAL POLISHING APPARATUS - A method of fabricating a semiconductor device includes dressing a surface of a polishing pad with a conditioning disk held by an arm while rotating a platen that holds the polishing pad in a chemical mechanical polishing apparatus, wherein the dressing is performed by pressing the conditioning disk to the polishing pad, and rotating the arm around a rotational axis of the arm thereby to move the conditioning disk substantially along a radius direction of the platen between a center part and a circumferential part of the platen, and wherein torque N applied to the arm is measured at plural positions of the conditioning disk along the substantial radius direction during the dressing, and it is determined whether maintenance to the arm is necessary in accordance with an average value of the measured torques N and a fluctuation range Y of the measured torques N. | 11-29-2012 |
| 20120315762 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The present invention discloses a method for fabricating semiconductor devices. After removing excessive aluminium to form aluminium gates through a chemical mechanical planarization (CMP) process, the exposed surfaces of the aluminium gates are oxidized with H | 12-13-2012 |
| 20120322264 | AQUEOUS POLISHING AGENT AND GRAFT COPOLYMERS AND THEIR USE IN A PROCESS FOR POLISHING PATTERNED AND UNSTRUCTURED METAL SURFACES - An aqueous polishing agent, comprising, as the abrasive, at least one kind of polymer particles (A) finely dispersed in the aqueous phase and having at their surface a plurality of at least one kind of functional groups (al) capable of interacting with the metals and/or the metal oxides on top of the surfaces to be polished and forming complexes with the said metals and metal cations, the said polymer particles (A) being preparable by the emulsion or suspension polymerization of at least one monomer containing at least one radically polymerizable double bond in the presence of at least one oligomer or polymer containing a plurality of functional groups (a1); graft copolymers preparable by the emulsion or suspension polymerization of at least one monomer containing at least one radically polymerizable double bond in the presence of at least one oligomeric or polymeric aminotriazine-polyamine condensate; and a process for the chemical and mechanical polishing of patterned and unstructured metal surfaces making use of the said aqueous polishing agent. | 12-20-2012 |
| 20120329278 | DISPENSER FOR CHEMICAL-MECHANICAL POLISHING (CMP) APPARATUS, CMP APPARATUS HAVING THE DISPENSER, AND CMP PROCESS USING THE CMP APPARATUS - A dispenser for a chemical-mechanical polishing (CMP) apparatus, includes a delivery arm disposed over a polishing pad of a CMP apparatus, at least a slurry delivery groove formed in the delivery arm and extending along a length of the delivery arm, and a plurality of first openings connected to the slurry delivery groove. | 12-27-2012 |
| 20120329279 | CMP Slurry/Method for Polishing Ruthenium and Other Films - A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates. | 12-27-2012 |
| 20130005147 | METHOD OF REDUCING CRITICAL DIMENSION PROCESS BIAS DIFFERENCES BETWEEN NARROW AND WIDE DAMASCENE WIRES - A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench. | 01-03-2013 |
| 20130005148 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer. | 01-03-2013 |
| 20130045596 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND POLISHING APPARATUS - According to one embodiment, a semiconductor device manufacturing method is provided. In the semiconductor device manufacturing method, a process target film is formed on a semiconductor substrate, and the surface of the process target film is polished by a CMP method. The CMP method comprises heating a rotating polishing pad from a first temperature to a second temperature higher than the first temperature, and bringing the surface of the process target film into contact with the polishing pad heated to the second temperature. | 02-21-2013 |
| 20130045597 | LIQUID COMPOSITION FOR CLEANING SEMICONDUCTOR SUBSTRATE AND METHOD OF CLEANING SEMICONDUCTOR SUBSTRATE USING THE SAME - [Problems] An object of the present invention is to provide a cleaning liquid composition which removes residual liquid and contaminants after chemical-mechanical polishing (CMP) of the surface of a semiconductor substrate in the production process of a semiconductor circuit device; and a cleaning method using the cleaning liquid composition. | 02-21-2013 |
| 20130052825 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer. | 02-28-2013 |
| 20130078810 | METHOD AND APPARATUS FOR PERFORMING A POLISHING PROCESS IN SEMICONDUCTOR FABRICATION - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a polishing head that is operable to perform a polishing process to a wafer. The apparatus includes a retaining ring that is rotatably coupled to the polishing head. The retaining ring is operable to secure the wafer to be polished. The apparatus includes a soft material component located within the retaining ring. The soft material component is softer than silicon. The soft material component is operable to grind a bevel region of the wafer during the polishing process. The apparatus includes a spray nozzle that is rotatably coupled to the polishing head. The spray nozzle is operable to dispense a cleaning solution to the bevel region of the wafer during the polishing process. | 03-28-2013 |
| 20130078811 | SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF - A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad. | 03-28-2013 |
| 20130078812 | Wafer Carrier with Flexible Pressure Plate - A wafer carrier with a wafer mounting plate disposed under a plenum which can be pressurized and depressurized to alter the shape of the wafer mounting plate and a plenum, formed with the wafer mounting plate and the wafer itself, to which vacuum can be applied to hold the wafer to the wafer mounting plate during polishing | 03-28-2013 |
| 20130084702 | ACRYLATE POLYURETHANE CHEMICAL MECHANICAL POLISHING LAYER - A chemical mechanical polishing pad comprising an acrylate polyurethane polishing layer, wherein the polishing layer exhibits a tensile modulus of 65 to 500 MPa; an elongation to break of 50 to 250%; a storage modulus, G′, of 25 to 200 MPa; a Shore D hardness of 25 to 75; and a wet cut rate of 1 to 10 μm/min. | 04-04-2013 |
| 20130095660 | METHOD FOR POLISHING SILICON WAFER - To final polish a finish-polished surface using a final polishing solution whose chief component is a weakly basic aqueous solution that does not contain abrasive grains. During the final polishing, the weakly basic aqueous solution having an alkali concentration that reduces a haze value of a final-polished surface below the haze value of the finish-polished surface of the wafer is used as the chief component of the final polishing solution. | 04-18-2013 |
| 20130102152 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor manufacturing apparatus includes at least one inner retaining ring, and an outer retaining ring. The at least one inner retaining ring applies a first pressure to the polishing pad, and retains a substrate on the polishing pad. The outer retaining ring applies a second pressure to the polishing pad, and retains the at least one inner retaining ring on the polishing pad. Control of the first pressure is independent with respect to control of the second pressure. | 04-25-2013 |
| 20130102153 | METHOD AND COMPOSITION FOR CHEMICAL MECHANICAL PLANARIZATION OF A METAL OR A METAL ALLOY - A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low dishing and erosion levels during CMP processing. | 04-25-2013 |
| 20130102154 | METHODS AND SYSTEMS FOR REMOVING MATERIALS FROM MICROFEATURE WORKPIECES WITH ORGANIC AND/OR NON-AQUEOUS ELECTROLYTIC MEDIA - Methods and systems for removing materials from microfeature workpieces are disclosed. A method in accordance with one embodiment of the invention includes providing a microfeature workpiece having a substrate material and a conductive material that includes a refractory metal (e.g., tantalum, tantalum nitride, titanium, and/or titanium nitride). First and second electrodes are positioned in electrical communication with the conductive material via a generally organic and/or non-aqueous electrolytic medium. At least one of the electrodes is spaced apart from the workpiece. At least a portion of the conductive material is removed by passing an electrical current along an electrical path that includes the first electrode, the electrolytic medium, and the second electrode. Electrolytically removing the conductive material can reduce the downforce applied to the workpiece. | 04-25-2013 |
| 20130109180 | METHOD FOR POLISHING SILICON WAFER, AND POLISHING SOLUTION FOR USE IN THE METHOD | 05-02-2013 |
| 20130137263 | ELECTRICALLY ASSISTED CHEMICAL-MECHANICAL PLANARIZATION (EACMP) SYSTEM AND METHOD THEREOF - A novel polishing pad is described. The polishing pad includes a base plate, a main polishing body, a plurality of metal bottom portions, a positive electrode conductive wire and a negative electrode conductive wire. The main polishing body made from a non-conductive material and disposed on the base plate includes a plurality of cavities thereon. The metal bottom portions are disposed in the cavities with each of the cavities having one of the metal bottom portions therein. The positive electrode conductive wire electrically is connected to a positive electrode of a power supply. The negative electrode conductive wire electrically is connected to a negative electrode of the power supply. The positive electrode conductive wire and the negative electrode conductive wire alternatively pass through the base plate and connect to the metal bottom portions respectively. | 05-30-2013 |
| 20130137264 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer. | 05-30-2013 |
| 20130157464 | PLANARIZING METHOD - According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon. | 06-20-2013 |
| 20130171823 | CMP Slurry Composition and Polishing Method Using the Same - A CMP slurry composition includes metal oxide particles, a diisocyanate compound, and deionized water. The CMP slurry composition is capable of selectively controlling polishing speed of a wafer surface having a convex portion and a concave portion, such that primary polishing and secondary polishing can be performed rapidly while stopping polishing of the nitride layer upon the secondary polishing. | 07-04-2013 |
| 20130178064 | POLISHING SLURRY AND CHEMICAL MECHANICAL PLANARIZATION METHOD USING THE SAME - A polishing slurry for a chemical mechanical planarization process includes polishing particles and polyhedral nanoscale particles having a smaller size than the polishing particles and including a bond of silicon (Si) and oxygen (O). | 07-11-2013 |
| 20130183826 | COMPOSITION FOR POLISHING AND COMPOSITION FOR RINSING - A polishing composition for a silicon wafer and a rinsing composition for a silicon wafer according to the present invention contain a nonionic surfactant of a polyoxyethylene adduct. The HLB value of the polyoxyethylene adduct is 8 to 15. The weight-average molecular weight of the polyoxyethylene adduct is 1400 or less. The average number of moles of oxyethylene added in the polyoxyethylene adduct is 13 or less. The content of the polyoxyethylene adduct in each of the polishing composition and the rinsing composition is 0.00001 to 0.1% by mass. | 07-18-2013 |
| 20130189841 | ENGINEERING DIELECTRIC FILMS FOR CMP STOP - A method for forming an integrated circuit is provided. In one embodiment, the method includes forming a stop layer comprising carbon doped silicon nitride on a gate region on a substrate, the gate region having a poly gate and one or more spacers formed adjacent the poly gate, forming a dielectric layer on the stop layer, and removing a portion of the dielectric layer above the gate region using a CMP process, wherein the stop layer is a strain inducing layer having a CMP removal rate that is less than the CMP removal rate of the dielectric layer and equal to or less than the CMP removal rate of the one or more spacers. | 07-25-2013 |
| 20130189842 | CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION COMPRISING A SPECIFIC HETEROPOLYACID - A chemical mechanical polishing (CMP) composition comprising a specific heteropolyacid Abstract A chemical-mechanical polishing (CMP) composition comprising: (A) inorganic particles, organic particles, or a mixture thereof, (B) a heteropolyacid of the formula HaXbPsMOyVzOc wherein X=any cation other than H 80 and a>0 (formula I) or a salt thereof, and, (C) an aqueous medium. | 07-25-2013 |
| 20130203254 | POLISHING COMPOSITION AND POLISHING METHOD - A polishing composition contains a water-soluble polymer, a polishing accelerator, and an oxidizing agent. The water-soluble polymer is a polyamide-polyamine polymer having an amine value of 150 mg KOH/1 g·solid or greater. | 08-08-2013 |
| 20130244430 | Double Patterning Method for Semiconductor Devices - A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer. | 09-19-2013 |
| 20130252425 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate. | 09-26-2013 |
| 20130252426 | POLISHING AGENT AND METHOD FOR POLISHING SUBSTRATE USING THE POLISHING AGENT - Disclosed is a polishing agent comprising: water; tetravalent metal hydroxide particles; and an additive, wherein the additive contains at least one of a cationic polymer and a cationic polysaccharide. The present invention can provide a polishing agent which is capable of polishing an insulating film at a high speed with less polishing flaws, and having a high polishing rate ratio of a silicon oxide film and a stopper film, in the CMP technology of flattening insulating film. The present invention can also provide a polishing agent set for storing the polishing agent, and a method for polishing a substrate using this polishing agent. | 09-26-2013 |
| 20130273739 | AQUEOUS POLISHING COMPOSITION AND PROCESS FOR CHEMICALLY MECHANICALLY POLISHING SUBSTRATES HAVING PATTERNED OR UNPATTERNED LOW-K DIELECTRIC LAYERS - An aqueous polishing composition comprising (A) abrasive particles and (B) an amphiphilic nonionic surfactant selected from the group consisting of water-soluble or water-dispersible surfactants having (b1) hydrophobic groups selected from the group consisting of branched alkyl groups having 10 to 18 carbon atoms; and (b2) hydrophilic groups selected from the group consisting of polyoxyalkylene groups comprising (b21) oxyethylene monomer units and (b22) substituted oxyalkylene monomer units wherein the substituents are selected from the group consisting of alkyl, cycloalkyl, or aryl, alkyl-cycloalkyl, alkyl-aryl, cycloalkyl-aryl and alkyl-cycloalkyl-aryl groups, the said polyoxyalkylene group containing the monomer units (b21) and (b22) in random, alternating, gradient and/or blocklike distribution; a CMP process for substrates having patterned or unpatterned low-k or ultra-low-k dielectric layers making use of the said aqueous polishing composition; and the use of the said aqueous polishing composition for manufacturing electrical, mechanical and optical devices. | 10-17-2013 |
| 20130280909 | METAL CUT PROCESS FLOW - A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features. | 10-24-2013 |
| 20130295769 | METHODS OF PATTERNING SMALL VIA PITCH DIMENSIONS - Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask. | 11-07-2013 |
| 20130295770 | METHODS FOR INTEGRATED CIRCUIT FABRICATION WITH PROTECTIVE COATING FOR PLANARIZATION - Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane. | 11-07-2013 |
| 20130302984 | POLISHING COMPOSITION, POLISHING METHOD USING SAME, AND SUBSTRATE PRODUCTION METHOD - Provided is a polishing composition characterized by: including at least one of either organic acid or organic salt and including a composition (A) including hydroxyethyl cellulose, ammonia, abrasive grains, and water. The electrical conductivity of the polishing composition is 1.2 to 8 times the electrical conductivity of the composition (A). The polishing composition is mainly used in substrate surface polishing applications. | 11-14-2013 |
| 20140011360 | CHEMICAL MECHANICAL POLISHING AQUEOUS DISPERSION AND CHEMICAL MECHANICAL POLISHING METHOD FOR SEMICONDUCTOR DEVICE - A chemical mechanical polishing aqueous dispersion of the invention includes (A) a first water-soluble polymer having a weight average molecular weight of 500,000 to 2,000,000 and including a heterocyclic ring in its molecule, (B) a second water-soluble polymer or its salt having a weight average molecular weight of 1000 to 10,000 and including one group selected from a carboxyl group and a sulfonic group, (C) an oxidizing agent, and (D) abrasive grains, and has a pH of 7 to 12. | 01-09-2014 |
| 20140024216 | GST CMP SLURRIES - The present invention provides chemical-mechanical polishing (CMP) compositions suitable for polishing a substrate comprising a germanium-antimony-tellurium (GST) alloy. The CMP compositions of the present invention are aqueous slurries comprising a particulate abrasive, a water-soluble surface active agent, a complexing agent, and a corrosion inhibitor. The ionic character of the surface active material (e.g., cationic, anionic, or nonionic) is selected based on the zeta potential of the particulate abrasive. A CMP method for polishing a GST alloy-containing substrate utilizing the composition is also disclosed. | 01-23-2014 |
| 20140038413 | Method of Manufacturing a Semiconductor Device including a Dielectric Structure - A dielectric layer is deposited on a working surface of a substrate, wherein the dielectric layer contains or consists of a dielectric polymer. The dielectric layer is partially cured. A portion of the partially cured dielectric layer is removed using a chemical mechanical polishing process. Then the curing of remnant portions of the partially cured dielectric layer is continued to form a dielectric structure. The partially cured dielectric layer shows high removal rates during chemical mechanical polishing. With remnant portions of the dielectric layer provided in cavities, high volume insulating structures can be provided in an efficient manner. | 02-06-2014 |
| 20140038414 | Process of planarizing a wafer with a large step height and/or surface area features - A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer. | 02-06-2014 |
| 20140051249 | SUBSTRATE POLISHING APPARATUS - A substrate polishing apparatus includes a retainer for holding a substrate and substrate rotating device that spins the retainer around a first rotational axis perpendicular to a to-be-polished surface of the substrate. A platen includes an abrasive pad disposed opposite of the to-be-polished surface of the substrate. A platen rotating device spins the platen around a second rotational axis perpendicular to the abrasive pad. A liquid storage chamber includes a wall portion surrounding the outer periphery of the substrate. One end of the wall portion is positionable in a liquid-tight manner with the abrasive pad to define a liquid storage space for retaining a polishing liquid around the outer periphery of the substrate. | 02-20-2014 |
| 20140057438 | POLISHING METHOD OF NON-OXIDE SINGLE-CRYSTAL SUBSTRATE - There is provided a polishing method for polishing a non-oxide single-crystal substrate such as a silicon carbide single-crystal substrate at a high polishing rate to obtain a high-quality surface that is smooth and excellent in surface properties. This polishing method is a method of supplying a polishing liquid to a polishing pad not including abrasive grains to bring a surface to be polished of the non-oxide single-crystal substrate and the polishing pad into contact with each other and polishing the surface to be polished by a relative movement between them, the method characterized in that the polishing liquid comprises: an oxidant whose redox potential is 0.5 V or more and which contains a transition metal; and water, and does not contain abrasive grains. | 02-27-2014 |
| 20140065825 | POLISHING SLURRY FOR CMP AND POLISHING METHOD - A method including preparing a polishing slurry for CMP for polishing at least a conductor layer and a conductive substance layer in contact with the conductor layer, wherein the absolute value of the potential difference between the conductive substance and the conductor at 50±5° C. is 0.25 V or less in the polishing slurry when a positive electrode and a negative electrode of a potentiometer are connected to the conductive substance and the conductor, respectively. The polishing slurry for CMP preferably comprises at least one compound selected from heterocyclic compounds containing any one of hydroxyl group, carbonyl group, carboxyl group, amino group, amide group and sulfinyl group, and containing at least one of nitrogen and sulfur atoms. | 03-06-2014 |
| 20140073136 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device manufacturing method comprises forming an interlayer dielectric film on a semiconductor substrate, forming a film on the interlayer dielectric film to cover a recess and projection formed on a surface of the interlayer dielectric film, polishing the film by CMP to expose the interlayer dielectric film, and etching the film and the interlayer dielectric film such that etching rates of the film and the interlayer dielectric film are equal. | 03-13-2014 |
| 20140120724 | COMPOSITE CONDITIONER AND ASSOCIATED METHODS - CMP pad dressers having leveled tips and associated methods are provided. In one aspect, for example, a composite conditioner can include a base plate and a plurality of polishing units secured to a surface of the base plate by an adhesive layer, where each polishing unit includes a plurality of polishing tips secured in a binding layer. Additionally, a height difference between a first highest polishing tip and a second highest polishing tip is less than or equal to about 10 μm, a height difference between the first highest polishing tip and a tenth highest polishing tip is less than or equal to about 20 μm, and a height difference between the first highest polishing tip and a 100th highest polishing tip is less than or equal to about 40 μm. Furthermore, the first highest polishing tip protrudes from the binding layer to a height of greater than or equal to about 50 μm. | 05-01-2014 |
| 20140120725 | POLISHING APPARATUS AND POLISHING METHOD - A polishing apparatus is used for polishing a surface of a substrate such as a semiconductor wafer to planarize the surface of the substrate. The polishing apparatus includes a polishing table having a polishing surface, and a top ring configured to hold a substrate with an outer circumferential edge of the substrate surrounded by a retainer ring and to press the substrate against the polishing surface. The top ring is movable between a polishing position above the polishing table, a position laterally of the polishing table, and a cleaning position. The polishing apparatus includes a cleaning unit disposed in the cleaning position and configured to eject a cleaning liquid toward the lower surface of the top ring, which is being rotated, thereby cleaning the substrate held by the top ring together with the lower surface of the top ring. | 05-01-2014 |
| 20140141611 | Surface Treatment in the Formation of Interconnect Structure - A Ultra-Violet (UV) treatment is performed on an exposed surface of a low-k dielectric layer and an exposed surface of a metal line. After the UV treatment, an organo-metallic soak process is performed on the exposed surface of the low-k dielectric layer and the exposed surface of the metal line. The organo-metallic soak process is performed using a process gas including a metal bonded to an organic group. | 05-22-2014 |
| 20140148008 | MULTI-POINT CHEMICAL MECHANICAL POLISHING END POINT DETECTION SYSTEM AND METHOD OF USING - A wafer polishing system including a platen configured to rotate in a first direction, and a polishing head configured to hold a wafer, the polishing head configured to rotate in a second direction. The wafer polishing system further includes an optical sensing system configured to detect a thickness of the wafer at a first location on the platen and a second location on the platen. A first distance from a center of the platen to the first location is different than a second distance from the center of the platen to the second location. | 05-29-2014 |
| 20140162455 | METHOD OF FORMING A PLANAR SURFACE FOR A SEMICONDUCTOR DEVICE STRUCTURE, AND RELATED METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE - A method of forming a planar surface for a semiconductor device structure. The method comprises forming a particle film comprising a plurality of discrete particles on a non-planar surface of a semiconductor device structure. The semiconductor device structure is subjected to at least one chemical-mechanical polishing process after forming the particle film on the non-planar surface of the semiconductor device structure. Methods of forming a semiconductor device structure are also described. | 06-12-2014 |
| 20140170852 | PROCESS FOR THE MANUFACTURE OF SEMICONDUCTOR DEVICES COMPRISING THE CHEMICAL MECHANICAL POLISHING OF ELEMENTAL GERMANIUM AND/OR SI1-XGEX MATERIAL IN THE PRESENCE OF A CMP COMPOSITION COMPRISING A SPECIFIC ORGANIC COMPOUND - A process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental germanium and/or Si | 06-19-2014 |
| 20140187042 | METHOD FOR CHEMICAL PLANARIZATION AND CHEMICAL PLANARIZATION APPARATUS - According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions. | 07-03-2014 |
| 20140199840 | CHEMICAL MECHANICAL POLISHING APPARATUS AND METHODS - In one aspect, a substrate polishing apparatus is disclosed. The apparatus has a polishing platform having two or more zones, each zone adapted to contain a different slurry component. In another aspect, a substrate polishing system is provided having a holder to hold a substrate, a polishing platform having a polishing pad, and a distribution system adapted to dispense, in a timed sequence, at least two different slurry components selected from a group consisting of an oxidation slurry component, a material removal slurry component, and a corrosion inhibiting slurry component. Polishing methods and systems adapted to polish substrates are provided, as are numerous other aspects. | 07-17-2014 |
| 20140213056 | APPARATUS, METHOD, AND COMPOSITION FOR FAR EDGE WAFER CLEANING - A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct cleaning fluids toward a far edge of the wafer after the CMP of the wafer. A wafer cleaning method includes CMP of a wafer by a polishing unit and directing cleaning fluids toward a far edge of the wafer after the CMP of the wafer by a cleaning dispensing unit. Another method can include CMP, applying deionized water, and applying pH adjuster having a pH range from about 2 to about 13. | 07-31-2014 |
| 20140220778 | PLANARIZATION METHOD AND PLANARIZATION APPARATUS - According to one embodiment, a planarization method and a planarization apparatus are provided. In the planarization method, a work surface of a work piece is planarized by bringing the work surface of the work piece containing a silicon oxide film and a surface of a solid plate onto which hydrogen ions are adsorbed, into contact or extremely close proximity with one another in a state in which a process liquid containing fluorine ions is supplied to the surface of the solid plate. | 08-07-2014 |
| 20140242797 | SEMICONDUCTOR FABRICATION METHOD USING STOP LAYER - A method of making a semiconductor assembly including the steps of: (i) providing an initial-state assembly including: (a) a fin layer, and (b) a hard mask layer located on top of at least a portion of the fin layer; (ii) performing a first material removal on the initial-state assembly, by CMP, to yield a second-state assembly; and (iii) performing a second material removal on the second-state assembly to yield a third-state assembly. In the first material-removal step: (i) any remaining portion of the soft sacrificial layer is removed, (ii) a portion of the fin layer is removed, and (iii) the lower portion of the hard mask layer is used as a stop layer for the second material removal. | 08-28-2014 |
| 20140248775 | CLEANING AGENT AND METHOD FOR PRODUCING SILICON CARBIDE SINGLE-CRYSTAL SUBSTRATE - The present invention provides a detergent for effectively cleaning, by a safe and simple method, a manganese component remaining on and adhered to a substrate surface, after polishing a silicon carbide single crystal substrate with a manganese compound-containing polishing agent. The present invention relates to a detergent for cleaning a silicon carbide single crystal substrate polished with a manganese compound-containing polishing agent, the detergent including at least one of ascorbic acid and erythorbic acid, in which the detergent has a pH of 6 or less. | 09-04-2014 |
| 20140273455 | HARD MASK REMOVAL DURING FINFET FORMATION - An approach for polishing-based hard mask removal during FinFET device formation is provided. In a typical embodiment, an initial device will be provided with a set of fins (e.g., silicon (Si)), a set of fin caps (e.g., silicon nitride (SiN)), and an oxide layer. A post-oxide planarizing and thinning polishing will first be performed (e.g., using a Silica-based slurry) to thin/reduce the oxide layer. A stop-on-nitride polishing will then be performed (e.g., using a Ceria-based slurry) to reduce the oxide layer to a top surface of the fin caps. Still yet, a stop-on-silicon polishing will be performed (e.g., using a Ceria-based slurry) to remove the set of fin caps and to reduce the oxide layer to a top surface to the set of fins. | 09-18-2014 |
| 20140273456 | Method for Integrated Circuit Patterning - A method of forming a target pattern includes forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction; forming a spacer around the mandrel pattern, the spacer having a first width; forming a cut pattern over the mandrel pattern and the spacer wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction; etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacer, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern; and reducing the first width of the spacer thereby to enlarge the plurality of openings. | 09-18-2014 |
| 20140273457 | Anti-Reflective Layer and Method - A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom. | 09-18-2014 |
| 20140273458 | Chemical Mechanical Planarization for Tungsten-Containing Substrates - Chemical mechanical polishing (CMP) compositions for polishing tungsten or tungsten-containing substrates comprise an abrasive, at least one solid catalyst, a chemical additive selected from the groups consisting of piperazine derivatives, salts of cyanate, and combinations thereof; and a liquid carrier. Systems and processes use the aqueous formulations for polishing tungsten or tungsten-containing substrates. | 09-18-2014 |
| 20140287586 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of a semiconductor device comprises forming a to-be-processed film includes a convex potion and concave potion on its surface on a semiconductor substrate via layers having a relative dielectric constant smaller than that of SiO | 09-25-2014 |
| 20140302675 | Nanogap in-between noble metals - A nanogap of controlled width in-between noble metals is produced using sidewall techniques and chemical-mechanical-polishing. Electrical connections are provided to enable current measurements across the nanogap for analytical purposes. The nanogap in-between noble metals may also be formed inside a Damascene trench. The nanogap in-between noble metals may also be inserted into a crossed slit nanopore framework. A noble metal layer on the side of the nanogap may have sub-layers serving the purpose of multiple simultaneous electrical measurements. | 10-09-2014 |
| 20140302676 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, SUBSTRATE HOLDING MECHANISM, AND SUBSTRATE HOLDING METHOD - An apparatus for processing a substrate is disclosed. The apparatus includes a polishing section configured to polish a substrate, a transfer mechanism configured to transfer the substrate, and a cleaning section configured to clean and dry the polished substrate. The cleaning section has plural cleaning lines for cleaning plural substrates. The plural cleaning lines have plural cleaning modules and plural transfer robots for transferring the substrates. | 10-09-2014 |
| 20140308813 | METHODS AND APPARATUS FOR A NON-CONTACT EDGE POLISHING MODULE USING ION MILLING - Systems, methods and apparatus for polishing a substrate edge without mechanical contact are disclosed. The apparatus includes a rotatable chuck configured to secure a substrate, an ion milling machine configured to project an ion beam on an edge of the substrate and to sputter off matter from the substrate, and an endpoint detection sensor configured to determine if a material removal endpoint of the substrate has been reached. Numerous additional features are disclosed. | 10-16-2014 |
| 20140315385 | METHOD OF FORMING A DIELECTRIC FILM - A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film. | 10-23-2014 |
| 20140322913 | POLISHING COMPOSITION - A polishing composition of the present invention is to be used for polishing an object including a portion containing a high-mobility material and a portion containing a silicon material. The polishing composition comprises an oxidizing agent and abrasive grains having an average primary particle diameter of 40 nm or less. The polishing composition preferably further contains a hydrolysis-suppressing compound that bonds to a surface OH group of the portion containing a silicon material of the object to function to suppress hydrolysis of the portion containing a silicon material. Alternatively, a polishing composition of the present invention contains abrasive grains, an oxidizing agent, and a hydrolysis-suppressing compound. The polishing composition preferably has a neutral pH. | 10-30-2014 |
| 20140342559 | METHOD OF FORMING A SPACER PATTERNING MASK - The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask. | 11-20-2014 |
| 20140342560 | POLISHING COMPOSITION - A polishing composition of the present invention is to be used for polishing an object including a portion containing a group III-V compound material. The polishing composition contains an oxidizing agent and an anticorrosive agent. The anticorrosive agent is preferably a nitrogen-containing organic compound, such as 1H-1,2,4-triazole and benzotriazole, or an organic compound having a carboxyl group, for example, dicarboxylic acid, such as malonic acid, succinic acid, glutaric acid, adipic acid, pimelic acid, maleic acid, phthalic acid, malic acid, and tartaric acid, or tricarboxylic acid, such as citric acid. | 11-20-2014 |
| 20140377953 | METHOD AND APPARATUS FOR SIMULTANEOUSLY REMOVING MULTIPLE CONDUCTIVE MATERIALS FROM MICROELECTRONIC SUBSTRATES - A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated. | 12-25-2014 |
| 20150037978 | HARD MASK REMOVAL METHOD - A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP. | 02-05-2015 |
| 20150050809 | CMP Slurry/Method for Polishing Ruthenium and Other Films - A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates. | 02-19-2015 |
| 20150064903 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL PLANARIZATION TO RECESS METAL - Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench. | 03-05-2015 |
| 20150093899 | Semiconductor Device Manufacturing Methods - Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method. | 04-02-2015 |
| 20150111382 | POLISHING COMPOSITION TO BE USED TO POLISH SEMICONDUCTOR SUBSTRATE HAVING SILICON THROUGH ELECTRODE STRUCTURE, AND POLISHING METHOD USING POLISHING COMPOSITION - Provided is a polishing composition used for polishing a semiconductor substrate having a through-silicon via structure, comprising an oxidizing agent having a standard electrode potential of 350 mV or more and 740 mV or less, a silicon polishing accelerating agent, a through-silicon via material polishing speed increasing agent, a silicon contamination preventing agent, and water. | 04-23-2015 |
| 20150132953 | Etching of semiconductor structures that include titanium-based layers - Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH | 05-14-2015 |
| 20150132954 | METHOD FOR PROCESSING STRUCTURE IN MANUFACTURING SEMICONDUCTOR DEVICE - A method used for processing a structure in manufacturing of a semiconductor device may include polishing the structure to form a polished structure. The polished structure may include a metal member, a dielectric layer that contacts the metal member, and a particle that contacts at least one of the metal member and the dielectric layer. The method may further include applying an organic acid to the polished structure to remove at least a portion of the particle. The particle may be substantially removed, such that satisfactory quality of the semiconductor may be provided. | 05-14-2015 |
| 20150132955 | POLISHING COMPOSITION, POLISHING METHOD USING SAME, AND METHOD FOR PRODUCING SUBSTRATE - A polishing composition of the present invention contains a water-soluble polymer and abrasive grains. The water-soluble polymer is an anionic compound having an acid dissociation constant pKa of 3 or less. Specific examples of such a compound include polyvinylsulfonic acid, polystyrenesulfonic acid, polyallylsulfonic acid, polyethyl acrylate sulfonic acid, polybutyl acrylate sulfonic acid, poly(2-acrylamide-2-methylpropanesulfonic acid), and polyisoprenesulfonic acid. The abrasive grains exhibit a negative zeta potential at a pH of 3.5 or less. Specific examples of such abrasive grains include colloidal silica. | 05-14-2015 |
| 20150140818 | METHODS AND SYSTEMS FOR CHEMICAL MECHANICAL POLISH CLEANING - The present disclosure provides a cleaning unit for a chemical mechanical polishing (CMP) process. The cleaning unit comprises a cleaning solution; a brush configured to scrub a wafer during the CMP process; and a spray nozzle configured to apply the cleaning solution to the wafer when the brush scrubs the wafer during the CMP process. In some embodiments, the spray nozzle includes an inlet where the cleaning solution enters the spray nozzle and an outlet where the cleaning solution exits the spray nozzle. In some embodiments, an inlet area (A | 05-21-2015 |
| 20150140819 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having trenches with different sizes is provided. A first oxide layer is formed to entirely cover the substrate. A prevention layer is formed on the first oxide layer. A first filling layer is formed on the prevention layer and fills the trenches until the first filling layer is higher than the substrate. A first polishing process is performed to polish the first filling layer until exposing the prevention layer. A second polishing process is performed to polish the first filling layer, the prevention layer and the first oxide layer until the substrate is exposed. | 05-21-2015 |
| 20150140820 | CLEANING AGENT FOR SEMICONDUCTOR SUBSTRATES AND METHOD FOR PROCESSING SEMICONDUCTOR SUBSTRATE SURFACE - A cleaning agent is provided for a semiconductor substrate superior in corrosion resistance of a tungsten wiring or a tungsten alloy wiring, and superior in removal property of polishing fines (particle) such as silica or alumina, remaining at surface of the semiconductor substrate, in particular, at surface of a silicon oxide film such as a TEOS film, after a chemical mechanical polishing process; and a method for processing a semiconductor substrate surface. A cleaning agent for a semiconductor substrate is to be used in a post process of a chemical mechanical polishing process of the semiconductor substrate having a tungsten wiring or a tungsten alloy wiring, and a silicon oxide film, comprising (A) a phosphonic acid-based chelating agent, (B) a primary or secondary monoamine having at least one alkyl group or hydroxyalkyl group in a molecule and (C) water, wherein a pH is over 6 and below 7. | 05-21-2015 |
| 20150147883 | Post-CMP Cleaning and Apparatus for Performing the Same - A method of performing a post Chemical Mechanical Polish (CMP) cleaning includes picking up the wafer, spinning a cleaning solution contained in a cleaning tank, and submerging the wafer into the cleaning solution, with the cleaning solution being spun when the wafer is in the cleaning solution. After the submerging the wafer into the cleaning solution, the wafer is retrieved out of the cleaning solution. | 05-28-2015 |
| 20150298285 | MULTILAYER POLISHING PAD - A multilayer polishing pad includes a cushion layer, an adhesive member, and a polishing layer placed on the cushion layer with the adhesive member interposed therebetween, wherein the adhesive member is an adhesive layer containing a polyester-based hot-melt adhesive or a double-sided tape including a base layer and the adhesive layer provided on each of both sides of the base layer, wherein the adhesive layer or the double-sided tape has a non-adhesive region that occupies 1 to 40% of the surface area, and the polyester-based hot-melt adhesive contains 100 parts by weight of a polyester resin as a base polymer and 2 to 10 parts by weight of an epoxy resin having two or more glycidyl groups per molecule. | 10-22-2015 |
| 20150303050 | METHOD FOR PRODUCING SiC SUBSTRATE - A method of manufacturing a SiC substrate of the invention includes at least an oxide film-forming process of forming an oxide film ( | 10-22-2015 |
| 20150311088 | DIE LEVEL CHEMICAL MECHANICAL POLISHING - A method of polishing a wafer at the die level with a targeted slurry delivery system. The wafer is placed on a wafer carrier exposing the top side of the wafer, the wafer contains a die. The polishing apparatus will polish a portion of the die using a pad that is smaller than the die and the pad is located above the die. A slurry is applied to a portion of the die being polished. Embodiments of the invention provide multiple pads working on the same die. | 10-29-2015 |
| 20150311097 | POLISHING APPARATUS AND POLISHING METHOD - A polishing apparatus capable of performing multi-stage polishing of a substrate, such as wafer, is disclosed. The polishing apparatus includes: a plurality of polishing tables each for supporting a polishing pad; a plurality of polishing heads each configured to press a substrate against the polishing pad; and a transporting device configured to transport the substrate to at least two of the plurality of polishing heads. The plurality of polishing heads have different structures. | 10-29-2015 |
| 20150325450 | REWORK AND STRIPPING OF COMPLEX PATTERNING LAYERS USING CHEMICAL MECHANICAL POLISHING - A method utilizing a chemical mechanical polishing process to remove a patterned material stack comprising at least one pattern transfer layer and a template layer during a rework process or during a post pattern transfer cleaning process is provided. The pattern in the patterned material stack is formed by pattern transfer of a directed self-assembly pattern generated from microphase separation of a self-assembly material. | 11-12-2015 |
| 20150325451 | MULTI-LAYER POLISHING PAD FOR CMP - The invention is directed to a multi-layer polishing pad for chemical-mechanical polishing comprising a top layer, a middle layer and a bottom layer, wherein the top layer and bottom layer are joined together by the middle layer, and without the use of an adhesive. The invention is also directed to a multi-layer polishing pad comprising an optically transmissive region, wherein the layers of the multi-layer polishing pad are joined together without the use of an adhesive. | 11-12-2015 |
| 20150332922 | Semiconductor Integrated Circuit Fabrication With Pattern-Reversing Process - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer. | 11-19-2015 |
| 20150336234 | METHOD FOR PRODUCING LAYERED POLISHING PADS - The present invention relates to a method for producing a layered circular polishing pad, comprising steps of forming, in a circular polishing sheet, concentric grooves and an outer circumferential region having a width of ½ or more of a groove pitch of the concentric grooves; and bonding the circular polishing sheet and a supporting layer to each other with a bonding member interposed therebetween to produce a layered polishing sheet. According to the present invention, it is possible to provide a method for producing a layered circular polishing pad in which the polishing layer and the supporting layer are not easily peeled from each other. | 11-26-2015 |
| 20150336236 | CONDITIONING OF GROOVING IN POLISHING PADS - Among other things, a method comprises polishing a surface of a substrate by applying a pressure between the surface of a substrate and a surface of a polishing pad. The surface of the polishing pad defines one or more grooves separated by one or more partition regions. The one or more grooves have an initial depth before the polishing starts and extend from an initial outer surface of the one or more partition regions to an initial bottom of the one or more grooves. The method also comprises removing material below an initial bottom of the one or more grooves such that a distance between an outer surface of the one or more partition regions and a bottom of the one or more grooves remain substantially the same as the initial depth. | 11-26-2015 |
| 20150340222 | METHOD OF FLATTENING A WAFER - The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region. | 11-26-2015 |
| 20150343596 | CIRCULAR POLISHING PAD - A circular polishing pad includes a circular polishing layer having XY grid grooves on a polishing surface. The center point of the circular polishing layer is offset in a region (Z) (including imaginary straight lines) enclosed by three imaginary straight lines (A, B, and C) each shifted by a groove pitch of 5% in relation to reference lines defined by an X groove or a Y groove. The circular polishing pad can minimize polishing unevenness on the surface of a material to be polished. | 12-03-2015 |
| 20150344738 | POLISHING COMPOSITION - [Problem] Provided is a polishing composition which is suitable for polishing a polishing object having a metal wiring layer and capable of diminishing the step defect while maintaining a high polishing rate. | 12-03-2015 |
| 20150348797 | Apparatus and Method for Chemical Mechanical Polishing Process Control - An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes. | 12-03-2015 |
| 20150357180 | METHODS FOR CLEANING SEMICONDUCTOR SUBSTRATES - Methods for cleaning semiconductor substrates with cleaning baths including ammonium hydroxide, hydrogen peroxide and a non-ionic surfactant are disclosed. The methods may result in reduced re-adhesion of released particles during cleaning which produces cleaner substrates. | 12-10-2015 |
| 20150357186 | Wafer Back Side Processing Structure and Apparatus - Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms. | 12-10-2015 |
| 20150357199 | CHEMICAL MECHANICAL POLISHING METHOD AND APPARATUS - Methods for polishing a semiconductor wafer using a pad resurfacing arm and an apparatus therefor are disclosed. Embodiments may include providing a semiconductor wafer on a chemical mechanical polishing (CMP) tool, the CMP tool including a polish pad and a pad resurfacing arm which includes a pad cleaning part, a pad conditioning part, and a slurry dispensing part, dispensing a slurry to the polish pad utilizing the pad resurfacing arm, and polishing the semiconductor wafer utilizing the polish pad. | 12-10-2015 |
| 20150360341 | POLISHING PAD - A polishing pad has a polishing layer that is formed of a polyurethane foam having fine cells. The polyurethane foam is a reaction cured body of a chain extender and an isocyanate-terminated prepolymer which is obtained by reacting a prepolymer starting material composition that contains an isocyanate component, a high molecular weight polyol and an aliphatic diol. The high molecular weight polyol contains a polyalkylene glycol A that has a peak of the molecular weight distribution within the range of 200 to 300 and a polyalkylene glycol B that has a peak of the molecular weight distribution within the range of 800 to 1200. | 12-17-2015 |
| 20150360342 | POLISHING PAD - A polishing pad includes a polishing layer, and the polishing layer is formed of a reaction cured body of a polyurethane-forming raw material composition that contains: an isocyanate-terminated prepolymer (A) which is obtained by reacting a prepolymer-forming raw material composition (a) that contains an isocyanate component and a polyester polyol; an isocyanate-terminated prepolymer (B) which is obtained by reacting a prepolymer-forming raw material composition (b) that contains an isocyanate component and a polyether polyol; and a chain extender. The polyether polyol contains a polyether polyol (C) that has a number average molecular weight of 1000 or less and a polyether polyol (D) that has a number average molecular weight of 1900 or more. The reaction cured body has a triple phase separation structure. | 12-17-2015 |
| 20150361303 | POLISHING AGENT AND METHOD FOR POLISHING SUBSTRATE USING THE POLISHING AGENT - Disclosed is a polishing agent comprising: water; tetravalent metal hydroxide particles; and an additive, wherein the additive contains at least one of a cationic polymer and a cationic polysaccharide. The present invention can provide a polishing agent which is capable of polishing an insulating film at a high speed with less polishing flaws, and having a high polishing rate ratio of a silicon oxide film and a stopper film, in the CMP technology of flattening insulating film. The present invention can also provide a polishing agent set for storing the polishing agent, and a method for polishing a substrate using this polishing agent. | 12-17-2015 |
| 20150364336 | UNIFORM GATE HEIGHT FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing. | 12-17-2015 |
| 20160009955 | CHEMICAL-MECHANICAL POLISHING COMPOSITIONS COMPRISING N,N,N',N'-TETRAKIS-(2-HYDROXYPROPYL)-ETHYLENEDIAMINE OR METHANESULFONIC ACID | 01-14-2016 |
| 20160016280 | ORBITAL POLISHING WITH SMALL PAD - A chemical mechanical polishing apparatus includes a plate on which a substrate is received, and a movable polishing pad support and coupled polishing pad which move across the substrate and orbit a local region of the substrate during polishing operation. The load of the pad against the substrate, the revolution rate of the pad, and the size, shape, and composition of the pad, may be varied to control the rate of material removed by the pad. | 01-21-2016 |
| 20160020098 | LITHOGRAPHY USING INTERFACE REACTION - A method of forming a semiconductor structure by; forming a first mask trench in a first mask, where the first mask is on a substrate; forming a second mask in the first mask trench; and forming a third mask between the first mask and the second mask by reacting the first mask with the second mask, where the first mask, the second mask, and the third mask all have different etching properties. | 01-21-2016 |
| 20160023324 | METHOD OF AND APPARATUS FOR CMP PAD CONDITIONING - A chemical mechanical polishing (CMP) apparatus is provided that includes a conditioning disc for conditioning a polishing pad of the CMP apparatus. The conditioning disc includes a plurality of portions of subsystem discs. The portions may be regions of the disc that are concentric. Each portion of the disc is operable to rotate at a different angular velocity. In some embodiments, a different applied loading is provided to each of the portions of the disc in addition to or in lieu of the different angular velocities. | 01-28-2016 |
| 20160024351 | POLISHING AGENT, POLISHING METHOD AND ADDITIVE LIQUID FOR POLISHING - A polishing agent includes a particle of a metal oxide, a water-soluble polyamide, an organic acid and water. The water-soluble polyamide has a tertiary amino group and/or an oxyalkylene chain in a molecule thereof. The polishing agent has a pH of 7 or less. | 01-28-2016 |
| 20160027668 | CHEMICAL MECHANICAL POLISHING APPARATUS AND METHODS - Embodiments of the invention provide a non-uniform substrate polishing apparatus that includes a polishing pad with two or more zones, each zone adapted to apply a different slurry chemistry to a different area on a substrate to create a film thickness profile on the substrate having at least two different film thicknesses. Polishing methods and systems adapted to polish substrates are also provided, as are numerous other aspects. | 01-28-2016 |
| 20160053136 | REDUCTION IN LARGE PARTICLE COUNTS IN POLISHING SLURRIES - The present disclosure provides a method for reducing large particle counts (LPCs) in copper chemical mechanical polishing slurry by way of using high purity removal rate enhancer (RRE) in the slurry. The conductivity of the RRE in deionized water solutions correlates very strongly with the number of LPCs in the RRE, and thus in a slurry using the RRE. | 02-25-2016 |
| 20160056263 | METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE - A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure. | 02-25-2016 |
| 20160064243 | CHEMICAL PLANARIZATION METHOD AND APPARATUS - A chemical planarization method according to an embodiment includes a step of forming a hydrophobic protective film on a film to be processed with surface asperity. A dissolving solution for dissolving the film to be processed is supplied to the surface of the protective film. A processing body with a hydrophobic surface is brought into contact with or brought closed to the protective film, and a portion of the protective film is selectively removed by hydrophobic interaction from the film to be processed. The film to be processed is dissolved by the dissolving solution after the portion of the protective film is removed. | 03-03-2016 |
| 20160074989 | POLISHING APPARATUS AND POLISHING METHOD - A polishing apparatus capable of eliminating a variation in film thickness along a circumferential direction of a substrate, such as a wafer, is disclosed. The polishing apparatus includes: a polishing head including an elastic membrane for pressing the substrate against the polishing surface and a retainer ring arranged so as to surround the substrate, the retainer ring being capable of contacting the polishing surface; a rotating mechanism configured to rotate the polishing head about its own axis; a rotation angle detector configured to detect a rotation angle of the polishing head; and a polishing controller configured to periodically change a polishing condition of the substrate in synchronization with the rotation angle of the polishing head. | 03-17-2016 |
| 20160093663 | PREPARATION PROCESS OF IMAGE SENSORS - The invention relates to the field of semiconductor, more particularly, to a preparation process of image sensors, comprising: Step S | 03-31-2016 |
| 20160099156 | SUBSTRATE PROCESSING APPARATUS AND PROCESSING METHOD - A polishing apparatus is provided. The polishing apparatus includes: a polishing unit configured to polish a substrate by bringing a polishing tool into contact with the substrate and moving the substrate relatively to the polishing tool; a cleaning unit; and a first transfer robot configured to transfer the substrate before polishing to the polishing unit and/or configured to transfer the substrate after polishing from the polishing unit to the cleaning unit. The cleaning unit includes: at least one cleaning module, a buff processing module configured to perform a buff process to the substrate, and a second transfer robot configured to transfer the substrate between the cleaning module and the buff processing module, the second transfer robot being different from the first robot. | 04-07-2016 |
| 20160099157 | BARC-ASSISTED PROCESS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS - The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate. The topographically variable surface varies in height across the semiconductor substrate. A polymeric bottom anti-reflective coating (BARC) is provided over the topographically variable surface. Chemical mechanical polishing is performed to remove a first portion of the BARC, and etching effectuates a top-down recessing of the BARC. | 04-07-2016 |
| 20160104629 | APPARATUS AND A METHOD FOR TREATING A SUBSTRATE - A substrate treating method may include jetting a fluid containing an abrasive onto a substrate, and polishing the substrate using the jetted fluid. | 04-14-2016 |
| 20160111297 | ITERATIVE SELF-ALIGNED PATTERNING - A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers. | 04-21-2016 |
| 20160114457 | UNIFORM POLISHING WITH FIXED ABRASIVE PAD - A polishing pad for use in chemical mechanical polishing of a substrate is disclosed. The polishing pad includes first and second major surfaces. The first major surface forms a polishing surface and is divided into a main portion and edge portions. The edge portions are nearer to edges of the polishing pad while the main portion is between the edge portions and farther from the edges of the polishing pad. The polishing pad also includes a plurality of polishing posts disposed on the first major surface of the pad. The densities of the polishing posts in the edge portions and main portion are different. | 04-28-2016 |
| 20160163600 | SELF-ALIGNED QUADRUPLE PATTERNING PROCESS - Methods for modifying a spacer and/or spaces between spacers to enable a fin cut mask to be dropped between the spacers are provided. A first set of second mandrel structures having a first width is formed on facing sidewall surfaces of a neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width less than the first width are formed on non-facing sidewall surfaces of the neighboring pair of first mandrel structures. Each first mandrel structure is removed and a spacer is formed on a sidewall surface of the first and second sets of second mandrel structures. In the region between the neighboring pair of first mandrel structure, a merged spacer is formed. The first and second sets of second mandrel structures are removed. A portion of an underlying substrate can be patterned utilizing each spacer and the merged spacer as etch masks. | 06-09-2016 |
| 20160172209 | CMP-FRIENDLY COATINGS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS | 06-16-2016 |
| 20160189973 | METHOD FOR PRODUCING POLISHED OBJECT AND POLISHING COMPOSITION KIT - [Problem] To provide a method for producing a polished object, which can remarkably reduce a haze level on a surface of the object to be polished while defects are significantly reduced. | 06-30-2016 |
| 20160189998 | WAFER TEMPORARY BONDING METHOD AND THIN WAFER MANUFACTURING METHOD - A method for temporarily bonding a wafer to a support via a temporary bonding arrangement is provided. The arrangement is a composite temporary adhesive layer consisting of a non-silicone thermoplastic resin layer (A) which is releasably bonded to the wafer, a thermosetting siloxane polymer layer (B) laid thereon, and a thermosetting siloxane-modified polymer layer (C) releasably bonded to the support. The method comprises the steps of providing a wafer laminate having a thermosetting silicone composition layer (B′) formed on the resin layer (A) which has been formed on the wafer, providing a support laminate having a siloxane-containing composition layer (C′) formed on the support, joining and heating layer (B′) and layer (C′) in vacuum for bonding and curing the layers together. | 06-30-2016 |
| 20160203993 | Pitch Reduction Technology Using Alternating Spacer Depositions During the Formation of a Semiconductor Device and Systems Including Same | 07-14-2016 |
| 20160203994 | POLISHING COMPOSITION | 07-14-2016 |
| 20160375545 | CHEMICAL MECHANICAL POLISHING PAD COMPOSITE POLISHING LAYER FORMULATION - A chemical mechanical polishing pad is provided containing: a polishing layer having a polishing surface; wherein the polishing layer comprises a first continuous non-fugitive polymeric phase and a second non-fugitive polymeric phase; wherein the first continuous non-fugitive polymeric phase has a plurality of periodic recesses; wherein the plurality of periodic recesses are occupied with the second non-fugitive polymeric phase; wherein the first continuous non-fugitive polymeric phase has an open cell porosity of ≦6 vol %; wherein the second non-fugitive polymeric phase contains an open cell porosity of ≧10 vol %; and, wherein the polishing surface is adapted for polishing a substrate. | 12-29-2016 |
| 20190143478 | MONOLITHIC PLATEN | 05-16-2019 |
| 20190148160 | CLOG DETECTION IN A MULTI-PORT FLUID DELIVERY SYSTEM | 05-16-2019 |
