| Entries |
| Document | Title | Date |
|---|
| 20080206992 | Method for manufacturing high flatness silicon wafer - The present invention relates to a method for manufacturing a high flatness silicon wafer comprising (S | 08-28-2008 |
| 20080227295 | Self-aligned contact frequency doubling technology for memory and logic device applications - Contact spatial-frequency doubling technology is invented to pattern a contact-hole array and a row/column (or multiple isolated rows/columns) of contact holes with their density increased to twice of the maximum density achievable during one exposure with a conventional lithographic technology. These contact frequency doubling processes can be used not only in contact-hole patterning for both memory and logic devices, but also applicable for doubling the density of epi-Si (or epi-SiGe, epi-Ge) columns. If introduced to fabricate vertical MOSFET devices wherein the epi-columns act as the transistor body/channel and drain/source is designed in the vertical way, the epi-column doubling technology can enable cost-effective fabrication processes for high-density 4F | 09-18-2008 |
| 20090004859 | METHOD OF MACHINING WAFER - A method of machining a wafer in which, at the time of grinding the back-side surface of the wafer, only a back-side surface region corresponding to a device formation region where semiconductor chips are formed is thinned by grinding, to form a recessed part on the back side of the wafer. An annular projected part surrounding the recessed part is utilized to secure rigidity of the wafer. Next, the recessed part is etched to cause metallic electrodes to project from the bottom surface of the recessed part, thereby forming a back-side electrode parts, then an insulating film is formed in the recessed part, and the insulating film and end surfaces of the back-side electrode parts are cut. | 01-01-2009 |
| 20090023289 | CONDUCTOR REMOVAL PROCESS - A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns. | 01-22-2009 |
| 20090029550 | Method of Manufacturing Nitride Substrate for Semiconductors - In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 μm to ±100 μm. Since with that bow device fabrication by photolithography is challenging, reducing the bow to +30 μm to −20 μm is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the bow. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the bow. | 01-29-2009 |
| 20090042390 | ETCHANT FOR SILICON WAFER SURFACE SHAPE CONTROL AND METHOD FOR MANUFACTURING SILICON WAFERS USING THE SAME - It is possible to reduce workloads of a both-side simultaneous polishing process or a single-side polishing process, and to achieve both of the maintenance of the wafer flatness and the reduction in wafer front side roughness upon completing a flattening process. A method for manufacturing silicon wafers according to the present invention includes a flattening process | 02-12-2009 |
| 20090047784 | RESIST STRIPPING METHODS USING BACKFILLING MATERIAL LAYER - A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method. | 02-19-2009 |
| 20090053894 | Method for Manufacturing Epitaxial Wafer - A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth. | 02-26-2009 |
| 20090203212 | Surface Grinding Method and Manufacturing Method for Semiconductor Wafer - The present invention provides a surface grinding method for a semiconductor wafer, which performs surface grinding with respect to a semiconductor wafer sliced into a thin plate shape, wherein at least a cleaning process for removing a heavy metal is performed before carrying out surface grinding of the semiconductor wafer, and a surface grinding process is carried out after performing the cleaning process. As a result, there are provided the surface grinding method and a manufacturing method for a semiconductor wafer, which can effectively reduce a contaminant, which has adhered to a surface of the semiconductor wafer, e.g., a heavy metal such as Cu. | 08-13-2009 |
| 20090311862 | Method for manufacturing a semiconductor wafer - By removing residual mechanical stress generated during processing, wafers can be manufactured while suppressing deformation and cracking of the wafer even if the wafer is a large-diameter wafer. A method for manufacturing a wafer, includes: a slicing step (S | 12-17-2009 |
| 20090311863 | METHOD FOR PRODUCING SEMICONDUCTOR WAFER - A semiconductor wafer is produced by a method comprising a slicing step of cutting out a thin disc-shaped semiconductor wafer from a crystalline ingot; a fixed grain bonded abrasive grinding step of sandwiching the semiconductor wafer between a pair of upper and lower plates each having a pad of fixed grain bonded abrasive to simultaneously grind both surfaces of the semiconductor wafer; and a one-side polishing step subjected to both surfaces of the semiconductor wafer after the fixed grain bonded abrasive grinding step. | 12-17-2009 |
| 20100120247 | METHOD OF FORMING FINE PATTERNS USING MULTIPLE SPACER PATTERNS - Fine patterns are formed by forming an etch-target layer on a substrate; forming support patterns on the etch-target layer; forming first spacer patterns on sidewalls of the support patterns; forming second spacer patterns coming in contact with the first spacer patterns; removing the support patterns; and etching the etch-target layer by using the first spacer patterns and the second spacer patterns as an etch mask. | 05-13-2010 |
| 20100273329 | METHOD FOR PREPARING A DONOR SURFACE FOR REUSE - A donor wafer, for example of silicon, has an irregular surface following cleaving of a lamina from the surface, for example by exfoliation following implant of hydrogen and/or helium ions to define a cleave plane. Pinholes in the lamina leave column asperities at the exfoliated surface of the donor wafer, and the beveled edge may leave an edge asperity which fails to exfoliate. To prepare the surface of the donor wafer for reuse, mechanical grinding removes the column and edge asperities, and minimal additional thickness. Following cleaning, growth and removal of an oxide layer at the surface rounds remaining peaks. The smoothed surface is well adapted to bonding to a receiver element and exfoliation of a new lamina. A variety of devices may be fabricated from the lamina, for example a photovoltaic cell. | 10-28-2010 |
| 20100330808 | CAP LAYER REMOVAL IN A HIGH-K METAL GATE STACK BY USING AN ETCH PROCESS - In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics. | 12-30-2010 |
| 20110021025 | METHOD FOR PRODUCING LASER-MARKED SEMICONDUCTOR WAFER - A laser-marked semiconductor wafer having a good flatness in the vicinity of laser mark-printed sites is produced by a method comprising a slicing step; a planarization step; a laser mark printing step; a grinding step; an etching step; and a polishing step. | 01-27-2011 |
| 20110039411 | Method For Producing A Polished Semiconductor Wafer - A polished semiconductor wafer of high flatness is produced by the following ordered steps:
| 02-17-2011 |
| 20110053376 | Wafer dividing apparatus and methods - Example embodiments are directed to a wafer dividing apparatus and method thereof. The wafer dividing apparatus includes a chuck unit having upper and lower chucks, a cutting wire that is provided in a space between the upper and lower chucks to cut a wafer and driven by a first driving unit, and an etchant supplying nozzle supplying etchant to a groove of the wafer, which is formed by the cutting wire. | 03-03-2011 |
| 20110059612 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed. | 03-10-2011 |
| 20110104899 | SUB-LITHOGRAPHIC PRINTING METHOD - A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size. | 05-05-2011 |
| 20110111594 | WAFER BONDING METHOD - Even for the case where a CVD oxide film is interposed at a bonding interface, as a pre-processing of bonding a first wafer and a second wafer, at least the surface roughness of the CVD oxide film of the first wafer is made small after removing organic substances. Therefore, it is possible to prevent void occurrence which is caused by the organic substances existing at and the roughness of the bonding interface of the two wafers. | 05-12-2011 |
| 20110237078 | SiC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a SiC substrate which has a first principal surface and a second principal surface, includes the step of removing, by a vapor phase etching process, at least a portion of a work-affected layer which is formed by mechanical flattening or cutting on the first principal surface of the SiC substrate. | 09-29-2011 |
| 20110263126 | METHOD FOR MANUFACTURING A SILICON WAFER - Method for manufacturing a silicon wafer free of point defect agglomerates by processes including adding pure carbon to raw material of polycrystalline silicon, melting to become a molten silicon liquid, pulling a single silicon crystal ingot comprising a perfect domain [P] from the molten silicon liquid by controlling a ratio of V/G (mm | 10-27-2011 |
| 20110306209 | GROUP III NITRIDE SUBSTRATE, SEMICONDUCTOR DEVICE COMPRISING THE SAME, AND METHOD FOR PRODUCING SURFACE-TREATED GROUP III NITRIDE SUBSTRATE - A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×10 | 12-15-2011 |
| 20120108065 | METHOD FOR MANUFACTURING POLISHING PAD - A method for manufacturing a polishing pad, which may be laminated, with a small number of manufacturing steps, high productivity and no peeling between a polishing layer and a cushion layer includes preparing a cell-dispersed urethane composition by a mechanical foaming method; continuously discharging the cell-dispersed urethane composition onto a face material, while feeding the face material; laminating another face material on the cell-dispersed urethane composition; curing the cell-dispersed urethane composition, while controlling its thickness to be uniform, so that a polishing layer including a polyurethane foam is formed; cutting the polishing layer parallel to the face into two pieces so that two long polishing layers each including the polishing layer and the face material are simultaneously formed; and cutting the long polishing layers to produce the polishing pad. | 05-03-2012 |
| 20120252212 | PROCESSING METHOD FOR WAFER HAVING EMBEDDED ELECTRODES - A wafer processing method which includes a protective member attaching step of attaching a protective member to the front side of the wafer, a back grinding step of grinding the back side of the silicon (Si) substrate of the wafer so as not to expose electrodes to the back side of the silicon (Si) substrate, and an etching step of etching the back side of the silicon (Si) substrate by using an etching liquid to thereby expose the electrodes to the back side of the silicon (Si) substrate. The etching liquid includes a first etching liquid having a high etching rate to silicon (Si) and a second etching liquid capable of etching silicon (Si) and having a low etching rate to silicon dioxide (SiO | 10-04-2012 |
| 20120289048 | Method for obtaining a layout design for an existing integrated circuit - A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure. | 11-15-2012 |
| 20130095659 | METHOD FOR PRODUCING SILICON WAVEGUIDES ON NON-SOI SUBSTRATE - The present invention relates to a method for producing silicon waveguides on non-SOI substrate (non-silicon-on-insulator substrate), and particularly relates to a method for producing silicon waveguides on silicon substrate with a laser. This method includes the following steps: (1) forming a ridge structure with high aspect ratio on a non-SOI substrate; (2) melting and reshaping the ridge structure by laser illumination for forming a structure having broad upper part and narrow lower part; and (3) oxidizing the structure having broad upper part and narrow lower part to form a silicon waveguide. | 04-18-2013 |
| 20130244429 | SHOT BLASTING MATERIAL USED FOR SILICON SUBSTRATE SURFACE TREATMENT AND METHOD FOR PREPARING SILICON SUBSTRATE - A shot blasting material used for silicon substrate surface treatment and a method for preparing a silicon substrate. The shot blasting material includes silicon carbide particles, and the median particle diameter of the silicon carbide particles is 1 μm to 30 μm. Surface treatment can be performed on at least one surface of a silicon substrate in a bombarding manner through the shot blasting material. The particle diameter of the silicon carbide particles used for bombarding is small, and only a mechanical damage layer with a small thickness is formed on a first surface of the silicon substrate, so in the subsequent chemical treatment procedure, it is not required to add concentrated sulfuric acid to a chemical corrosive liquid, and a corrosion step and a cleaning step may be combined into one step, thereby reducing the process flow time, and decreasing the process cost; meanwhile, the method is environment friendly. | 09-19-2013 |
| 20130302983 | TEMPORARY ADHESIVE FOR WAFER PROCESSING, MEMBER FOR WAFER PROCESSING USING THE SAME, WAFER PROCESSED BODY, AND METHOD FOR PRODUCING THIN WAFER - The present invention provided is the temporary adhesive for wafer processing which temporarily bonds a wafer having a circuit face on the front surface and a processing face on the back surface to a support, and includes a first temporary adhesive layer which is a layer (A) of a thermoplastic resin modified organopolysiloxane obtained by partial dehydration condensation of an organopolysiloxane resin containing a R | 11-14-2013 |
| 20130316538 | SURFACE MORPHOLOGY GENERATION AND TRANSFER BY SPALLING - The generation of surface patterns or the replication of surface patterns is achieved in the present disclosure without the need to employ an etching process. Instead, a unique fracture mode referred to as spalling is used in the present disclosure to generate or replicate surface patterns. In the case of surface pattern generation, a surface pattern is provided in a stressor layer and then spalling is performed. In the case of surface pattern replication, a surface pattern is formed within or on a surface of a base substrate, and then a stressor layer is applied. After applying the stressor layer, spalling is performed. Generation or replication of surface patterns utilizing spalling provides a low cost means for generation or replication of surface patterns. | 11-28-2013 |
| 20140030892 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing an ingot made of silicon carbide; obtaining a silicon carbide substrate by cutting the ingot prepared; etching a silicon surface of the silicon carbide substrate; and polishing the etching surface of the silicon carbide substrate after etching the silicon carbide substrate. The step of etching a silicon surface of the silicon carbide substrate includes the step of removing silicon atoms, which form the silicon carbide, from an etching region using chlorine gas, the etching region including the etching main surface of the silicon carbide substrate. | 01-30-2014 |
| 20140256133 | POST METAL CHEMICAL-MECHANICAL PLANARIZATION CLEANING PROCESS - A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module. | 09-11-2014 |
| 20140315384 | METHOD OF PROCESSING A DEVICE SUBSTRATE - Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate. | 10-23-2014 |
| 20150318174 | METHOD FOR MANUFACTURING SIC SUBSTRATE - A method for manufacturing a SiC substrate is provided. The method includes: a sacrificial film-forming process of forming a sacrificial film on a surface of a SiC substrate in a film thickness that is equal to or greater than a maximum height difference of the surface; a sacrificial film planarization process of planarizing a surface of the sacrificial film by mechanical processing; and a SiC substrate planarization process of performing dry etching under conditions in which etching selectivity between the SiC substrate and the sacrificial film is in a range of 0.5 to 2.0 so as to remove the sacrificial film and so as to planarize the surface of the SiC substrate. | 11-05-2015 |
| 20150332909 | WAFER PROCESSING METHOD - A method of processing a wafer includes: a grinding step of grinding a back surface of the wafer to form, on the back side of the wafer, a recess corresponding to a device region and an annular projecting portion corresponding to a peripheral marginal region; and a splitting groove forming step of forming, after the grinding step is conducted, a splitting groove for splitting the device region and the peripheral marginal region from each other at the boundary between the recess and the annular projecting portion, the splitting groove extending from the front surface of the wafer to reach the back surface of the wafer. The splitting groove is formed by dry etching. | 11-19-2015 |
| 20160027679 | METHOD FOR REPAIRING AN OXIDE LAYER AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE APPLYING THE SAME - A method for repairing an oxide layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for repairing an oxide layer comprises following steps. First, a carrier having a first area and a second area is provided, wherein a repairing oxide layer is formed on the second area. Then, the carrier is attached to a substrate with an oxide layer to be repaired formed thereon, wherein the carrier and the substrate are attached to each other through the repairing oxide layer and the oxide layer to be repaired. Thereafter, the oxide layer to be repaired is bonded with the repairing oxide layer. | 01-28-2016 |
| 20160133476 | FABRICATION METHOD OF SEMICONDUCTOR PIECE - A fabrication method of a semiconductor piece includes forming a groove that has a first groove portion, and a second groove portion which is a groove portion formed to communicate with a lower part of the first groove portion and extends toward a lower part at a steeper angle than an angle of the first groove portion, has a shape without an angle portion between the first groove portion and the second groove portion, is positioned on the front side, and is formed by dry etching; affixing a retention member including an adhesive layer to the surface in which the groove on the front side is formed; thinning the substrate from the back side of the substrate in a state in which the retention member is affixed; and removing the retention member from the surface after the thinning. | 05-12-2016 |
| 20160141182 | SLURRY COMPOSITIONS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME - Provided are slurry compositions for polishing a germanium-containing layer and methods of fabricating a semiconductor device using the same. The slurry composition may include a polishing particle, an oxidizing agent, a polishing accelerator, and a selectivity control agent. The oxidizing agent may include at least one selected from the group consisting of superoxide, dioxygenyl, ozone, ozonide, chlorite, chlorate, perchlorate, halogen compounds, nitric acid, nitrate, hypochlorite, hypohalite, and peroxide. | 05-19-2016 |
| 20160197227 | THIN FILM LIFT-OFF VIA COMBINATION OF EPITAXIAL LIFT-OFF AND SPALLING | 07-07-2016 |
