| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438643000 |
At least one layer forms a diffusion barrier
| 114 |
| 438648000 |
Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)
| 10 |
| 438650000 |
Having noble group metal (i.e., silver (Ag), gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), osmium (Os), or alloy thereof) | 5 |
| 20080242079 | IN-SITU FORMATION OF CONDUCTIVE FILLING MATERIAL IN THROUGH-SILICON VIA - The formation of electronic assemblies including a die having through vias is described. In one embodiment, a method includes providing Si die including a first surface and a second surface opposite the first surface, and forming a via extending through the Si die from the first surface to the second surface. The via is formed to have a larger width at the first surface than at the second surface, the larger width at the first surface being no less than 100 microns. The method also includes placing a plurality of particles in the via, wherein at least some of the particles comprise a polymer and at least some of the particles comprise a metal. The method also includes heating the die and the particles in the via to cross-link at least part of the polymer in the via, and cooling the die to solidify the polymer and form a electrically conductive composite including the cross-linked polymer and the metal in the via. Other embodiments are described and claimed. | 10-02-2008 |
| 20080318417 | METHOD OF FORMING RUTHENIUM FILM FOR METAL WIRING STRUCTURE - A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a non-cyclic dienyl; (ii) supplying an excited reducing gas into the reaction chamber to activate the ruthenium precursor adsorbed onto the substrate; and (iii) repeating steps (i) and (ii), thereby forming a ruthenium thin film on the substrate. | 12-25-2008 |
| 20100285660 | COPPER DEPOSITION FOR FILLING FEATURES IN MANUFACTURE OF MICROELECTRONIC DEVICES - A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper wettable metal to fill the feature with copper. | 11-11-2010 |
| 20120329271 | DISCONTINUOUS/NON-UNIFORM METAL CAP STRUCTURE AND PROCESS FOR INTERCONNECT INTEGRATION - A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform. | 12-27-2012 |
| 20130252419 | Metal Alloy Cap Integration - A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap. | 09-26-2013 |
| 438644000 |
Having adhesion promoting layer | 3 |
| 20090004848 | METHOD FOR FABRICATING INTERCONNECTION IN SEMICONDUCTOR DEVICE - A method for fabricating an interconnection in a semiconductor device includes forming a hydrogenated tungsten nucleation layer on a semiconductor substrate, and forming a bulk tungsten layer on the tungsten nucleation layer. Boron ions react with a hydrogen gas supplied together with a diborane gas to be restored to a diborane again, thereby preventing a boron layer from being formed on an interface of the tungsten nucleation layer. | 01-01-2009 |
| 20090029544 | ADHESION AND MINIMIZING OXIDATION ON ELECTROLESS CO ALLOY FILMS FOR INTEGRATION WITH LOW K INTER-METAL DIELECTRIC AND ETCH STOP - A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on a substrate, exposing the capping layer to a plasma, heating the substrate to more than about 100° C., and depositing a low dielectric constant material. | 01-29-2009 |
| 20110151659 | MULTILAYERED THROUGH A VIA - A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV. | 06-23-2011 |
| 438645000 |
Having planarization step | 3 |
| 20090053890 | SELECTIVE THIN METAL CAP PROCESS - A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits a thin (e.g., 5 nm) metal blanket film (e.g., Ta/TaN) on top the copper lines and dielectric, after the wafer has been planarized. Further a thin dielectric cap is formed over the metal blanket film. A photoresist coating is deposited over the thin dielectric cap and a lithographic exposure process is performed, but without a lithographic mask. A mask is not needed in this situation, because due to the reflectivity difference between copper and the ILD lying under the two thin layers, a mask pattern is automatically formed for etching away the Ta/TaN metal cap between copper lines. Thus, this mask pattern is self-aligned above the copper lines. | 02-26-2009 |
| 20090170310 | METHOD OF FORMING A METAL LINE OF A SEMICONDUCTOR DEVICE - In a method of forming a metal line of a semiconductor device, a dielectric film is formed on a semiconductor substrate. A plurality of parallel photoresist patterns are formed over the entire structure including the dielectric film. A spacer is formed on sidewalls of the photoresist patterns. The dielectric film is exposed by removing the photoresist patterns. Damascene patterns are formed by etching the exposed dielectric film. The spacer is removed. Metal material is formed over the entire structure including the damascene patterns and polishing the metal material, thereby forming a metal line. | 07-02-2009 |
| 20160254183 | Multi-Layer Metal Contacts | 09-01-2016 |
| 438647000 |
Having electrically conductive polysilicon component | 2 |
| 20120015515 | MANUFACTURING METHOD FOR A BURIED CIRCUIT STRUCTURE - A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer. | 01-19-2012 |
| 20120196436 | MANUFACTURING METHOD FOR A BURIED CIRCUIT STRUCTURE - A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a patterned photoresist having a surface lower than an opening of the trench in the trench, removing the first conductive layer not covered by the patterned photoresist to form a second conductive layer having a top lower than an opening of the trench in the trench, removing the patterned photoresist, performing a dry etching process to remove the second conductive layer from the bottom of the trench to form a third conductive layer on the sidewalls of the trench, performing a selective metal chemical vapor deposition to form a metal layer having a surface lower than a surface of the substrate, and forming a protecting layer filling the trench on the metal layer. | 08-02-2012 |
| Entries |
| Document | Title | Date |
|---|
| 20110008958 | Methods of Selectively Growing Nickel-Containing Materials - The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel salt. | 01-13-2011 |
| 20120276736 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing. | 11-01-2012 |
| 20130237053 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming method which generates metal ions from a metal target with a plasma in a processing chamber and attracts the metal ions with a bias to deposit a metal thin film on a target object wherein trenches are formed. The method includes: generating metal ions from a target and attracting the metal ions into a target object with a bias to form a base film in a trench; ionizing a rare gas with the bias in a state where no metal ion is generated and attracting the generated ions into the target object to etch the base film; and plasma sputtering the target to generate metal ions and attracting the metal ions into the object with a high frequency power for bias to deposit a main film as a metal film, while reflowing the main film by heating. | 09-12-2013 |
| 20140363970 | METHOD OF MAKING A PILLAR STRUCTURE HAVING A NON-METAL SIDEWALL PROTECTION STRUCTURE - A method of making a pillar structure includes forming a first under-bump-metallurgy (UBM) layer formed on a pad region of a substrate, wherein the first UBM layer includes sidewalls. The method further includes forming a second UBM layer on the first UBM layer, wherein the second UBM layer includes a sidewall surface, an area of the first UBM layer is greater than an area of the second UBM layer. The method further includes forming a copper-containing pillar on the second UBM layer, wherein the copper-containing pillar includes a sidewall surface and a top surface. The method further includes forming a protection structure on the sidewall surface of the copper-containing pillar and on an entirety of the sidewall surface of the second UBM layer, wherein the protection structure does not cover the sidewalls of the first UBM layer, and the protection structure is a non-metal material. | 12-11-2014 |
| 20150340282 | CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTMES, DEVICES, AND METHODS - Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate. | 11-26-2015 |
