| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438648000 | Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof) | 10 |
| 20080305629 | TUNGSTEN NITRIDE ATOMIC LAYER DEPOSITION PROCESSES - In one embodiment, a method for forming a tungsten barrier material on a substrate is provided which includes depositing a tungsten layer on a substrate during a vapor deposition process and exposing the substrate sequentially to a tungsten precursor and a nitrogen precursor to form a tungsten nitride layer on the tungsten layer. Some examples provide that the tungsten layer may be deposited by sequentially exposing the substrate to the tungsten precursor and a reducing gas (e.g., diborane or silane) during an atomic layer deposition process. The tungsten layer may have a thickness of about 50 Å or less and tungsten nitride layer may have an electrical resistivity of about 380 μΩ-cm or less. Other examples provide that a tungsten bulk layer may be deposited on the tungsten nitride layer by a chemical vapor deposition process. | 12-11-2008 |
| 20090163022 | TFT ARRAY PANEL - Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111). | 06-25-2009 |
| 20100035427 | METHODS FOR GROWING LOW-RESISTIVITY TUNGSTEN FILM - Improved methods for depositing low resistivity tungsten films are provided. The methods involve depositing a tungsten nucleation layer on a substrate and then depositing a tungsten bulk layer over the tungsten nucleation layer to form the tungsten film. The methods provide precise control of the nucleation layer thickness and improved step coverage. According to various embodiments, the methods involve controlling thickness and/or improving step coverage by exposing the substrate to pulse nucleation layer (PNL) cycles at low temperature. Also in some embodiments, the methods may improve resistivity by using a high temperature PNL cycle of a boron-containing species and a tungsten-containing precursor to finish forming the tungsten nucleation layer. | 02-11-2010 |
| 20100087060 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - The present invention relates to methods of forming semiconductor structures. The methods may include disposing electrically conductive material within an opening in a first dielectric material, passivating an upper surface of the electrically conductive material and introducing materials to form an interlayer dielectric upon the passivated upper surface. The present invention also includes methods of passivating surfaces of a semiconductor structure with a nitrogen-containing species. | 04-08-2010 |
| 20100267230 | METHOD FOR FORMING TUNGSTEN CONTACTS AND INTERCONNECTS WITH SMALL CRITICAL DIMENSIONS - Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process. | 10-21-2010 |
| 20110250749 | INTERCONNECTS WITH IMPROVED ELECTROMIGRATION RELIABILITY - An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality of segments to enable the interconnect structure to avoid electromigration problems. | 10-13-2011 |
| 20120329270 | SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS - A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material. | 12-27-2012 |
| 20150037973 | METHOD FOR CAPPING COPPER INTERCONNECT LINES - A method of forming a capping layer over copper containing contacts in a dielectric layer with a liner comprising a noble metal liner around the copper containing contacts is provided. An electroless deposition is provided to deposit a deposition comprising copper on the noble metal liner and the copper containing contacts. A capping layer is formed over the deposition comprising copper. | 02-05-2015 |
| 438649000 | Silicide | 2 |
| 20100167528 | LOW RESISTANCE METAL SILICIDE LOCAL INTERCONNECTS AND A METHOD OF MAKING - A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect. | 07-01-2010 |
| 20130273734 | METHOD OF MANUFACTURING METAL SALICIDE LAYERS - A method of manufacturing salicide layers includes the following steps. Firstly, a silicon substrate with a patterned stack structure of a silicon layer and a first cap layer sequentially formed thereon is provided. Then, a second cap layer is formed on the exposed silicon substrate. The materials of the first cap layer and the second cap layer are different. Then, the first cap layer is removed to expose the silicon layer. Then, a first metal layer is formed on the silicon layer and reacted with the silicon layer to produce a first salicide layer. Afterward, the second cap layer is removed, and a second metal layer is formed over the surface of the silicon substrate and reacted with the silicon substrate to produce a second salicide layer. | 10-17-2013 |
Patent applications in class Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)
Patent applications in all subclasses Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)
