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Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)

Subclass of:

438 - Semiconductor device manufacturing: process

438584000 - COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL

438597000 - To form ohmic contact to semiconductive material

438618000 - Contacting multiple semiconductive regions (i.e., interconnects)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438637000 With formation of opening (i.e., viahole) in insulative layer 197
438625000 At least one metallization level formed of diverse conductive layers 125
438631000 Having planarization step 27
438624000 Separating insulating layer is laminate or composite of plural insulating materials 22
438623000 Including organic insulating material between metal levels 16
438636000 Including use of antireflective layer 6
438641000 Selective deposition 4
20140080300MULTI-LAYER CIRCUIT SUBSTRATE FABRICATION METHOD PROVIDING IMPROVED TRANSMISSION LINE INTEGRITY AND INCREASED ROUTING DENSITY - An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.03-20-2014
20150044866INTERCONNECTION OF SEVERAL LEVELS OF A STACK OF SUPPORTSFOR ELECTRONIC COMPONENTS - Method for producing a microelectronic device formed from a stack of supports (W) each provided with one or more electronic components (C) and comprising a conductive structure (02-12-2015
20150087146MICROELECTRONIC INTERCONNECT ELEMENT WITH DECREASED CONDUCTOR SPACING - A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.03-26-2015
20160181154SEMICONDUCTOR DEVICE WITH MULTI-LAYER METALLIZATION06-23-2016
438635000 Insulator formed by reaction with conductor (e.g., oxidation, etc.) 1
20150132944ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory circuit. The semiconductor memory circuit includes a plurality of first conductive lines which includes an anti-oxidation layer on both sides of each first conductive line, an inter-layer dielectric layer suitable for gap-filling a space between the first conductive lines, a material layer formed over the first conductive lines and the inter-layer dielectric layer and including oxygen vacancies, and a plurality of second conductive lines formed over the material layer to intersect with the first conductive lines. A first portion of the material layer where the first conductive lines and the second conductive lines overlap each other has a lower oxygen content than a second portion of the material layer where the inter-layer dielectric layer and the second conductive lines overlap each other.05-14-2015
Entries
DocumentTitleDate
20080227287Method For Dual Damascene Process - The present disclosure provides a method of dual damascene processing. The method includes providing a substrate having vias formed therein; forming an under-layer in the vias and on the substrate; applying a solvent washing process to the under-layer; forming a silicon contained layer on the under-layer; patterning the silicon contained layer (SCL) to form SCL openings exposing the under-layer within the SCL openings; and etching the substrate and the under-layer within the SCL openings to form trenches.09-18-2008
20080227288Dual damascene process - A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.09-18-2008
20080227289Method of Fabricating Integrated Circuitry - The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.09-18-2008
20080242077Strained metal silicon nitride films and method of forming - A method for forming a strained metal nitride film and a semiconductor device containing the strained metal nitride film. The method includes exposing a substrate to a gas containing a metal precursor, exposing the substrate to a gas containing a silicon precursor, exposing the substrate to a gas containing a nitrogen precursor activated by a plasma source at a first level of plasma power and configured to react with the metal precursor or the silicon precursor with a first reactivity characteristic, and exposing the substrate to a gas containing the nitrogen precursor activated by the plasma source at a second level of plasma power different from the first level and configured to react with the metal precursor or the silicon precursor with a second reactivity characteristic such that a property of the metal silicon nitride film formed on the substrate changes to provide the strained metal silicon nitride film.10-02-2008
20080254612POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES - Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition Si10-16-2008
20080286960Method of manufacturing semiconductor device suitable for forming wiring using damascene method - (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.11-20-2008
20080293239Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment - A first conductive layer is formed. An insulating layer is formed so that at least a part of the insulating layer is disposed on the first conductive layer. A second conductive layer is formed so that at least a part of the second conductive layer is disposed on the insulating layer over the first conductive layer. Each of the first and second conductive layers is formed by discharging drops of a solvent containing fine particles of a conductive material. The insulating layer is formed by discharging drops of a solvent containing fine particles of an insulating material.11-27-2008
20080311737Manufacturing method for semiconductor device containing stacked semiconductor chips - An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.12-18-2008
20090004843METHOD FOR FORMING DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY - Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.01-01-2009
20090035934Self-Aligned Cross-Point Memory Fabrication - Fabricating a cross-point memory structure using two lithography steps with a top conductor and connector or memory element and a bottom conductor orthogonal to the top connector. A first lithography step followed by a series of depositions and etching steps patterns a first channel having a bottom conductor. A second lithography step followed by a series of depositions and etching steps patterns a second channel orthogonal to the first channel and having a memory element connecting the an upper conductor and the lower conductor at their overlaid intersections.02-05-2009
20090075471Method of manufacturing semiconductor memory device - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.03-19-2009
20090098726METHOD FOR FORMING INLAID INTERCONNECT - After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.04-16-2009
20090111261Over-passivation process of forming polymer layer over IC chip - A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes.04-30-2009
20090170307METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal connecting terminal, and the metal layer is pressed to cause the metal layer in a corresponding portion to a wiring pattern to come in contact with the internal connecting terminal, and to then bond the metal layer in a portion provided in contact with the internal connecting terminal to the internal connecting terminal in a portion provided in contact with the metal layer.07-02-2009
20090176365CONTACT FORMATION - The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.07-09-2009
20090258488METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING STORAGE NODE LANDING PADS SEPARATED FROM BIT LINE CONTACT PLUGS - A method can include forming gate lines on a semiconductor substrate and forming a first interlayer dielectric layer for insulating the gate lines from each other. First and second contact plugs are formed on the semiconductor substrate and landing pads are formed on the first contact plugs and the first interlayer dielectric layer to overlap portions of the first contact plugs. Recessed contact plugs are formed to have recessed portions by etching the second contact plugs, to be located below an upper surface of the first interlayer dielectric layer, where a cross-sectional total distance between the landing pads and the recessed contact plugs increases due to the recessed portions.10-15-2009
20100041228Method of manufacturing a wiring board - In a method of manufacturing a wiring board, a basic circuit pattern is formed on an insulating plate, and a metal layer is formed on the basic circuit pattern by cold spraying to thereby form a built-up circuit pattern on the basic circuit pattern.02-18-2010
20100041229METHOD AND FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.02-18-2010
20100081271METHOD OF FORMING A DIFFUSION BARRIER AND ADHESION LAYER FOR AN INTERCONNECT STRUCTURE - A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening.04-01-2010
20100112802MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a first wiring pattern on a surface of each of the first insulating layer and the second insulating layer; a sixth step of forming a via-hole from which the first wiring pattern is exposed on the second insulating layer; and a seventh step of forming a second wiring pattern electrically connected on a surface of the second insulating layer.05-06-2010
20100136781SIMULTANEOUS VIA AND TRENCH PATTERNING USING DIFFERENT ETCH RATES - One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.06-03-2010
20100167523SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a wiring formed in predetermined pattern above the semiconductor substrate, a first insulating film lying right under the wiring, and a second insulating film lying in a peripheral portion other than a portion right under the wiring, in which a surface layer of the first insulating film lying in a boundary surface between the first insulating film and the second insulating film is chemically modified to reinforce the surface layer.07-01-2010
20100261345METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a semiconductor device and method of manufacturing thereof, a first insulation interlayer is formed on a substrate including a lower conductive pattern. The first insulation interlayer has a first opening through which the lower conductive pattern is exposed. An interconnection is formed in the first opening such that the interconnection is contact with the lower conductive pattern and protruded from the first insulation interlayer. A second insulation interlayer is formed on the first insulation interlayer in such a manner that the second insulation interlayer has a second opening through the interconnection is exposed and the second opening is centrally aligned with the interconnection. An upper conductive pattern is formed in the second opening such that the upper conductive pattern is contacted with the interconnection. Accordingly, a mis-alignment between the upper conductive pattern and the interconnection is prevented.10-14-2010
20100311235SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A semiconductor device has first wiring layers 12-09-2010
20100330800METHODS OF FORMING LAYERS OF ALPHA-TANTALUM - A method of forming a layer of alpha-tantalum on a substrate including the steps of depositing a layer of titanium nitride on a substrate; and depositing a layer of alpha-tantalum on the layer of titanium nitride, wherein the deposition of the alpha-tantalum is carried out at temperatures below about 300° C.12-30-2010
20110021017METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.01-27-2011
20110165773Circuit Signal Connection Interface - A circuit signal connection interface, a manufacturing method thereof, and an electronic device using the same are provided. The circuit signal connection interface includes a first signal line and a second signal line juxtaposed to each other, an insulation layer, and a first conductive pad. The first conductive pad electrically connects to the first signal line, and crosses the second signal line. The insulation layer is disposed between the second signal line and the first conductive pad. The electronic device further includes a circuit device including a first conducting bump and a second conducting bump connected to each other in a parallel manner. The first conducting bump electrically connects to a first portion of the first conductive pad while the second conducting bump electrically connects to a second portion of the first conductive pad.07-07-2011
20110165774Contact and Via Interconnects Using Metal Around Dielectric Pillars - An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.07-07-2011
20110171823DIELECTRIC SPACERS FOR METAL INTERCONNECTS AND METHOD TO FORM THE SAME - A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land.07-14-2011
20110269307Method for Making Integrated Circuit Device Using Copper Metallization on 1-3 PZT Composite - Provided herein is a method of making an integrated circuit device using copper metallization on 1-3 PZT composite. The method includes providing an overlay of electroplated immersion of gold (Au) to cover copper metal traces, the overlay preventing oxidation on 1:3 PZT composite with material. Also included is the formation of immersion Au nickel electrodes on the 1-3 PZT composite to achieve pad metallization for external connections.11-03-2011
20110287627SEMICONDUCTOR TEST PAD STRUCTURES - A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.11-24-2011
20120009779CONTACT FORMATION - The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes forming a filler material in the trench and removing the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes forming a spacer material on at least one side surface of the trench to the particular depth of the filler material and forming a conductive material in the trench over the filler material.01-12-2012
20120034774Energy Conditioning Circuit Arrangement for Integrated Circuit - The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.02-09-2012
20120135599CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYERS CONFIGURED TO BLOCK ELECTROMAGNETIC EDGE INTERFERENCE - Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.05-31-2012
20130005136Methods Of Forming Metal Silicide-Comprising Material And Methods Of Forming Metal Silicide-Comprising Contacts - A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.01-03-2013
20130012018ON-CHIP COOLING FOR INTEGRATED CIRCUITS - A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.01-10-2013
20130089978INTEGRATED CIRCUIT USING FDSOI TECHNOLOGY, WITH WELL SHARING AND MEANS FOR BIASING OPPOSITELY DOPED GROUND PLANES PRESENT IN A SAME WELL - A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.04-11-2013
20130095652METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming an interlayer insulating film on a substrate; forming a first hard mask formation film on the interlayer insulating film; altering the first hard mask formation film; after the altering of the first hard mask formation film, transferring an interconnect groove pattern to the altered first hard mask formation film to form a first hard mask made of the altered first hard mask formation film; and etching the interlayer insulating film using the first hard mask to form an interconnect groove in the interlayer insulating film. The first hard mask formation film is made of a metal film or a metallic compound film.04-18-2013
20130095653NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND STRINGS AND METHODS OF FORMING THE SAME - A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.04-18-2013
20130109170DEPOSITION METHOD AND A DEPOSITION APPARATUS OF FINE PARTICLES, A FORMING METHOD AND A FORMING APPARATUS OF CARBON NANOTUBES, AND A SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME05-02-2013
20130237051METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.09-12-2013
20130295764METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES - A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided11-07-2013
20140045328INTERCONNECTION STRUCTURE FOR N/P METAL GATES - A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening and removing the dummy electrode. The method further includes depositing a first work-function metal layer in the first and second portions, whereby the first work-function metal layer is over the second work-function metal layer in the opening and depositing a signal metal layer over the first work-function metal layer in the first and second portions.02-13-2014
20140094028Contact and Via Interconnects Using Metal Around Dielectric Pillars - An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.04-03-2014
20140199831SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.07-17-2014
20140235050Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.08-21-2014
20140322910VIA-FREE INTERCONNECT STRUCTURE WITH SELF-ALIGNED METAL LINE INTERCONNECTIONS - The present disclosure provides a method for forming a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.10-30-2014
20140363967THROUGH SILICON VIAS FOR SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.12-11-2014
20150087145Chip Comprising an Integrated Circuit, Fabrication Method and Method for Locally Rendering a Carbonic Layer Conductive - A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit.03-26-2015
20150318203STAIR STEP FORMATION USING AT LEAST TWO MASKS - Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.11-05-2015
20160204031SHIELDED COPLANAR LINE07-14-2016
20170236753PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE08-17-2017
20180025913SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME01-25-2018

Patent applications in class Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)

Patent applications in all subclasses Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)

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