| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438623000 | Including organic insulating material between metal levels | 16 |
| 20080286961 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: forming a via pattern in an insulating film by use of an alignment mark of a lower wiring line; forming, by use of an alignment mark of the via pattern, an upper wiring groove pattern in an upper insulating film in which the via pattern is embedded; and repeating etching in a self-aligning manner to form a via and a wiring groove in an insulating film previously stacked under the insulating film in which the via pattern has been formed. | 11-20-2008 |
| 20080299759 | Method to form a via - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 12-04-2008 |
| 20080299760 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A highly reliable method for forming contact plugs is provided. The method can prevent short circuiting from occurring between self aligned contact plugs and word lines or between self aligned contact plugs and bit lines by applying a material, whose etching speed ratio relative to that of the silicon-based insulating film is | 12-04-2008 |
| 20080305625 | POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS - A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth. | 12-11-2008 |
| 20080311738 | METHOD OF FORMING AN INTERCONNECT JOINT - A method of forming an interconnect joint includes providing a first metal layer ( | 12-18-2008 |
| 20080318409 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD FOR ETCHING THE SAME - A method for manufacturing a dual damascene structure includes forming a wiring layer over a substrate, forming an inorganic insulating film over the wiring layer, forming a via hole in the inorganic insulating film using a first resist pattern with an opening as an etching mask, removing the first resist pattern, forming an organic insulating film on the inorganic insulating film and in the via hole, forming a hard mask on the organic insulating film, forming a hard mask pattern using a second resist pattern with an opening on the hard mask as an etching mask, forming a wiring groove by etching the organic insulating film using the second resist pattern and the hard mask pattern as etching masks until the organic insulating film inside the via hole is eliminated and simultaneously eliminating the second resist pattern, and implanting a conductive substance into the via hole and wiring groove. | 12-25-2008 |
| 20090011592 | METHOD OF MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N | 01-08-2009 |
| 20090075472 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS - Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. | 03-19-2009 |
| 20100055896 | SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a volatile organic memory in which data can be written other than during manufacturing and falsification by rewriting can be prevented, and to provide a semiconductor device including such an organic memory. It is a feature of the invention that a semiconductor device includes a plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction different from the first direction; a memory cell array including a plurality of memory cells each provided at one of intersections of the bit lines and the word lines; and memory elements provided in the memory cells, wherein the memory elements include bit lines, an organic compound layer, and the word lines, and the organic compound layer includes a layer in which an inorganic compound and an organic compound are mixed. | 03-04-2010 |
| 20110312177 | PATTERNABLE DIELECTRIC FILM STRUCTURE WITH IMPROVED LITHOGRAPHY AND METHOD OF FABRICATING SAME - The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate, said inorganic antireflective coating is vapor deposited and comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La; forming at least one interconnect pattern within the at least one patternable low-k material; and curing the at least one patternable low-k material. The inventive method can be used to form dual-damascene interconnect structures as well as single-damascene interconnect structures. | 12-22-2011 |
| 20120028458 | ALPHA PARTICLE BLOCKING WIRE STRUCTURE AND METHOD FABRICATING SAME - An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive terminal pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer. | 02-02-2012 |
| 20120231622 | SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME - A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided. | 09-13-2012 |
| 20130189836 | PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF - Silsesquioxane polymers that cure to porous silsesquioxane polymers, silsesquioxane polymers that cure to porous silsesquioxane polymers in negative tone photo-patternable dielectric formulations, methods of forming structures using negative tone photo-patternable dielectric formulations containing silsesquioxane polymers that cure to porous silsesquioxane polymers, structures containing porous silsesquioxane polymers and monomers and method of preparing monomers for silsesquioxane polymers that cure to porous silsesquioxane polymers. | 07-25-2013 |
| 20160097898 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE - An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via. | 04-07-2016 |
| 20160118359 | Interconnect Structures and Methods of Forming Same - Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. | 04-28-2016 |
| 20160172232 | Interconnect Having Air Gaps and Polymer Wrapped Conductive Lines | 06-16-2016 |
