| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438615000 | Including fusion of conductor | 33 |
| 20080206980 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD AND STRUCTURE FOR IMPLEMENTING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved. | 08-28-2008 |
| 20100105201 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved. | 04-29-2010 |
| 20100190333 | METHOD OF FORMING CONNECTION TERMINAL - A method of forming a connection terminal may include preparing a substrate, forming a first conductor of a tube shape having an opened upper portion on the substrate, forming a second conductor on the first conductor, and annealing the second conductor so that a portion of the second conductor extends in an internal space of the first conductor through the opened upper portion. | 07-29-2010 |
| 20100210101 | Formation of Solder Bumps - A method of providing connections to a chip having contact pads on the surface thereof, comprising: locating a discrete solder element on each pad; and melting the discrete solder elements so as to cause each of them to adhere to the respective pad, thereby forming a solder bump extending from the surface of the chip; wherein the size of each discrete solder element relative to the area of the pad on which it is located is such that the height of each bump is less than 70% of the diameter of the solder element that formed it. | 08-19-2010 |
| 20110053368 | Arrangement for solder bump formation on wafers - An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon. | 03-03-2011 |
| 20110151657 | METHOD FOR FABRICATING ELECTRICAL BONDING PADS ON A WAFER - A method for fabricating electrical bonding pads on the electrical contact areas of a wafer includes producing first blocks made of a solder material, producing second blocks made of a solder material on these first blocks, and passing the blocks through an oven so as to shape the blocks into approximately domed electrical bonding pads. | 06-23-2011 |
| 20110237065 | SOLDERING FLUX AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - Soldering flux includes: a solvent of which solubility in water is more than 0.01% by weight and less than 6.8% by weight; an organic acid component; and amine counteracting the organic acid component. A solubility of the amine in water is more than 5.0% by weight, and the amine is able to be linked to a conductive metal via a coordination linkage. A solder bump is formed by heating a solder ball with the soldering flux. The residue of the flux on the surface of the solder bump has water solubility, and is easily eliminated. Further, the conductive metal coordinated to the amine is deposited on the surface of the solder bump by water washing. As a result, when testing the semiconductor device having the solder bump | 09-29-2011 |
| 20120088362 | Thermal Compressive Bond Head - A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump. | 04-12-2012 |
| 20120108053 | APPARATUS, SYSTEM, AND METHOD FOR WIRELESS CONNECTION IN INTEGRATED CIRCUIT PACKAGES - Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed. | 05-03-2012 |
| 20120244697 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved. | 09-27-2012 |
| 20130217224 | Micro Bump And Method For Forming The Same - A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam. | 08-22-2013 |
| 20130309862 | METHOD FOR MANUFACTURING Sn ALLOY BUMP - Provided is a method for manufacturing an Sn alloy bump, wherein composition of the Sn alloy bump can be readily controlled. The method for manufacturing an Sn alloy bump formed of an alloy composed of Sn and other one or more types of metals has a step of forming an Sn layer on an electrode pad in a resist opening formed on a substrate by electrolytic plating; a step of laminating Sn and an alloy layer on the Sn layer by electrolytic plating; and a step of forming an Sn alloy bump by melting the Sn layer and the laminated alloy layer after removal of a resist. | 11-21-2013 |
| 20150318191 | MOLDED INSULATOR IN PACKAGE ASSEMBLY - Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material. In some embodiments, an apparatus includes an electrical element (such as a die or a bridge interconnect structure) positioned on a surface of an insulator layer, a conductive pad positioned on the surface of the insulator layer and spaced apart from the electrical element, and a molded insulator material disposed on the surface of the insulator layer adjacent to the electrical element and on the conductive pad. Other embodiments may be described and/or claimed. | 11-05-2015 |
| 20160043048 | PREVENTING MISSHAPED SOLDER BALLS - “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer. | 02-11-2016 |
| 20160141261 | Ball Amount Process in the Manufacturing of Integrated Circuit - An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness. | 05-19-2016 |
| 438616000 | By transcription from auxiliary substrate | 3 |
| 20090004840 | Method of Creating Molds of Variable Solder Volumes for Flip Attach - A method for fabricating a solder transfer mold includes masking a substrate with a masking agent. A pattern is transferred to the substrate mask. The masked substrate is etched until cavities of a first volume are formed. The cavities of the first volume are selectively coated. The masked substrate is etched until cavities of a second volume are formed. | 01-01-2009 |
| 20090298278 | METHOD OF BONDING SEMICONDUCTOR DEVICES UTILIZING SOLDER BALLS - A method for bonding a semiconductor device onto a substrate is provided which comprises the steps of picking up a solder ball with a pick head, placing the solder ball onto the substrate and melting the solder ball on the substrate and placing the semiconductor device on the molten solder ball. The molten solder ball is then allowed to cool to form a solder joint which bonds the semiconductor device to the substrate. | 12-03-2009 |
| 20110092066 | Bumping Electronic Components Using Transfer Substrates - A method for forming solder bumps on an electronic component. Providing a transfer substrate having a plurality of solder balls, disposing the transfer substrate on the surface of the electronic component, heating to reflow the solder balls onto the electronic component; and removing the sacrificial substrate. The transfer substrate may comprise a sacrificial film and a metal layer patterned with a mask which is used to form solder balls on the transfer substrate. Or, the transfer substrate may comprise a sheet of material having solder balls embedded at least partially in the sheet. A method of aligning a part being bumped with a transfer substrate, using a shuttle mechanism and an alignment film is disclosed. | 04-21-2011 |
| 438617000 | By wire bonding | 15 |
| 20080227284 | Wire bonding method and related device for high-frequency applications - A wire bond circuit device has a circuit die in which substantially all of the input/output (I/O) pads are disposed along the outermost row of pads. A substrate onto which the die is disposed has wedges that are similarly arranged in rows, with the wedges used to carry I/O placed closest to the circuit die. As a result, lowest-tiered bond wire is used to connect the I/O-related pads to their respective wedges. | 09-18-2008 |
| 20080227285 | WIREBOND STRUCTURE AND METHOD TO CONNECT TO A MICROELECTRONIC DIE - A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C. | 09-18-2008 |
| 20080233733 | METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT - A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure. | 09-25-2008 |
| 20080242076 | METHOD OF MAKING SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND - A method of making a semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad. | 10-02-2008 |
| 20080286959 | Downhill Wire Bonding for QFN L - Lead - Downhill wire bonding process for QFN is performed with a capillary using goldwire that connects die (the Integrated Circuit or the substrate) and the stitch platform also called lead fingers. The goldwire is molten into a ball by applying high current. The molten ball is compressed against the bond pads of the integrated circuit using high temperature and ultrasonic energy. To complete the connection, the capillary is lifted vertically from the bond pads of the die or integrated circuit to loop over to the lead finger so that the goldwire is compressed against the lead finger with a reduced angle of approach of the capillary. Downhill wire bonding of the lead frames is advantageously addressed by increasing the thickness of the stitch platform so as to reduce the angle of approach of the capillary during the downhill wire bonding process between various components of the semiconductor. | 11-20-2008 |
| 20080293235 | COMPOUND WIREBONDING AND METHOD FOR MINIMIZING INTEGRATED CIRCUIT DAMAGE - A method is provided for creating a compound bond in a wire bonding process. The method includes forming a free air ball ( | 11-27-2008 |
| 20080293236 | METHOD OF MANUFACTURING CHIP INTEGRATED SUBSTRATE - There are provided the steps of connecting a chip component | 11-27-2008 |
| 20090053887 | WIREBOND PAD FOR SEMICONDUCTOR CHIP OR WAFER - In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps. | 02-26-2009 |
| 20090191702 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad. | 07-30-2009 |
| 20100048017 | BONDED STRUCTURE AND BONDING METHOD - An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon. | 02-25-2010 |
| 20100248470 | Method of manufacturing semiconductor device - A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion. | 09-30-2010 |
| 20100311234 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. A first bond of a first wire loop is formed. A wire is bonded through a ball to a lead or a chip electrode of a semiconductor chip to form a second bond of the first wire loop and a first bond of a second wire loop. A second bond of the second wire loop is formed. The ball provides a large bonding area, and thus, provides a strong bonding strength. | 12-09-2010 |
| 20110070729 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device, includes: preparing a semiconductor IC chip and an external electrode terminal which is positioned away from the semiconductor IC chip, wherein the semiconductor IC chip has first and second electrode pads thereon, the second electrode pad being positioned between the first electrode pad and the external electrode terminal; connecting the first electrode pad and the external electrode terminal by a loop-like wire; and pressing a portion of the loop-like wire toward the semiconductor IC chip, thereby connecting the portion of the loop-like wire with the second electrode pad. | 03-24-2011 |
| 20140045327 | Double Solid Metal Pad with Reduced Area - An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions. | 02-13-2014 |
| 20170236801 | SEMICONDUCTOR DEVICES AND PROCESSING METHODS | 08-17-2017 |
