| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438558000 |
From solid dopant source in contact with semiconductor region
| 51 |
| 438565000 |
From vapor phase
| 13 |
| 438548000 |
Plural dopants simultaneously in plural regions
| 7 |
| 438550000 |
Nonuniform heating | 5 |
| 20080227277 | Method of manufacturing semiconductor element - A method of manufacturing a semiconductor element includes implanting ions of a dopant having a large diffusion coefficient into a semiconductor to provide a doped layer; and irradiating the doped layer with a plurality of pulsed laser beams supplied by a plurality of laser irradiation devices to activate the doped layer and provide an activated doped layer. The activated doped layer may be one of a single doped layer or a plurality of successive doped layers which each have respective conduction types that are one of identical or different. Device breakage and failure of the manufactured semiconductor element due to heat induced during laser irradiation are substantially prevented by this method. | 09-18-2008 |
| 20090068825 | IMPLEMENTATION OF TEMPERATURE-DEPENDENT PHASE SWITCH LAYER FOR IMPROVED TEMPERATURE UNIFORMITY DURING ANNEALING - The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process. | 03-12-2009 |
| 20090176356 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES USING THERMAL GRADIENT-INDUCING FILMS - Methods for fabricating semiconductor devices using thermal gradient-inducing films are provided. One method comprises providing a substrate having a first region and a second region and forming a film overlying the second region and exposing the first region. The substrate is subjected to a thermal process wherein the film induces a predetermined thermal gradient between the first region and the second region. | 07-09-2009 |
| 20140162443 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface. | 06-12-2014 |
| 20140162444 | DIFFUSION SOURCES FROM LIQUID PRECURSORS - A method selectively diffuses dopants into a substrate wafer. The method comprises blanket depositing a doped liquid precursor including dopants on a surface of the substrate wafer to create a doped film on the surface of the substrate wafer, selectively forming a diffusion source in the doped film to selectively diffuse the dopants into the substrate wafer, and heating the doped film on the substrate wafer, wherein said heating the doped film diffuses the dopants from the doped film into the substrate wafer. | 06-12-2014 |
| 438549000 |
Single dopant forming plural diverse regions (e.g., forming regions of different concentrations or of different depths, etc.) | 3 |
| 20100167512 | Methods for Nanostructure Doping - Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure. | 07-01-2010 |
| 20130280898 | METHOD FOR FORMING A DOPANT PROFILE - A method is provided for forming a dopant profile based on a surface of a wafer-like semiconductor component with phosphorus as a dopant. The method includes the steps of applying a phosphorus dopant source onto the surface, forming a first dopant profile with the dopant source that is present on the surface, removing the dopant source, and forming a second dopant profile that has a greater depth in comparison to the first dopant profile. In order to form an optimized dopant profile, the dopant source is removed after forming the first dopant profile, and precipitates that are crystallized selectively on or in the surface from the precipitates Si | 10-24-2013 |
| 20140322906 | Method for Patterned Doping of a Semiconductor - A method for an improved doping process allows for improved control of doping concentrations on a substrate. The method may comprise printing a polymeric material on a substrate in a desired pattern; and depositing a barrier layer on the substrate with a liquid phase deposition process, wherein a pattern of the barrier layer is defined by the polymeric material. The method further comprises removing the polymeric material, and doping the substrate. The barrier layer substantially prevents or reduces doping of the substrate to allow patterned doping regions to be formed on the substrate. The method can be repeated to allow additional doping regions to be formed on the substrate. | 10-30-2014 |
| 438546000 |
Plural dopants in same region (e.g., through same mask opening, etc.) | 2 |
| 20110300697 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a method of fabricating a semiconductor device, including the steps of forming a diffusion preventing mask on a surface of a semiconductor substrate, applying a dopant diffusing agent containing a dopant of a first conductivity type or a second conductivity type onto the surface of the semiconductor substrate at a spacing from the diffusion preventing mask, and forming a dopant diffusion layer by diffusing the dopant from the dopant diffusing agent into the semiconductor substrate. | 12-08-2011 |
| 20140011347 | PROCESS FOR CONTACT DOPING - Provided is a process for modifying the chemical composition of a surface region of a material, employing rapid thermal processing (RTP) conditions. | 01-09-2014 |
| 438544000 |
To solid-state solubility concentration | 1 |
| 20100167510 | METHODS OF USING A SET OF SILICON NANOPARTICLE FLUIDS TO CONTROL IN SITU A SET OF DOPANT DIFFUSION PROFILES - A method of forming a multi-doped junction is disclosed. The method includes providing a first substrate and a second substrate. The method also includes depositing a first ink on a first surface of each of the first substrate and the second substrate, the first ink comprising a first set of nanoparticles and a first set of solvents, the first set of nanoparticles comprising a first concentration of a first dopant. The method further includes depositing a second ink on a second surface of each of the first substrate and the second substrate, the second ink comprising a second set of nanoparticles and a second set of solvents, the second set of nanoparticles comprising a second concentration of a second dopant. The method also includes placing the first substrate and the second substrate in a back to back configuration; and heating the first substrate and the second substrate in a first drive-in ambient to a first temperature and for a first time period. The method further includes exposing the first substrate and the second substrate in the back to back configuration to a deposition ambient, the deposition ambient comprising POCl | 07-01-2010 |
| Entries |
| Document | Title | Date |
|---|
| 20080206972 | DOPED NANOPARTICLE-BASED SEMICONDUCTOR JUNCTION - A doped semiconductor junction for use in an electronic device and a method for making such junction is disclosed. The junction includes a first polycrystalline semiconductor layer doped with donors or acceptors over a substrate such that the first doped semiconductor layer has a first polarity, the first layer including fused semiconductor nanoparticles; and a second layer in contact with the first semiconductor layer over a substrate to form the semiconductor junction. | 08-28-2008 |
| 20080220598 | Method for Dopant Diffusion - A method for controlling dopant diffusion is disclosed. Using certain control parameters that are not used in the prior art, the method provides an unprecedented measure of control over the dopant diffusion process. The control parameters include, among others, the size of the diffusion windows in the diffusion mask and the proximity of the diffusion windows to a dopant sink. In some embodiments, the diffusion process is conducted in an epi-reactor. | 09-11-2008 |
| 20080227276 | Silicon Substrate With Reduced Surface Roughness - The present disclosure provides a method for fabricating a semiconductor device including providing a semiconductor substrate comprising a first surface and a second surface, wherein at least one imaging sensor is located adjacent the first surface, activating a dopant layer in the semiconductor substrate adjacent the second surface using a localized annealing process, and etching the dopant layer | 09-18-2008 |
| 20080242067 | SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which is formed over a top of the heavily doped diffusion layer and contains impurities at a lower concentration than the heavily doped diffusion layer. | 10-02-2008 |
| 20080242068 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN layer is formed over the HfN layer and heat treatment is performed. Nitrogen diffuses from the MoN layer into the HfN layer in which nitrogen concentration is low and a work function is set by the HfN layer according to nitrogen concentration which depends on the nitrogen content of the HfN layer before the heat treatment and the amount of nitrogen that diffuses into the HfN layer. On the other hand, nitrogen hardly diffuses from the MoN layer into the HfN layer which originally has a certain nitrogen content, and a work function is set by the HfN layer according to nitrogen concentration in the HfN layer before the heat treatment. By controlling the nitrogen content of each layer and the amount of nitrogen that diffuses, a low-resistance metal gate electrode having a predetermined work function can be formed in each of the nMOS transistor formation region and the pMOS transistor formation region. | 10-02-2008 |
| 20080248638 | PROCESS FOR MANUFACTURING VOLTAGE-CONTROLLED TRANSISTOR - The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential. | 10-09-2008 |
| 20080268628 | N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PROFILE AND METHOD OF FORMING SAME - The disclosure relates to a method of forming an n-type doped active area on a semiconductor substrate that presents an improved placement profile. The method comprises the placement of arsenic in the presence of a carbon-containing arsenic diffusion suppressant in order to reduce the diffusion of the arsenic out of the target area during heat-induced annealing. The method may additionally include the placement of an amorphizer, such as germanium, in the target area in order to reduce channeling of the arsenic ions through the crystalline lattice. The method may also include the use of arsenic in addition to another n-type dopant, e.g. phosphorus, in order to offset some of the disadvantages of a pure arsenic dopant. The disclosure also relates to a semiconductor component, e.g. an NMOS transistor, formed in accordance with the described methods. | 10-30-2008 |
| 20090042378 | USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line. | 02-12-2009 |
| 20090087971 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION DIFFUSION - A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling. | 04-02-2009 |
| 20090130832 | SILICON SURFACE STRUCTURING METHOD - A method for the structuring of multicrystalline silicon substrate surfaces and emitter diffusion into said surfaces comprises the following steps: providing a texturing solution which comprises at least a portion of phosphoric acid, providing a semiconductor substrate with a surface to be structured, coating the surface to be structured with the texturing solution, heating the texturing solution to a heating temperature T | 05-21-2009 |
| 20090142911 | MASKING PASTE, METHOD OF MANUFACTURING SAME, AND METHOD OF MANUFACTURING SOLAR CELL USING MASKING PASTE - A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO | 06-04-2009 |
| 20100041220 | METHODS FOR UNIFORMLY OPTICALLY ANNEALING REGIONS OF A SEMICONDUCTOR SUBSTRATE - Methods for uniformly optically annealing regions of a semiconductor substrate and methods for fabricating semiconductor substrates using uniform optical annealing are provided. In accordance with an exemplary embodiment, a method for uniformly optically annealing a semiconductor substrate comprises the step of obtaining an optical reflectance of a first region of the semiconductor substrate. A second region of the semiconductor substrate is fabricated such that the optical reflectance of the second region is substantially equal to the optical reflectance of the first region, wherein the first region is not the second region. The semiconductor substrate is optically annealed. | 02-18-2010 |
| 20100048006 | PHOSPHOROUS-COMPRISING DOPANTS AND METHODS FOR FORMING PHOSPHOROUS-DOPED REGIONS IN SEMICONDUCTOR SUBSTRATES USING PHOSPHOROUS-COMPRISING DOPANTS - Phosphorous-comprising dopants, methods for forming phosphorous-doped regions in a semiconductor material, and methods for fabricating phosphorous-comprising dopants are provided. In one embodiment, a phosphorous-comprising dopant comprises a phosphorous source comprising a phosphorous-comprising salt, a phosphorous-comprising acid, phosphorous-comprising anions, or a combination thereof, an alkaline material, cations from an alkaline material, or a combination thereof, and a liquid medium. | 02-25-2010 |
| 20100087054 | METHOD FOR FORMING DEEP WELL OF POWER DEVICE - The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process to the first open region to form a first sub-doped region; removing the first patterned mask layer and the first sacrificial layer; forming an epitaxial layer on the substrate; forming a second sacrificial layer on the epitaxial layer; forming a second patterned mask layer on the second sacrificial layer exposing a second open region; performing a second doping process to the second open region to form a second sub-doped region; removing the second patterned mask layer; performing an annealing process to make the first and the second sub-doped regions form a deep well region; and removing the second sacrificial layer. | 04-08-2010 |
| 20100136774 | METHOD OF FABRICATING A DIODE - A method of fabricating a diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone, a weakly p-doped zone and a heavily p-doped zone. In the vertical direction, the weakly p-doped zone has a thickness of at least 25% and at most 50% of the thickness of the semiconductor body. | 06-03-2010 |
| 20100311230 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A PIN diode has an n | 12-09-2010 |
| 20110003464 | METHODS OF USING A SILICON NANOPARTICLE FLUID TO CONTROL IN SITU A SET OF DOPANT DIFFUSION PROFILES - A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface, and depositing an ink on the front substrate surface in an ink pattern, the ink comprising a set of nanoparticles and a set of solvents. The method further includes heating the substrate in a baking ambient to a first temperature of between about 200° C. and about 800° C. and for a first time period of between about 3 minutes and about 20 minutes in order to create a densified film ink pattern. The method also includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl | 01-06-2011 |
| 20110021012 | COMPOSITIONS FOR FORMING DOPED REGIONS IN SEMICONDUCTOR SUBSTRATES, METHODS FOR FABRICATING SUCH COMPOSITIONS, AND METHODS FOR FORMING DOPED REGIONS USING SUCH COMPOSITIONS - Compositions for forming doped regions in semiconductor substrates, methods for fabricating such compositions, and methods for forming doped regions using such compositions are provided. In one embodiment, a dopant-comprising composition comprises a conductivity-determining type impurity dopant, a silicate carrier, a solvent, and a moisture adsorption-minimizing component. In another embodiment, a dopant-comprising composition comprises a conductivity-determining type impurity dopant, a silicate carrier, a solvent, and a high boiling point material selected from the group consisting of glycol ethers, alcohols, and combinations thereof. The high boiling point material has a boiling point of at least about 150° C. | 01-27-2011 |
| 20110263110 | FILM-FORMING COMPOSITION - A film-forming composition for use in a coating diffusion method, capable of diffusing a dopant at a higher concentration, and further capable of concomitantly forming a silica-based coating film is provided. A film-forming composition for constituting a diffusion film provided for diffusing a dopant element into a silicon wafer, the film-forming composition including: (A) a polymeric silicon compound; (B) an oxide of the dopant element, or a salt including the dopant element; and (C) porogene. | 10-27-2011 |
| 20110287618 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR APPARATUS - Disclosed is a method of manufacturing a silicon carbide semiconductor apparatus which provides a smooth silicon carbide surface while maintaining a high impurity activation ratio. The method of manufacturing a silicon carbide semiconductor apparatus which forms an impurity region in the surface layer of a silicon carbide substrate includes the steps of implanting an impurity into the surface layer of the silicon carbide substrate, forming a carbon film on the surface of the silicon carbide substrate, preliminarily heating the silicon carbide substrate with the carbon film as a protective film, and thermally activating the silicon carbide substrate with the carbon film as a protective film. | 11-24-2011 |
| 20120003826 | METHODS AND COMPOSITIONS FOR DOPING SILICON SUBSTRATES WITH MOLECULAR MONOLAYERS - Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred. | 01-05-2012 |
| 20120058632 | METHODS OF FORMING A METAL CONTACT ON A SILICON SUBSTRATE - A method of forming a metal contact on a silicon substrate is disclosed. The method includes depositing a nanoparticle ink on a substrate surface in a pattern, the nanoparticle ink comprising set of nanoparticles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified nanoparticle layer with a nanoparticle layer thickness of greater than about 50 nm. The method further includes depositing an SiN | 03-08-2012 |
| 20120083104 | METHODS OF FORMING A FLOATING JUNCTION ON A SOLAR CELL WITH A PARTICLE MASKING LAYER - A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns. The method also includes exposing the substrate to a set of etchants for a third time period, wherein the front surface PSG layer and the rear surface PSG layer are substantially removed; depositing a front surface SiN | 04-05-2012 |
| 20120122306 | DIFFUSING AGENT COMPOSITION, AND METHOD FOR FORMING AN IMPURITY DIFFUSION LAYER - A diffusing agent composition contains a condensation product (A) and an impurity diffusion component (B). The condensation product (A) is a reaction product yielded by hydrolyzing an alkoxysilane. The impurity diffusion component (B) is a monoester or diester of phosphoric acid, or a mixture thereof. | 05-17-2012 |
| 20120225544 | Method for producing a semiconductor component - Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×10 | 09-06-2012 |
| 20120252196 | METHOD FOR FORMING ULTRA-SHALLOW DOPING REGIONS BY SOLID PHASE DIFFUSION - A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment. | 10-04-2012 |
| 20120276725 | METHODS OF SELECTIVELY FORMING METAL-DOPED CHALCOGENIDE MATERIALS, METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS, AND METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING SAME - Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material. A method of doping a chalcogenide material of a memory cell with at least one transition metal without using an etch or chemical mechanical planarization process to remove the transition metal from an insulative material of the memory cell is also disclosed, wherein the chalcogenide material is not silver selenide. | 11-01-2012 |
| 20130023113 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a MOSFET includes the steps of: introducing an impurity into a silicon carbide layer; forming a carbon layer in a surface layer portion of the silicon carbide layer having the impurity introduced therein, by selectively removing silicon from the surface layer portion; and activating the impurity by heating the silicon carbide layer having the carbon layer formed therein. | 01-24-2013 |
| 20130164923 | LOW VOLTAGE PNPN PROTECTION DEVICE - A low voltage protection device that includes a silicon substrate comprises an inner layer of a first dopant type. The device also includes a first outer layer of a second dopant type disposed adjacent a first surface of the inner layer and a second outer layer of the second dopant type disposed adjacent a second surface of the inner layer opposite the first surface. The device further includes a first mesa region disposed in a peripheral region of a first side of the low voltage protection device. The first mesa region includes a first area that includes a peripheral portion of a cathode of the low voltage protection device, the cathode formed by diffusing a high concentration of dopant species of the first type on a first surface of the silicon substrate, and a second area comprising a high concentration of diffused dopant species of the second type. | 06-27-2013 |
| 20130260545 | METHODS AND COMPOSITIONS FOR DOPING SILICON SUBSTRATES WITH MOLECULAR MONOLAYERS - Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred. | 10-03-2013 |
| 20130273725 | METHOD OF FABRICATING A STRUCTURED SEMICONDUCTOR SUBSTRATE - A method is provided for fabricating a structured semiconductor substrate including: i) depositing, on the surface of a semiconductor material, a sacrificial layer of material different from the semiconductor material. At step ii), the sacrificial layer, formed in step i) is etched at least in part so as to form sacrificial layer islets on the surface of the semiconductor material. The semiconductor material of step ii) is etched at least in part, in zones that are not protected by said islets, so as to form a structured semiconductor material, this step iii) being performed in the presence of oxygen so as to deposit an oxide layer on the surface of the semiconductor material. The sacrificial layer islets and the oxide layer are eliminated from the surface of the semiconductor material obtained in step iii), so as to form the structured substrate. | 10-17-2013 |
| 20130330918 | PATTERNED DOPING OF SEMICONDUCTOR SUBSTRATES USING PHOTOSENSITIVE MONOLAYERS - A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate. | 12-12-2013 |
| 20130344690 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, in a method of manufacturing a semiconductor device, a gate electrode material film is anisotropically etched using a mask having a predetermined pattern so as to form a first gate electrode on a first region, first dummy gates on the space area of the first region, a second gate electrode on a second region and second dummy gates on the space area of the second region. The first dummy gates have a first coverage and are disposed so as to surround the first gate electrode. The second dummy gates have a second coverage and are disposed so as to surround the second gate electrode. A first insulating film is anisotropically etched so as to form a first sidewall having a first thickness on the first gate electrode and a second sidewall having a second thickness larger than the first thickness on the second gate electrode. | 12-26-2013 |
| 20140120705 | INORGANIC PHOSPHATE CONTAINING DOPING COMPOSITIONS - A composition for doping semiconductor materials, such as silicon, may contain a) a solvent and a) an inorganic salt of a phosphor containing acid dispersed in the solvent. Also disclosed are doping methods using such composition as well as methods of making the doping composition. | 05-01-2014 |
| 20140199826 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes introducing an impurity into a SiC substrate, forming a mixed material layer, which is made from a resin and a fibrous carbon material, on a surface of the SiC material into which the impurity is introduced, performing heat treatment of the SiC substrate in which the mixed material layer is formed on the surface of the SiC substrate, and removing the mixed material layer after the heat treatment. | 07-17-2014 |
| 20140256123 | ELECTRICALLY ACTUATED DEVICE AND METHOD OF CONTROLLING THE FORMATION OF DOPANTS THEREIN - In an example of a method for controlling the formation of dopants in an electrically actuated device, a predetermined concentration of a dopant initiator is selected. The predetermined amount of the dopant is localized, via diffusion, at an interface between an electrode and an active region adjacent to the electrode. The dopant initiator reacts with a portion of the active region to form the dopants. | 09-11-2014 |
| 20140295655 | METHOD FOR FORMING THROUGH-SILICON VIA (TSV) WITH DIFFUSED ISOLATION WELL - A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance. | 10-02-2014 |
| 20140315376 | SYSTEM AND METHODS OF EMBEDDING MATERIAL IN A GLASS SUBSTRATE - A method for embedding a dopant into a glass substrate is provided. The method may include the steps of applying the dopant to a surface of the glass substrate, positioning the glass substrate adjacent to a catalyst such that the dopant is intermediate the catalyst and the glass substrate, heating the glass substrate to a first temperature, operating a directed thermal energy source so as to generate thermal energy incident upon the dopant, reducing the temperature of the glass substrate to a second temperature below the first temperature, and holding the glass substrate at the second temperature for at least a period of time. | 10-23-2014 |
| 20140322905 | METHOD OF FORMING THE BUFFER LAYER IN THE LTPS PRODUCTS - The present disclosure disclosed a method of forming the buffer layer in the LTPS products. The method comprises the following steps: heating the substrate to make the alkali metal ions diffuse to the surface of the glass; washing the substrate by acid to remove the alkali metal ions on the surface of the glass; forming the buffer layer on the glass which has been heated and washed by acid, wherein the material of the buffer layer is SiOx. The method of the present disclosure based on the design of the single buffer layer, it can greatly promote the capacity and can economize the gas. Furthermore, it can avoid the cross contamination of the different layers so as to promote characteristic of the element. | 10-30-2014 |
| 20150132930 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ANNEALING METHOD - A semiconductor device manufacturing method includes: amorphizing the impurity diffusion layer formation region; doping the impurity diffusion layer formation region of the semiconductor substrate with impurities; and performing an annealing treatment including lamp annealing in which a heating lamp is used and microwave annealing in which microwaves are irradiated, on the semiconductor substrate doped with the impurities, for activating the impurities. In addition to activation of the impurity, re-crystallization and removing of crystal defects also take place in the annealing treatment. | 05-14-2015 |
| 20150325442 | Formulations of Solutions and Processes for Forming a Substrate Including a Dopant - Formulations of solutions and processes are described to form a substrate including a dopant. In particular implementations, the dopant can include arsenic (As) or phosphorus (P). In an embodiment, a dopant solution is provided that includes a solvent and a dopant-containing molecule. In a particular embodiment, the solvent of the dopant solution can have a flashpoint that is at least 55° C. In some cases, the dopant-containing molecule can have a molecular weight that is no greater than about 300 g/mol. In other instances, a ratio of a concentration of a dopant-containing molecule relative to a concentration of a contaminant is no greater than about 1×10 | 11-12-2015 |
| 20160093510 | METHOD FOR PERFORMING ACTIVATION OF DOPANTS IN A GAN-BASE SEMICONDUCTOR LAYER - The method for performing activation of p-type dopants in a GaN-base semiconductor comprises a first step consisting in providing a substrate comprising (i) a GaN-base semiconductor material layer comprising p-type electric dopant impurities, (ii) a cap block devoid of any silicon-base compound, in contact with the semiconductor material layer, and (iii) a silicon-base covering layer covering the cap block. The method comprises a second heat treatment step at a temperature of more than 900° C. so as to activate the p-type electric dopant impurities in the semiconductor material layer. | 03-31-2016 |
