| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365233110 |
Plural clock signals
| 30 |
| 365233130 |
DDR (double data rate) memory
| 20 |
| 365233120 |
External clock signal modification
| 11 |
| 365233180 |
Burst mode signal
| 6 |
| 365233500 |
Transition detection | 5 |
| 20080298159 | SEMICONDUCTOR INTEGRATED CIRCUIT - An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant with the system interface specification and outputs the same to the controller. By converting the system interface specification and the memory interface specification to each other by an interface conversion macro, a common memory macro can be mounted on a semiconductor integrated circuit even when the system interface specification differs. Accordingly, when designing a system, the design verification time, evaluation time, and test time of the semiconductor integrated circuit can be reduced. As a result, the design time and design cost of the semiconductor integrated circuit can be reduced. | 12-04-2008 |
| 20090086566 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PERFORMING PAGE MODE OPERATION - A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal. | 04-02-2009 |
| 20090175115 | MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR ITS MANUFACTURING - Embodiments relates to a memory device, comprising a plurality of memory cells, said memory cells being addressable by a plurality of addresses, an interface for reading and/or writing data from a host system to said memory device, said interface comprising at least an address bus and a clock signal line, said address bus being configured to transmit a first part of an address at the leading edge of said clock signal and a second part of an address at the trailing edge of said clock signal. | 07-09-2009 |
| 20090190430 | NON-VOLATILE LATCH CIRCUIT FOR RESTORING DATA AFTER POWER INTERRUPTION - A nonvolatile latch circuit that exhibits improved the performance of a system is presented. The nonvolatile latch circuit is capable of storing all kinds of the states generated during the operation of the system as non-volatility information. The nonvolatile latch circuit is capable of restoring the previous state where of power is unexpectedly interrupted when the system is re-booting. The present invention includes an input control unit, a data control unit, a storage control unit, a clock control unit, a data transition detecting unit, and a data output unit. | 07-30-2009 |
| 20090274002 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PROCESSING ADDRESS AND COMMAND SIGNALS THEREOF - A semiconductor integrated circuit device includes an input unit configured to receive address and command signals, an internal address generator configured to output an internal address signal by adjusting a timing of the input address signal to correspond to a predetermined internal signal processing timing margin, and an internal command generator configured to output an internal command having a predetermined time difference from the internal address signal by adjusting a timing of the input command signal. | 11-05-2009 |
| 365233160 |
Write mode signal only | 4 |
| 20110158032 | CLOCK CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME - A clock control circuit is presented for reducing unnecessary current consumption. The clock control circuit includes a write enable signal generation unit and a clock enable signal generation unit. The write enable signal generation unit is configured to generate a first write enable signal, which is enabled during a predetermined time period after a write command is inputted, in response to first and second burst signals and a write signal including a pulse generated in response to the write command. The clock enable signal generation unit is configured to generate a clock enable signal, which is enabled during a write operation period, in response to the first write signal and the first write enable signal. | 06-30-2011 |
| 20110205832 | ON-DIE TERMINATION CIRCUIT, MEMORY DEVICE, MEMORY MODULE, AND METHOD OF OPERATING AND TRAINING AN ON-DIE TERMINATION - An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination impedance at the input/output data pin, the termination circuit having a switching device that selectively connects a termination impedance to the input/output data pin based on the presence of an asynchronous control signal (ACS), wherein the ACS is generated based on the presence of a memory WRITE command. The memory device may further comprise a training circuit comprising: an asynchronous signal delay configured to delay the signal path of the ACS signal to the termination circuit; and a comparing unit configured to compare a phase difference between the ACS signal and a reference signal, the comparing unit comprising a phase detector and a replica delay, wherein the replica delay is configured to delay the signal path of the ACS signal to the phase detector, and the phase detector is configured to output the phase difference as training result. | 08-25-2011 |
| 20110216621 | Synchronous Command-Based Write Recovery Time Auto Precharge Control - Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal. | 09-08-2011 |
| 20140003185 | ON-DIE TERMINATION CIRCUIT AND TERMINATION METHOD | 01-02-2014 |
| 365233170 |
Read mode signal only | 2 |
| 20080225630 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM - A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 09-18-2008 |
| 20100157719 | Circuit for generating read and signal and circuit for generating internal clock using the same - A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse signal and the delayed clock signal and generates a read detection signal having a pulse width corresponding to a certain clock, and a read end signal generating unit which receives a first signal, the delayed clock signal and the read detection signal and generates a read end signal. | 06-24-2010 |
| 365233150 |
Standby signal | 2 |
| 20110090755 | Memory Device Having Multiple Power Modes - A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command. | 04-21-2011 |
| 20120057424 | Memory Device Having Multiple Power Modes - A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command. | 03-08-2012 |
| 365233190 |
Common read and write mode signal | 2 |
| 20080253220 | Flexible RAM Clock Enable - A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. | 10-16-2008 |
| 20080304354 | Semiconductor memory device and method for reading/writing data thereof - A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control signal activated when an address for accessing a memory cell of a complementary bit line is inputted. The write selector is configured to selectively transmit data of a write path in response to the control signal. The read selector is configured to selectively transmit data of a read path in response to the control signal | 12-11-2008 |
| 365233140 |
Initiating signal | 2 |
| 20120155212 | SEMICONDUCTOR DEVICE GENERATING A CLOCK SIGNAL WHEN REQUIRED - Such a device is disclosed that includes a clock generation circuit generating a first clock signal and having an output node, and a drive circuit coupled to the output node of the clock generation circuit. The clock generation circuit outputs the first clock signal from the output node to the drive circuit in a clock output mode, fixes a potential of the output node to a first level in a first clock stop mode, and fixes the potential of the output node to a second level that is different from the first level in a second clock stop mode. | 06-21-2012 |
| 20140376326 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a clock pulse generating circuit suitable for outputting a command enable clock pulse when a predetermined command is input during a predetermined command-masking period, a command interface circuit suitable for outputting an internal command signal based on the command enable clock pulse and the command, and a target operating circuit suitable for performing an operation corresponding to the command based on the internal command signal. | 12-25-2014 |
| Entries |
| Document | Title | Date |
|---|
| 20080219083 | Semiconductor memory device and power control method thereof - A semiconductor memory device for saving power consumption and control method thereof are disclosed. The clock frequency on memory chips is dynamically adjusted to match the data transferring rate between the other units in computer system and the memory chips. A fill state of buffer and transferring rate on an input/output interface are detected by a monitor. A frequency adjuster increases or decrease the clock frequency on memory chips for keeping a good transferring rate and saving unnecessary power according to the monitor's detection. | 09-11-2008 |
| 20080225629 | MEMORY CONTROL DEVICE - A memory control device is disclosed that comprises a clock generator that generates a reference clock, a DLL circuit that receives the reference clock from the clock generator and outputs an output value indicative of a clock cycle of the reference clock, a delay setting circuit that receives the output value from the DLL circuit and outputs a delay setting value based on the output value according to at least one parameter, and plural delay elements that receive the delay setting value and introduce a delay responsive to the delay setting value. One or more of the delay elements receive input signals from corresponding one or more flip-flops driven by drive clocks generated by the clock generator, and send output signals to corresponding one or more output buffers that are to be connected to a memory. | 09-18-2008 |
| 20080239865 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature. | 10-02-2008 |
| 20080267000 | SINGLE-CLOCK, STROBELESS SIGNALING SYSTEM - A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path. | 10-30-2008 |
| 20080279034 | DATA OUTPUT CIRCUIT OF SYNCHRONOUS MEMORY DEVICE - A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal. | 11-13-2008 |
| 20080285375 | SEMICONDUCTOR DEVICE, MODULE INCLUDING THE SEMICONDUCTOR DEVICE, AND SYSTEM INCLUDING THE MODULE - A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock. | 11-20-2008 |
| 20080291770 | PLL CIRCUIT FOR INCREASING POTENTIAL DIFFERENCE BETWEEN GROUND VOLTAGE AND REFERENCE VOLTAGE OR POWER SOURCE VOLTAGE OF OSCILLATION CIRCUIT - A PLL circuit includes a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal; an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance with the frequency control signal, a power source voltage, and a predetermined reference voltage; and a bias control circuit, connected to the oscillation circuit, for increasing either the potential difference between the reference voltage of the oscillation circuit and a ground voltage or the potential difference between the power source voltage of the oscillation circuit and the ground voltage. A transistor in the oscillation circuit can operate in a saturation area, thereby operating the PLL circuit at a high speed with a low power source voltage, without being easily affected by a variation in the temperature or other process conditions. | 11-27-2008 |
| 20090016145 | Integrated Circuit Device With A Rom Matrix - A read only memory matrix in an integrated circuit contains data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells of the matrix. A differential sense amplifier has a first input coupled to a bit line, a second input coupled to a reference circuit and a control input for controlling activation and deactivation of amplification by the sense amplifier. A coupling circuit controllably permits charge sharing between a selectable one of the bit lines and the first input. A timing circuit is arranged to signal operation in a first phase, when the word lines have selected a row of the matrix, followed by a second phase. The timing circuit controls the coupling circuit to permit charge sharing between the input and the selectable one of the bit lines in the first phase. In the second phase the timing circuit controls the coupling circuit to prevent charge sharing, makes the reference circuit deactivate driving the reference voltage, and subsequently activates amplification by the differential sense amplifier. Preferably the timing circuit contains a dummy bit line and a trigger circuit for triggering the second phase when a potential swing on the dummy bit line exceeds a threshold value. | 01-15-2009 |
| 20090016146 | Latency counter, semiconductor memory device including the same, and data processing system - A latency counter includes: a frequency-dividing circuit that generates a plurality of divided clocks LCLKE and LCLKO of which the phases differ each other based on an internal clock LCLK; and frequency-divided counter circuits each of which counts a latency of an internal command based on the corresponding divided clocks LCLKE and LCLKO. Thus, the counting of the latency is performed based not on the internal clock LCLK itself but on the divided clocks LCLKE and LCLKO obtained by frequency-dividing the internal clock LCLK. Thus, even when a frequency of the internal clock LCLK is high, an operation margin can be sufficiently secured. | 01-15-2009 |
| 20090059713 | RAM MACRO AND TIMING GENERATING CIRCUIT THEREOF - A timing generating circuit generates a control clock ( | 03-05-2009 |
| 20090086565 | System and Method for Processing Signals in High Speed DRAM - A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided. | 04-02-2009 |
| 20090103391 | Memory clock generator having multiple clock modes - An integrated circuit | 04-23-2009 |
| 20090154285 | MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK - A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller. | 06-18-2009 |
| 20090161475 | SYSTEM FOR PROVIDING READ CLOCK SHARING BETWEEN MEMORY DEVICES - A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an external clock received by the external clock receiver and an external read clock received by the read clock receiver. The results of the synchronizing are utilized to refresh the internal read clock. The memory device also includes a mechanism, a read clock driver and a mode register fit. The mechanism is utilized to select between the external clock and the external read clock as input to the phase comparator. The read clock driver outputs the internal read clock generated at the memory device to a read clock output pin. The mode register bit controls the selection of the mechanism, the enabling and disabling of the read clock receiver and the enabling and disabling of the read clock driver. | 06-25-2009 |
| 20090190429 | System to Provide Memory System Power Reduction Without Reducing Overall Memory System Performance - A memory system is provided that provides memory system power reduction without reducing overall memory system performance. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth while the second operating frequency is independently decreased to reduce power being consumed by the set of memory devices. | 07-30-2009 |
| 20090201758 | Method for designing integrated circuit incorporating memory macro - An integrated circuit design method is provided in which memory instances are assigned to memory macros integrated within an integrated circuit. The integrated circuit design method includes: assigning a plurality of memory instances operating at the same operation frequency to a single memory macro; arranging a frequency multiplier which receives a first clock signal to generate a second clock signal through frequency multiplication of the first clock signal, and feeds the second clock signal to the plurality of memory instances; and arranging a control circuit which selects the memory instances in synchronization with the first clock signal. | 08-13-2009 |
| 20090231948 | Data output circuit having shared data output control unit - A data output circuit is provided which is capable of reducing a size and current consumption by commonly using a data output control unit for a plurality of data output units. The data output circuit includes a data output control unit for receiving an external clock signal and generate clock pulses having a pulse width, a first data output unit for outputting first data in synchronization with the clock pulse, and a second data output unit for outputting second data in synchronization with the clock pulses. | 09-17-2009 |
| 20090238025 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 09-24-2009 |
| 20090274001 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - Semiconductor memory device and method for operating the same includes a data output unit configured to output data in synchronization with a data output clock and a clock control unit configured to selectively transfer the data output clock to the data output unit under the control of a read command. | 11-05-2009 |
| 20090279378 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers. | 11-12-2009 |
| 20090285048 | COUNTER CIRCUIT, LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate. | 11-19-2009 |
| 20090290446 | Memory Word-line Tracking Scheme - A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter. | 11-26-2009 |
| 20090296514 | METHOD FOR ACCESSING A MEMORY CHIP - The present invention provides a method for accessing a memory chip. The method includes: positioning a plurality of first input pins and a plurality of second input pins on the memory chip; respectively inputting a plurality of row address signals into the plurality of first input pins, where a length of a row address command package of each row address signal corresponds to a plurality of clock periods of a clock signal, and the row address command package includes a plurality of row input commands; and respectively inputting a plurality of column address signals into the plurality of second input pins, where a length of a column address command package of each column address signal corresponds to a plurality of clock periods of the clock signal, and the column address command package includes a plurality of column input commands. | 12-03-2009 |
| 20090303827 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in synchronism the clock from the clock transfer portion, wherein the clock from the clock supply portion to the clock transfer portion swings at a current mode logic (CML) level. | 12-10-2009 |
| 20090316514 | Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 12-24-2009 |
| 20090323456 | MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed. | 12-31-2009 |
| 20090323457 | SYSTEM AND METHOD FOR SYNCHRONIZING ASYNCHRONOUS SIGNALS WITHOUT EXTERNAL CLOCK - One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device. | 12-31-2009 |
| 20100008176 | Write Leveling Of Memory Units Designed To Receive Access Requests In A Sequential Chained Topology - A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the frequency of the slower clock signal is determined based on the maximum fly-by delay (generally the delay between sending of a signal on the shared sequential path and the receipt at the memory unit in the sequence) that may be present in the memory system. For example, if the fly by delay can be M (an integer) times the time period of the clock signal during normal write operations, the slower clock signal may have a time period of M times that of the clock signal during write operation. | 01-14-2010 |
| 20100014377 | METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS - Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line. | 01-21-2010 |
| 20100027368 | READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY - A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off. | 02-04-2010 |
| 20100039878 | CIRCUIT AND METHOD FOR GENERATING DATA OUTPUT CONTROL SIGNAL FOR SEMICONDUCTOR INTEGRATED CIRCUIT - The data output control signal generating circuit include sa delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output enable signals. A column address strobe latency control multiplexer selects the output enable signal corresponding to column address strobe latency among the plurality of output enable signals, on the basis of the signal obtained by delaying the input signal by the phase difference between the clock and the delay locked loop clock, and outputs the selected signal as the data output control signal. | 02-18-2010 |
| 20100046314 | Memory Device Having a Read Pipeline and a Delay Locked Loop - A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation. | 02-25-2010 |
| 20100054073 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a clock inputting unit configured to receive a system clock and a data clock, a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock and determining a phase of the data division clock according to a division control signal, a phase dividing unit configured to generate a plurality of multiple-phase data division clocks each having a predetermined phase difference according to the data division clock, and a first phase detecting unit configured to detect a phase of the system clock based on a predetermined selection clock among the multiple-phase data division clocks, and generate the division control signal according to the detection result. | 03-04-2010 |
| 20100054074 | VOLTAGE GENERATION CIRCUIT AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME - A high voltage generation circuit includes a clock logic unit configured to generate a switch clock signal and a pump clock signal, that has a varying frequency, in response to an input signal, a high voltage unit configured to generate a high voltage in response to the pump clock signal, a high voltage switch configured to output a selection signal in response to the switch clock signal, and a switching element configured to transfer the high voltage, generated by the high voltage unit, to an output node in response to the selection signal. | 03-04-2010 |
| 20100091601 | CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT - A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device. | 04-15-2010 |
| 20100157718 | Configurable Latching for Asynchronous Memories - A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller's techniques for entering synchronous burst read mode. In some embodiments, the bit may selectively enable the memory to assume one of two synchronous burst read modes which are based on different arrangements of CLK and ADV# signals. | 06-24-2010 |
| 20100165781 | INTERNAL WRITE/READ PULSE GENERATING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - A control clock generating unit outputs a clock as a control clock when a column address strobe pulse is input and fixes the control clock to a specific level when an all bank precharge signal or a refresh signal is enabled. An internal pulse generating unit outputs an external write pulse or an external read pulse as an internal write pulse or an internal read pulse in response to the control clock. | 07-01-2010 |
| 20100165782 | MEMORY SYSTEM FOR SELECTIVELY TRANSMITTING COMMAND AND ADDRESS SIGNALS - A system includes a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of the memory modules. Each bus is adapted to transmit corresponding ones of the address signals, the command signals, and the select signals to the corresponding memory module. Each of the memory modules includes: a plurality of memory devices; and a register adapted to receive and buffer the corresponding command and address signals transmitted to the memory module, and adapted to transmit the buffered command signal to the memory devices which are to be accessed, in response to the corresponding select signal for accessing the memory devices. | 07-01-2010 |
| 20100226196 | DUTY CYCLE CORRECTOR PREVENTING EXCESSIVE DUTY CYCLE CORRECTION IN LOW-FREQUENCY DOMAIN - Provided is a duty cycle corrector including a low frequency detector detecting whether an input clock signal frequency is less than or greater than a predetermined frequency. If less than, a common mode control circuit controlling a common mode of a duty cycle correction amplifier amplifying the input clock signal is disabled. The duty cycle corrector may include a column address strobe (CAS) latency determination unit that determines whether a CAS latency is greater than or less than a predetermined value instead of the low frequency detector. | 09-09-2010 |
| 20100238756 | Self Reset Clock Buffer In Memory Devices - A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal. | 09-23-2010 |
| 20100302895 | ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK GENERATION - A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals. | 12-02-2010 |
| 20100302896 | Systems and methods for Stretching Clock Cycles in the Internal Clock Signal of a Memory Array Macro - Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal. In one embodiment, a local clock buffer in the memory array macro receives a regular periodic external clock signal and generates an internal clock signal. The local clock buffer includes a first signal path that has one or more faster-than-nominal components so that the first rising edge of the internal clock cycle occurs early than it would in a clock buffer with nominal components. When the memory array macro is active for a data access, the local clock buffer stretches a clock cycle of the internal clock signal so that the first and second half-periods of the internal clock cycle are each greater than the half-periods of the external clock signal. | 12-02-2010 |
| 20110013472 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit. | 01-20-2011 |
| 20110026355 | INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE INCORPORATING SAME - An interface circuit includes an input/output terminal, a clock generator, a set of multiple data ports, and a data port selector. The input/output terminal is connected to the external circuit to receive a data signal. The clock generator generates a series of multiple phase-shifted clock signals based on a basic clock signal. Each of the multiple data ports is connected to the input/output terminal and the clock generator to receive the data signal in synchronization with an associated one of the multiple phase-shifted clock signals to output a latched data signal. The data port selector is connected to the multiple data ports to check the multiple latched data signals to select one of the multiple data ports. The interface circuit loads the data signal through the selected data port in synchronization with the associated one of the multiple phase-shifted clock signals. | 02-03-2011 |
| 20110032787 | INPUT BUFFER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal. | 02-10-2011 |
| 20110044123 | CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT - A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device. | 02-24-2011 |
| 20110058442 | Semiconductor device having ODT function and data processing system including the same - To include an AL counter that outputs a second ODT signal after counting a clock signal by an additive latency after receiving a first ODT signal, and a counter control circuit that controls the AL counter such that the second ODT signal having the same logic value as a logic value of the first ODT signal at a time of shifting from an asynchronous mode to a synchronous mode is output during a period until when at least the clock signal is input by an additive latency after the shifting. With this configuration, an interruption of an CDT operation can be prevented without separately providing a CKE counter. Therefore, the circuit scale can be reduced and the power consumption can be also reduced. | 03-10-2011 |
| 20110058443 | LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit. | 03-10-2011 |
| 20110058444 | LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - A latency counter includes a counter circuit and a point-shift FIFO circuit. Latch circuits included in the point-shift FIFO circuit are divided into n groups having wired-OR outputs, and an output of a latch circuit that belongs to a group different from a current group is selected each time a count value is updated. Therefore, an output load is reduced compared to a case where outputs of all the latch circuits are bundled in a wired-OR connection. Further, because there is no need to provide a reset circuit corresponding to each wired-OR wire, it is possible to achieve a reduction in the circuit scale. Furthermore, because a waveform of a signal flowing in the wired-OR wire does not change in a state where internal commands are continuously created in n clock cycles, it is possible to achieve a reduction in the power consumption. | 03-10-2011 |
| 20110058445 | LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit. | 03-10-2011 |
| 20110141841 | SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING ON-DIE TERMINATION CIRCUIT AND ON-DIE TERMINATION METHOD - A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation. | 06-16-2011 |
| 20110158030 | METHOD AND APPARATUS FOR TUNING PHASE OF CLOCK SIGNAL - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 06-30-2011 |
| 20110199851 | MEMORY CONTROLLER, SEMICONDUCTOR STORAGE DEVICE, AND MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER AND THE SEMICONDUCTOR STORAGE DEVICE - A memory system includes a clock generation circuit, a memory device, and a controller. The memory device includes output circuits and a temperature sensor, the output circuits configured to output data at an output timing obtained based on a clock signal supplied from the clock generation circuit. The controller includes input circuits that receive the data outputted from the memory device at an input timing obtained based on a clock signal supplied from the clock generation circuit and a correction value setting circuit that adjusts the input timing based on a temperature value from the temperature sensor. | 08-18-2011 |
| 20110228626 | SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES - A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock. | 09-22-2011 |
| 20110249525 | Circuits, Systems and Methods for Adjusting Clock Signals Based on Measured Performance Characteristics - Circuits, systems, and related methods to measure a performance characteristic(s) associated with a semiconductor die and adjust a clock signal based on the measured performance characteristic(s) are provided. The adjusted clock signal can be used to provide a clock signal to a functional circuit provided in the semiconductor die to assure proper operation of the functional circuit while operating with performance, voltage, temperature (PVT) delay variations. In this regard, a performance monitoring circuit is provided in the semiconductor die that includes the functional circuit. As a result, the performance monitoring circuit may be exposed to similar delay variations as the functional circuit. The performance monitoring circuit is configured to measure a performance characteristic(s) associated with the semiconductor die. The performance characteristic(s) is used to adjust a clock signal to provide an adjusted clock signal to the functional circuit for proper operation based on the performance characteristic(s). | 10-13-2011 |
| 20110255362 | READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY - A system having a processor, a memory controller coupled to said processor, a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller and at least one of said DRAM chips comprising a clock synchronization circuit to receive a reference clock signal and to output a synchronized clock output signal. The system has a plurality of signal buses coupling the processor to the memory controller and the memory controller to said DRAM chips. The signal line conveys signals from said memory controller to said clock synchronization circuit to turn on and off the clock synchronization circuit according to control logic. A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off. | 10-20-2011 |
| 20120044780 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data. | 02-23-2012 |
| 20120120754 | Semiconductor device including latency counter - For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density. | 05-17-2012 |
| 20120147692 | SEMICONDUCTOR DEVICE OUTPUTTING READ DATA IN SYNCHRONIZATION WITH CLOCK SIGNAL - A semiconductor device is provided with a clock output control circuit which supplies a long-period clock signal having a period longer than an internal clock signal within an active period and supplies the internal clock signal within a read period subsequent to the active period, a clock transfer circuit which transfers the internal clock signal and the long-period clock signal outputted from the clock output control circuit, a data input/output terminal, and an input/output circuit which outputs read data to the data input/output terminal in synchronization with the internal clock signal having been transferred by the clock transfer circuit. | 06-14-2012 |
| 20120250445 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal. | 10-04-2012 |
| 20120269023 | SYSTEM WITH CONTROLLER AND MEMORY - According to the system of the present invention, data (DQ) signals are outputted/received between a controller | 10-25-2012 |
| 20120281493 | Apparatus for Memory Interface Configuration and Associated Methods - An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit. | 11-08-2012 |
| 20120327736 | Data sampling devices - Designs of a sampling controller working with memory chips are described. The designs enable a memory chip to work in high frequency clocks, resulting in high data throughput rate. A data sampling device includes a memory chip and a sampling controller. The sampling controller includes an asynchronous data memory. A data writing port of the asynchronous data memory receives a clock signal and employs the clock signal as a writing clock to store the sampling data into an internal memory and activate a data reading port thereof to read and output the sampling data. | 12-27-2012 |
| 20130039142 | INPUT BUFFER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal. | 02-14-2013 |
| 20130039143 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data window is synchronized with the edge of the source clock in response to a training output command, and a second data input/output unit configured to receive a recovery information training data, whose data window is scanned based on the edge of the source clock, in response to the training input command, and output a data in a state where an edge of a data window is synchronized with the edge of the source clock in response to the training output command. | 02-14-2013 |
| 20130135956 | SEMICONDUCTOR DEVICE, A PARALLEL INTERFACE SYSTEM AND METHODS THEREOF - A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line. | 05-30-2013 |
| 20130142003 | DUAL CLOCK EDGE TRIGGERED MEMORY - A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock. | 06-06-2013 |
| 20130163366 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation. | 06-27-2013 |
| 20130223179 | DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A delay locked loop (DLL) circuit having improved noise characteristics. The DLL circuit includes a first divider for generating a first divided signal by dividing an external clock; a second divider for generating a second divided signal by dividing an internal clock; a phase detector for detecting a phase difference between the first divided signal and the second divided signal; and an adjusting unit for synchronizing the internal clock and the external clock, based on the phase difference. | 08-29-2013 |
| 20130286765 | CHANNEL SKEWING - Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels. | 10-31-2013 |
| 20130294186 | PHASE-LOCKED LOOP AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME, AND TEST SYSTEM INCLUDING THE INTEGRATED CIRCUIT CHIP - A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock. | 11-07-2013 |
| 20140078852 | SEMICONDUCTOR DEVICE INCLUDING LATENCY COUNTER - For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density. | 03-20-2014 |
| 20140112089 | INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO CHANGE A CLOCK SIGNAL FREQUENCY WHILE A DATA SIGNAL IS VALID - Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid. | 04-24-2014 |
| 20140241102 | DUAL CLOCK EDGE TRIGGERED MEMORY - A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock. | 08-28-2014 |
| 20140247683 | SEMICONDUCTOR DEVICE HAVING A CONTROL CHIP STACKED WITH A CONTROLLED CHIP - A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit. | 09-04-2014 |
| 20140247684 | Semiconductor Device - A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips. | 09-04-2014 |
| 20140369153 | DATA STROBE CONTROL DEVICE - A data strobe control device is disclosed, which relates to a technology for controlling a data write path of a semiconductor memory device. The data strobe control device includes: a plus-mode controller configured to output a first control signal for controlling a first mode and a plus on-the-fly signal upon receiving a plus-mode signal and an on-the-fly signal; an on-the-fly controller configured to output a second control signal for controlling a second mode according to the on-the-fly signal and an operation signal; a path controller configured to latch an address in response to the second control signal during the second mode, latch the address in response to the first control signal during the first mode, and accordingly output an address latch signal; and a strobe pulse generator configured to output a strobe control signal synchronized with a control clock signal in response to the address latch signal and a burst length signal. | 12-18-2014 |
| 20140376325 | SEMICONDUCTOR DEVICE HAVING A REDUCED FOOTPRINT OF WIRES CONNECTING A DLL CIRCUIT WITH AN INPUT/OUTPUT BUFFER - An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance. | 12-25-2014 |
| 20150043298 | ELECTRONIC DEVICE - To alleviate the effect of undesired signal reflection in a branch wiring, even when the length of a branch path branched from a main wiring of a fly-by topology is long. | 02-12-2015 |
| 20150049571 | MEMORY CONTROL DEVICE, CONTROL METHOD OF MEMORY CONTROL DEVICE, INFORMATION PROCESSING APPARATUS - A set value retaining register stores therein, in an associated manner, control information on a memory and a clock frequency that is supplied to the memory. A memory access control circuit determines whether control information associated with the specified clock frequency is present in the set value retaining register. When the memory access control circuit determines that the control information associated with the specified clock frequency is not present in the set value retaining register, a memory tuning circuit decides control information that is associated with the specified clock frequency. When the memory access control circuit determines that the control information associated with the specified clock frequency is not present in the set value retaining register, a data transmission/reception module controls the memory on the basis of the control information decided by the memory tuning circuit. | 02-19-2015 |
| 20150098296 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM WITH THE SAME - A semiconductor device includes a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock; and a delay amount information provision unit suitable for providing delay amount information corresponding to a phase difference between the first internal clock and the second internal clock to an external device. | 04-09-2015 |
| 20150098297 | TIMING-DRIFT CALIBRATION - The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device. | 04-09-2015 |
| 20150124549 | SEMICONDUCTOR DEVICES - The semiconductor device includes a pulse width comparator suitable for generating an internal pulse signal having the same pulse width as an output pulse signal whose pulse width is controlled by first and second control signals during a predetermined period and suitable for generating first and second digital signals and a comparison pulse signal from the internal pulse signal according to a delay time which is set by the first and second control signals, an output pulse signal generator suitable for retarding the comparison pulse signal by the delay time determined by first and second control signals to generate the output pulse signal, and a control signal generator suitable for generating the first and second control signals which are sequentially enabled in response to pulses of the output pulse signal. | 05-07-2015 |
| 20150131398 | TIMING-DRIFT CALIBRATION - The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device. | 05-14-2015 |
| 20150302909 | SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD OF THE SAME - A semiconductor memory apparatus includes a delay control portion configured to generate a plurality of control signals by performing subtraction operation on a CL information and an AL information; and a delay portion configured to decide a delay amount, delay an input signal by the delay amount, and output the delayed input signal as a delay signal in response to the plurality of control signals. | 10-22-2015 |
| 20150325277 | CHANNEL SKEWING - Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels. | 11-12-2015 |
| 20150332747 | Methods of and Apparatus for Determining Unique Die Identifiers for Multiple Memory Die Within a Common Package - Respective die IDs are determined for a plurality of memory die commonly packaged as a memory device based on their respective Unique Identifiers (“UIDs”). An external controller initiates an internal Die ID (“DID”) determination process in which each die eventually asserts a signal on its inter-die signaling pin after a number of clocks as determined by its UID, and assigns itself a Die ID based on the number of signals asserted by other die prior to its own signaling response. Each die keeps track of the number of signals asserted by the other die prior to its own signaling response, as well as, optionally, the total number of signals on the signaling pin to determine the package die count for the device. | 11-19-2015 |
| 20150333740 | INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY - Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples. | 11-19-2015 |
| 20150365080 | System and Method for a Pulse Generator - According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input. | 12-17-2015 |
| 20150372683 | DLL CIRCUIT AND SEMICONDUCTOR DEVICE - In accordance with disclosed embodiments, a DLL circuit includes a variable frequency division circuit that uses a variable frequency division ratio to frequency-divide a first clock signal to generate first and second frequency-divided clock signals, a grain size change circuit that changes the count width in synchronization with the first frequency-divided clock signal, a counter circuit that updates the count value in accordance with the count width in synchronization with the second frequency-divided clock signal, and a variable delay circuit that delays the first clock signal on the basis of a delay amount that is in accordance with the count value, thereby generating a second clock signal. When the relationship in magnitude between the phase difference between the first and second clock signals and a predetermined value becomes inverse just after the updating of the count value, the grain size change circuit changes the count width, and the variable frequency division circuit sets the frequency division ratio of the second frequency-divided clock signal being greater than that of the first frequency-divided clock signal. | 12-24-2015 |
| 20160104520 | CLOCK SIGNAL PROCESSOR AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME - A clock signal processor includes a duty cycle corrector, a switch point calculator, and a multiplexer. The duty cycle corrector generates a second clock signal by modifying a duty cycle of a first clock signal. The switch point calculator activates a switch signal at an end of a latency period in which a read command is provided to a non-volatile memory device and an invalid data is read from the non-volatile memory device. The multiplexer outputs one of the first and second clock signals as a third clock signal based on the switch signal. | 04-14-2016 |
| 20160111137 | Addressing, Command Protocol, and Electrical Interface for Non-volatile Memories Utilized in Recording Usage Counts - A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is configured such that following reception of a command and upon encountering a first condition while processing the command, the memory module limits a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time for indicating an occurrence of the first condition. | 04-21-2016 |
| 20170236567 | SYSTEMS AND METHODS FOR INDIVIDUALLY CONFIGURING DYNAMIC RANDOM ACCESS MEMORIES SHARING A COMMON COMMAND ACCESS BUS | 08-17-2017 |
